JPH1197613A - Ic package - Google Patents

Ic package

Info

Publication number
JPH1197613A
JPH1197613A JP25545997A JP25545997A JPH1197613A JP H1197613 A JPH1197613 A JP H1197613A JP 25545997 A JP25545997 A JP 25545997A JP 25545997 A JP25545997 A JP 25545997A JP H1197613 A JPH1197613 A JP H1197613A
Authority
JP
Japan
Prior art keywords
signal group
package
noise
signals
driving unit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP25545997A
Other languages
Japanese (ja)
Other versions
JP3507300B2 (en
Inventor
Yoshihito Harada
義仁 原田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Canon Inc
Original Assignee
Canon Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Canon Inc filed Critical Canon Inc
Priority to JP25545997A priority Critical patent/JP3507300B2/en
Priority to US09/153,456 priority patent/US6512680B2/en
Publication of JPH1197613A publication Critical patent/JPH1197613A/en
Application granted granted Critical
Publication of JP3507300B2 publication Critical patent/JP3507300B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3431—Leadless components
    • H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components

Landscapes

  • Structure Of Printed Boards (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PROBLEM TO BE SOLVED: To avoid causing nonconformities due to noise, etc., by forming an allotting pattern which divides signals in groups of signals susceptible for or easy to emit noises and signals for transferring heavy currents. SOLUTION: Analog blocks including AD converters 22, DA converters 23, oscillator circuits OSC 24, etc., are required to be highly accurate and have high impedances which are extremely susceptible to external noises. Communication port COM 27, high-speed clock terminals CLK 28 and PWM 29 are for signal groups having comparatively high frequencies among digital signals and hence tend to emit noises. A driver DR 30, power source PS 33, etc., are terminals for transferring comparatively heavy currents and hence tend to generate and emit a noise, if its current path includes a wiring resistance. This eliminates the disadvantages resulting from many capacitive couplings that the ball grid array package essentially has, thus avoiding generation of noises due to crosstalks.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は、ＩＣパッケージに
係り、特にボールグリッドアレイパッケージ（以下ＢＧ
Ａパッケージと略称する）に関するものである。The present invention relates to an IC package, and more particularly to a ball grid array package (hereinafter referred to as BG).
A package).

【０００２】[0002]

【従来の技術】近年、ＩＣ等の多ピン化、小サイズ化の
流れの中で、ＳＳＯＰやＱＦＰ等の表面実装パッケージ
における狭ピッチ化がますます進んできている。2. Description of the Related Art In recent years, in the trend of increasing the number of pins and reducing the size of ICs, the pitch of surface mounting packages such as SSOPs and QFPs has been increasingly narrowed.

【０００３】特に、狭ピッチ化の一つとして例えば０．
５ｍｍのクワッドフラットパッケージ（以下ＱＦＰと略
称する）がハンディ機器製品に多用されている。[0003] In particular, as one of the methods for narrowing the pitch, for example, 0.
A 5 mm quad flat package (hereinafter abbreviated as QFP) is frequently used for handy device products.

【０００４】しかしながら、実装コストを考えるとこれ
以上の狭ピッチ化には実装装置、実装材料、実装管理と
いった種々の面から限界がきており、多ピン化に対する
回答としてパッケージのボディサイズを大きくすること
なく解決する方法、すなわち従来の１次元的なピン配列
から２次元的なピン配列としてのピングリッドアレイ
（以下ＰＧＡと略称する）やボールグリッドアレイ（以
下ＢＧＡと略称する）が採用されている。特にＰＧＡは
大きさというよりは多ピン化に対する単純な回答として
早くからソケットが利用され、パソコンのＣＰＵやゲー
トアレイ等に多用されている。However, in view of mounting costs, further narrowing of the pitch is limited in various aspects such as mounting devices, mounting materials, and mounting management. As a response to increasing the number of pins, it is necessary to increase the package body size. For example, a pin grid array (hereinafter abbreviated as PGA) or a ball grid array (hereinafter abbreviated as BGA) as a two-dimensional pin array instead of a conventional one-dimensional pin array is adopted. In particular, PGA has been used from early on as a simple answer to the increase in the number of pins rather than the size, and is widely used for CPUs, gate arrays, and the like of personal computers.

【０００５】一般にＰＧＡは多ピン、高速のデジタル信
号を扱うものが多く、そのパッケージは高価なものが多
い。一方、ＢＧＡはＰＧＡと異なり、まず表面実装用の
パッケージでしかもフレキシブルプリント基板を含むプ
リント基板等にチップを載せ、裏面にハンダボールを格
子状に比較的粗いピッチで配している。したがって、粗
いピッチにも拘らずパッケージサイズの割りに多ピンが
確保でき、またハンダボールによる自己位置修正効果所
謂セルフアライメント効果で比較的ローコストの実装が
可能である。In general, many PGAs handle multi-pin, high-speed digital signals, and their packages are often expensive. On the other hand, the BGA is different from the PGA in that a chip is first mounted on a printed circuit board or the like including a flexible printed circuit board in a package for surface mounting, and solder balls are arranged on the back surface in a grid pattern at a relatively coarse pitch. Therefore, despite the coarse pitch, a large number of pins can be secured for the package size, and mounting at a relatively low cost can be achieved by the self-alignment effect of the solder ball, that is, the self-alignment effect.

【０００６】[0006]

【発明が解決しようとする課題】しかしながら、ＢＧＡ
は平面的（２次元的）なパッド配置であるため、多層基
板のマザーボードで受けることが前提になるが、それで
も狭い領域に高密度のパッドを配するため、互いの信号
間でのクロストークが増え、また配線をマザーボード内
で引き出す際にも引き出し線同士の立体交差による容量
結合により信号の電気的漏洩である所謂クロストークが
増大する。However, the BGA
Is a planar (two-dimensional) pad arrangement, so it is assumed that it will be received by a multi-layer board motherboard. However, since high-density pads are arranged in a narrow area, crosstalk between signals will occur. Also, when wires are drawn out from the motherboard, so-called crosstalk, which is electrical leakage of signals, increases due to capacitive coupling due to three-dimensional crossing between the lead wires.

【０００７】本出願に係る第１の発明の目的は、デジタ
ルとアナログ混在のＩＣを多ピンであるにも拘らず実装
コストの安価なＢＧＡパッケージに入れても、ノイズ等
で不具合が生じないようにすることにある。An object of the first invention according to the present application is to prevent noise and other problems from occurring even when a digital and analog mixed IC is placed in a BGA package with a low mounting cost despite having many pins. It is to make.

【０００８】本出願に係る第２の発明の目的は、ノイズ
に弱い信号群が不具合となるのを防止することにある。It is an object of a second invention according to the present application to prevent a signal group susceptible to noise from becoming defective.

【０００９】本出願に係る第３の発明の目的は、ＡＤ変
換器、ＤＡ変換器、発振回路等の信号群が不具合となる
のを防止することにある。An object of a third invention according to the present application is to prevent a signal group of an AD converter, a DA converter, an oscillation circuit and the like from becoming defective.

【００１０】本出願に係る第４の発明の目的は、他の信
号群に対しノイズを放出し易い信号群による悪影響を防
止することにある。It is an object of a fourth invention according to the present application to prevent an adverse effect of a signal group that easily emits noise on another signal group.

【００１１】本出願に係る第５の発明の目的は、高速ク
ロック、ＰＷＭ等の信号群による他の信号群の不具合を
防止することにある。An object of a fifth invention according to the present application is to prevent a problem of another signal group caused by a signal group such as a high-speed clock and PWM.

【００１２】本出願に係る第６の発明の目的は、高抵抗
部の電位差の出現に伴うノイズの発生等を防止すること
にある。[0012] It is an object of a sixth invention according to the present application to prevent generation of noise or the like due to appearance of a potential difference in a high resistance portion.

【００１３】本出願に係る第７の発明の目的は、電源、
グランド、アクチュエータ駆動部、発光素子駆動部等の
信号群によるノイズの発生等を防止することにある。A seventh object of the present invention is to provide a power supply,
An object of the present invention is to prevent generation of noise due to a signal group of a ground, an actuator driving unit, a light emitting element driving unit, and the like.

【００１４】本出願に係る第８の発明の目的は、両面基
板のマザーボードでの高抵抗部の電位差の出現に伴うノ
イズの発生等を防止することにある。It is an object of an eighth invention according to the present application to prevent the occurrence of noise or the like due to the appearance of a potential difference of a high-resistance portion on a motherboard of a double-sided board.

【００１５】本出願に係る第９の発明の目的は、多層マ
ザーボードに実装した電源、グランド、アクチュエータ
駆動部、発光素子駆動部等の信号群によるノイズの発生
等を防止することにある。An object of a ninth invention according to the present application is to prevent generation of noise or the like due to a signal group of a power supply, a ground, an actuator driving unit, a light emitting element driving unit, etc. mounted on a multilayer motherboard.

【００１６】本出願に係る第１０の発明の目的は、ハン
ダボールによるセルフアライメント効果で比較的ローコ
ストの実装を可能とし、且つＢＧＡが本来もっている容
量結合の多さによるデメリットを排除し、クロストーク
によるノイズの発生を防止することにある。An object of a tenth invention according to the present application is to enable mounting at a relatively low cost by the self-alignment effect of a solder ball, to eliminate disadvantages due to a large capacity coupling inherent in a BGA, and to reduce crosstalk. The purpose of the present invention is to prevent the generation of noise due to noise.

【００１７】[0017]

【課題を解決するための手段】本出願に係る第１の発明
の目的を実現する構成としては、請求項１記載のよう
に、ＩＣ素子を内包し、前記ＩＣ素子に対する信号の入
出力を複数のパッドを介して行うＩＣパッケージにおい
て、信号群をノイズに弱い信号群、ノイズを放出し易い
信号群、大電流をやりとりする信号群等の複数の群に分
割し、且つ群相互を隔離するように割付配設パターン化
した。As a configuration for realizing the object of the first invention according to the present invention, an IC element is included and a plurality of signal inputs / outputs to / from the IC element are provided. In the IC package performed through the pad, the signal group is divided into a plurality of groups such as a signal group which is susceptible to noise, a signal group which easily emits noise, and a signal group which exchanges a large current, and the groups are isolated from each other. The layout pattern has been assigned.

【００１８】上記した構成によれば、多ピン化に適合
し、実装コストも比較的安価なＢＧＡをデジタル・アナ
ログ混在のＩＣに採用しても、そのピン配置に工夫をこ
らすことによってＢＧＡが本来もっている容量結合の多
さによるデメリットを排除し、クロストークによるノイ
ズの発生を防止することができる。According to the above-described configuration, even if a BGA which is compatible with the increase in the number of pins and has a relatively low mounting cost is adopted for a digital / analog mixed IC, the BGA is originally designed by devising the pin arrangement. Disadvantages due to the large amount of capacitive coupling can be eliminated, and generation of noise due to crosstalk can be prevented.

【００１９】また、ＢＧＡ基板内での配線の置換が比較
的容易にできるため、この手法は一層現実的となる。Further, since the replacement of the wiring in the BGA substrate can be made relatively easily, this method becomes more practical.

【００２０】本出願に係る第２の発明の目的を実現する
構成としては、請求項２記載のように、前記ノイズに弱
い信号群をパッケージの外周部またはコーナー部のパッ
ドに割り付けることをとした。As a configuration for realizing the object of the second invention according to the present application, as set forth in claim 2, the group of signals susceptible to noise is allocated to pads on the outer peripheral portion or the corner portion of the package. .

【００２１】上記した構成によれば、例えばＢＧＡ内の
ＩＣのパッドレイアウトによって割付配設パターン化を
容易に実現することができ、ノイズに弱い信号群が不具
合となるのを未然に回避できる。According to the above-described configuration, for example, it is possible to easily realize the allocation and arrangement pattern by the pad layout of the IC in the BGA, and it is possible to prevent a signal group susceptible to noise from becoming defective.

【００２２】本出願に係る第３の発明の目的を実現する
構成としては、請求項３記載のように、前記ノイズに弱
い信号群は、ＡＤ変換器、ＤＡ変換器、発振回路等の信
号群であることとした。In a configuration for realizing the object of the third invention according to the present application, as described in claim 3, the signal group that is weak to noise is a signal group of an AD converter, a DA converter, an oscillation circuit, and the like. It was decided.

【００２３】上記した構成によれば、ＡＤ変換器、ＤＡ
変換器、発振回路等の信号群が不具合となるのを未然に
回避できる。According to the above configuration, the AD converter, the DA
It is possible to prevent a signal group such as a converter and an oscillation circuit from becoming defective.

【００２４】本出願に係る第４の発明の目的を実現する
構成としては、請求項４記載のように、前記ノイズを放
出し易い信号群をパッケージの外周部またはコーナー部
のパッドに割り付けることとした。According to a fourth aspect of the present invention, a signal group that easily emits noise is allocated to pads on an outer peripheral portion or a corner portion of a package. did.

【００２５】上記した構成によれば、他の信号群に対し
ノイズを放出し易い信号群による悪影響を未然に回避す
ることができる。According to the above-described configuration, it is possible to avoid the adverse effect of a signal group that easily emits noise to another signal group.

【００２６】本出願に係る第５の発明の目的を実現する
構成としては、請求項５記載のように、前記ノイズを放
出し易い信号群は、高速クロック、ＰＷＭ等の信号群で
あることを特徴とした。According to a fifth aspect of the present invention, a signal group that easily emits noise is a signal group such as a high-speed clock and a PWM signal. Features.

【００２７】上記した構成によれば、高速クロック、Ｐ
ＷＭ等の信号群による他の信号群の不具合を未然に回避
できる。According to the above configuration, the high-speed clock, P
Problems of other signal groups due to signal groups such as WM can be avoided beforehand.

【００２８】本出願に係る第６の発明の目的を実現する
構成としては、請求項６記載のように、大電流をやりと
りする信号群をパッケージの外周部またはコーナー部の
パッドに割り付けることとした。As a configuration for realizing the object of the sixth invention according to the present application, as set forth in claim 6, a group of signals for exchanging a large current is allocated to pads on an outer peripheral portion or a corner portion of a package. .

【００２９】上記した構成によれば、従来のスルーホー
ルを通過させた場合のように高抵抗部の電位差の出現に
伴うノイズの発生等を未然に回避できる。According to the above-described configuration, it is possible to prevent the occurrence of noise due to the appearance of the potential difference in the high-resistance portion as in the case of passing through a conventional through hole.

【００３０】本出願に係る第７の発明の目的を実現する
構成としては、請求項７記載のように、前記大電流をや
りとりする信号群は、電源、グランド、アクチュエータ
駆動部、発光素子駆動部等の信号群であることとした。According to a seventh aspect of the present invention, a signal group for exchanging a large current includes a power supply, a ground, an actuator driving unit, and a light emitting element driving unit. And so on.

【００３１】上記した構成によれば、電源、グランド、
アクチュエータ駆動部、発光素子駆動部等の信号群によ
るノイズの発生等を未然に回避できる。According to the above configuration, the power supply, the ground,
Generation of noise or the like due to a signal group of the actuator driving unit, the light emitting element driving unit, and the like can be avoided.

【００３２】本出願に係る第８の発明の目的を実現する
構成としては、請求項８記載のように、前記大電流をや
りとりする信号群を割り付ける際に、多層マザーボード
に実装した時にマザーボードの第１層である部品実装面
から引き出せるパッドに割り付けることとした。As a configuration for realizing the object of the eighth invention according to the present application, as described in claim 8, when allocating the signal group for exchanging the large current, the signal group of the motherboard when mounted on a multilayer motherboard is assigned. The pads are assigned to pads that can be pulled out from the component mounting surface, which is one layer.

【００３３】上記した構成によれば、両面基板のマザー
ボードでの大電流をやりとりする信号群のパッド割り付
けパターンを種々に工夫することで高抵抗部の電位差の
出現に伴うノイズの発生等を未然に回避することができ
る。According to the above-described configuration, variously devised pad assignment patterns of a signal group for exchanging a large current in the motherboard on the double-sided board can prevent the occurrence of noise due to the appearance of a potential difference in the high-resistance portion. Can be avoided.

【００３４】本出願に係る第９の発明の目的を実現する
構成としては、請求項９記載のように、請求項８におけ
る大電流をやりとりする信号群としては、電源、グラン
ド、アクチュエータ駆動部、発光素子駆動部等の信号群
が含まれることとした。According to a ninth aspect of the present invention, a signal group for exchanging a large current according to the ninth aspect includes a power supply, a ground, an actuator driver, A signal group of a light emitting element driving unit and the like is included.

【００３５】上記した構成によれば、多層マザーボード
に実装した電源、グランド、アクチュエータ駆動部、発
光素子駆動部等の信号群によるノイズの発生等を未然に
回避できる。According to the above-described configuration, it is possible to prevent the occurrence of noise or the like due to a signal group of a power supply, a ground, an actuator driving unit, a light emitting element driving unit, and the like mounted on the multilayer motherboard.

【００３６】本出願に係る第１０の発明の目的を実現す
る構成としては、請求項１０記載のように、請求項１乃
至９におけるＢＧＡとしては、全格子、中空方陣タイプ
を含み、ＣＰＳ等の小型タイプのＢＧＡサイズを含むこ
とを特徴とした。As a structure for realizing the object of the tenth invention according to the present application, as described in claim 10, the BGA in claims 1 to 9 includes a full lattice, a hollow square type, and a CPS or the like. It is characterized by including a small BGA size.

【００３７】上記した構成によれば、粗いピッチでも多
ピンが確保できるハンダボールによるセルフアライメン
ト効果で比較的ローコストの実装が可能となると同時
に、ＢＧＡが本来もっている容量結合の多さによるデメ
リットを排除し、クロストークによるノイズの発生を防
止することができる。According to the above-described structure, the self-alignment effect of the solder ball that can secure a large number of pins even at a coarse pitch enables relatively low-cost mounting, and at the same time, eliminates disadvantages due to the inherently large capacity coupling of the BGA. However, the generation of noise due to crosstalk can be prevented.

【００３８】[0038]

【発明の実施の形態】BEST MODE FOR CARRYING OUT THE INVENTION

（第１の実施の形態）図１乃至図８は本発明の第１の実
施の形態を示す。(First Embodiment) FIGS. 1 to 8 show a first embodiment of the present invention.

【００３９】図１は表面実装パッケージとして一般的な
ＳＳＯＰの平面図、図２は同様に表面実装パッケージと
して一般的なＱＦＰの平面図である。FIG. 1 is a plan view of a general SSOP as a surface mount package, and FIG. 2 is a plan view of a QFP similarly as a surface mount package.

【００４０】ＳＳＯＰはボディ１の両端側から複数のリ
ード２が突出している。そして、このＳＳＯＰはリード
２が図１に示すように配列しているので、その配線の引
き出しは矢印のように２方向である。一方、ＱＦＰはボ
ディ３の四辺から複数のリード２が突出しており、その
配線の引き出し線は図２の矢印のように４方向である。
したがって、ＳＳＯＰやＱＦＰは単に信号を引き出すだ
けなら素直に外に拡がるだけであり、各信号を交差させ
る必然性はない。現実には外部につく他のＩＣや回路等
の制約により信号の交差は発生するが、これらのパッケ
ージの本質としてはスムーズな配線引き出しが可能であ
る。一方、ＢＧＡは、図３に示すように、ボディ４にハ
ンダボール５が格子状に配置されている。In the SSOP, a plurality of leads 2 project from both ends of the body 1. In this SSOP, since the leads 2 are arranged as shown in FIG. 1, the wiring is drawn in two directions as indicated by arrows. On the other hand, in the QFP, a plurality of leads 2 protrude from four sides of the body 3, and lead lines of the wires are in four directions as shown by arrows in FIG. 2.
Therefore, SSOPs and QFPs simply spread out if they only extract signals, and there is no necessity to cross each signal. In reality, signal crossing occurs due to restrictions on other ICs and circuits attached to the outside, but the nature of these packages allows smooth wiring extraction. On the other hand, in the BGA, as shown in FIG. 3, solder balls 5 are arranged on a body 4 in a lattice pattern.

【００４１】図４に実装状態の断面図が示されていて、
ＢＧＡ基板６上にボンディングワイヤー９で接続させた
ＩＣチップ８がモールド樹脂７で封止されている。そし
て、ＢＧＡ基板６の裏面にはハンダボール１０が格子状
あるいは中空方陣状に配設される。ＢＧＡ基板６として
はＦＲ−４やＢＴレジン等のハードなものもあるが、フ
レキシブルプリント基板等を使用することもある。ま
た、ＩＣチップ８はボンディングワイヤー９で接続され
るものの他、フリップチップといわれるバンプによる裏
向きの接続もある。FIG. 4 is a sectional view showing a mounted state.
An IC chip 8 connected to a BGA substrate 6 by a bonding wire 9 is sealed with a mold resin 7. The solder balls 10 are arranged on the back surface of the BGA substrate 6 in a lattice shape or a hollow square shape. As the BGA substrate 6, there is a hard substrate such as FR-4 or BT resin, but a flexible printed substrate may be used. In addition to the IC chip 8 connected by the bonding wire 9, there is a flip-chip connection called a flip chip.

【００４２】さらには、ＣＳＰ（チップサイズパッケー
ジ）と呼ばれる狭ピッチのパッケージもある。一般に、
ボールピッチが０．８ｍｍ以下のＢＧＡはＣＳＰと呼ば
れることが多い。Further, there is a narrow pitch package called a CSP (chip size package). In general,
A BGA having a ball pitch of 0.8 mm or less is often called a CSP.

【００４３】これらのパッケージの特徴は、ピンが４辺
に設けられているＱＦＰ等の表面実装パッケージとは異
なり、パッケージの裏面に二次元全体にピンを設けてい
るために極めて高密度にピンが付設できるという特徴が
ある。その意味では、ピンの接続に半田ボールを使用し
ないＬＧＡ（ランドグリッドアレイ）といったデバイス
が最近開発されつつあるが、このタイプパッケージの裏
面全体を有効に使ったピン付設という意味で本発明の主
旨に合っており、本発明に応用することができる。The feature of these packages is that, unlike a surface mount package such as a QFP in which pins are provided on four sides, pins are provided on the back of the package two-dimensionally, so that the pins are extremely dense. There is a feature that it can be attached. In that sense, devices such as LGA (land grid array) devices that do not use solder balls for connecting pins are being developed recently. Therefore, it can be applied to the present invention.

【００４４】１１はマザーボードで夫々のハンダボール
１０が該マザーボード１１に実装された後、Ｓ１，Ｓ
２，Ｓ３，Ｓ４といった各信号線の引き出しが行なわれ
ている。Ｓ１やＳ４は多層基板のＢＧＡ実装面側の引き
出しで、Ｓ２やＳ３はスルーホール１２を通して裏面引
き出しを行なっている。このとき、Ｓ３とＳ４の間には
容量結合１３がある。また、図５（Ａ）に示すように、
Ｓ５とＳ６の間にはスルーホール１４があるために抵抗
分１５が発生する。そのため、図５（Ｂ）に示すよう
に、スルーホール１４、容量結合１３により信号Ｓ７と
Ｓ８において信号のクロストーク１６が発生し易くな
る。Numeral 11 denotes a mother board, after each solder ball 10 is mounted on the mother board 11, S1 and S2.
Each signal line such as 2, S3, S4 is drawn. S1 and S4 are drawn on the BGA mounting surface side of the multilayer substrate, and S2 and S3 are drawn on the back surface through the through holes 12. At this time, there is a capacitive coupling 13 between S3 and S4. Also, as shown in FIG.
Since there is a through hole 14 between S5 and S6, a resistance 15 is generated. Therefore, as shown in FIG. 5B, signal crosstalk 16 easily occurs in signals S7 and S8 due to through hole 14 and capacitive coupling 13.

【００４５】ＳＳＯＰやＱＦＰでの配線引き出しでは隣
接ピンの引き出しによる容量結合は銅箔の厚み分が対抗
した分だけであるが、ＢＧＡの配線引き出しは引き出し
線幅の対抗した広い面積での容量結合があるため、クロ
ストークも大きくなり易い。図６は１３×１３の合計１
６９ピンのＢＧＡの配線引き出しを両面基板のマザーボ
ードで実施したもので、両層を通じて示してあり、１７
はハンダパッド、１８はスルーホール、１９は引き出し
線である。In SSOP or QFP wiring extraction, the capacitive coupling due to the extraction of adjacent pins is only the thickness of the copper foil which is opposed to that of the copper foil. Therefore, crosstalk tends to increase. FIG. 6 shows 13 × 13 total 1
A wiring extraction of a 69-pin BGA was performed on a motherboard of a double-sided board, which is shown through both layers.
Is a solder pad, 18 is a through hole, and 19 is a lead wire.

【００４６】図７（Ａ）は実装面の引き出し状態を示
し、図７（Ｂ）はスルーホールを通して裏面へ引き出し
たものである。図７（Ａ）で本体はハンダパッド１７と
スルーホール１８が存在するが、スルーホール１８の方
は見難さをなくすために意図的に省略してある。FIG. 7A shows a state in which the mounting surface is drawn out, and FIG. 7B shows a state in which the mounting surface is drawn out to the back surface through a through hole. In FIG. 7A, the main body has a solder pad 17 and a through-hole 18, but the through-hole 18 is intentionally omitted to make it difficult to see.

【００４７】図７（Ｂ）に示すスルーホール１８は夫々
のすぐ隣接したハンダパッド１７からの信号を裏面に移
し、引き出してある。In the through holes 18 shown in FIG. 7B, signals from the immediately adjacent solder pads 17 are transferred to the back surface and are drawn out.

【００４８】図６〜図７（Ｂ）に示すように、ただ単に
引き出すだけでも通しで見るとかなりの部品面、裏面の
相互間の信号の重なりが見受けられる。すなわち、クロ
ストークがかなり発生しそうであることが考えられる。As shown in FIGS. 6 and 7 (B), a considerable overlap of signals between the component surface and the back surface can be seen when viewed through even if the cable is simply pulled out. That is, it is considered that crosstalk is likely to occur.

【００４９】現在、ＢＧＡに搭載されるＩＣチップはメ
モリーやマイクロプロセッサーやデジタル信号処理ＩＣ
やゲートアレイ等のデジタルＩＣが殆どである。今後、
他ピン化や実装コストの安さを武器にしてデジタル・ア
ナログ混在ＩＣ等も搭載されていくと考えられるが、前
述したようなクロストークにはよほど気を付ける必要が
ある。At present, the IC chip mounted on the BGA includes a memory, a microprocessor, and a digital signal processing IC.
Most are digital ICs such as gates and gate arrays. from now on,
It is thought that digital / analog mixed ICs and the like will be mounted using other pins and low mounting cost as a weapon, but it is necessary to pay close attention to the crosstalk as described above.

【００５０】図８はデジタル・アナログ混在ＩＣの一例
としてシングルチップマイコン２０を示した。２１はコ
アＣＰＵ、２２はＡＤ変換器、２３はＤＡ変換器、２４
は発振回路ＯＳＣ、２５は汎用ポートＰＢ、２６は汎用
ポートＰＡ、２７は通信ポートＣＯＭ、２８はクロック
端子ＣＬＫ、２９はＰＷＭ、３０はドライバーＤＲでモ
ータ３１や発光表示器３２のように比較的大電流を出し
入れしている。また、３３は電源ＰＳである。FIG. 8 shows a single-chip microcomputer 20 as an example of a digital / analog mixed IC. 21 is a core CPU, 22 is an AD converter, 23 is a DA converter, 24
Is an oscillating circuit OSC, 25 is a general-purpose port PB, 26 is a general-purpose port PA, 27 is a communication port COM, 28 is a clock terminal CLK, 29 is a PWM, and 30 is a driver DR, such as a motor 31 or a light emitting display 32. A large current is taken in and out. Reference numeral 33 denotes a power supply PS.

【００５１】前記ＡＤ変換器２２、ＤＡ変換器２３、発
振回路ＯＳＣ２４等はアナログブロックであり、高精度
が要求されたり、インピーダンスが高く、外部からのノ
イズに極めて弱い。The A / D converter 22, the D / A converter 23, the oscillation circuit OSC24, etc. are analog blocks, which require high accuracy, have high impedance, and are extremely weak against external noise.

【００５２】一方、通信ポートＣＯＭ２７や高速クロッ
クのクロック端子ＣＬＫ２８やＰＷＭ２９はデジタル信
号の中でも比較的周波数が高く、そのためノイズを放出
し易い信号群である。On the other hand, the communication port COM27, the clock terminal CLK28 of the high-speed clock, and the PWM 29 have a relatively high frequency among the digital signals, and are a group of signals that easily emit noise.

【００５３】また、ドライバーＤＲ３０や電源ＰＳ３３
等は比較的大電流をやりとりする端子のため、その電流
パスに配線抵抗が含まれると電位差が発生しノイズを放
出し易い端子といえる。また、比較的大電流をやりとり
する信号群として上記したもの以外にグランド、アクチ
ュエータ駆動部、発光素子駆動部等がある。The driver DR30 and the power supply PS33
And the like are terminals that exchange a relatively large current, and if wiring resistance is included in the current path, a potential difference occurs and noise can be easily emitted. Further, in addition to the above-described signals, a ground, an actuator driving unit, a light emitting element driving unit, and the like are used as a signal group for exchanging a relatively large current.

【００５４】したがって、ＡＤ変換器２２、ＤＡ変換器
２３、発振回路ＯＳＣ２４等のアナログブロック群は他
の部分と隔離して容量結合によるクロストークを減らす
必要があり、これらをＢＧＡのコーナー部３５や外周部
３６、３７に配設することでノイズによる不具合を防ぐ
ことができる。また、アナログブロック群とは逆に通信
ポートＣＯＭ２７やクロック端子ＣＬＫ２８やＰＷＭ２
９等のデジタル信号群をＢＧＡの別のコーナー部や外周
部に配設して隔離することでノイズによる不具合を防ぐ
ことができる。さらに、ドライバーＤＲ３０や電源ＰＳ
３３等は、スルーホール等の高抵抗部があると電位差が
発生してノイズ源になるため、スルーホールを通過しな
いパッドに配したり、他の信号から隔離するためにＢＧ
Ａの別のコーナー部や外周部に配設することでノイズに
よる不具合を回避できる。Therefore, the analog blocks such as the AD converter 22, the DA converter 23, and the oscillation circuit OSC24 need to be separated from other parts to reduce crosstalk due to capacitive coupling. By disposing them on the outer peripheral portions 36 and 37, it is possible to prevent problems due to noise. Also, contrary to the analog block group, the communication port COM27, the clock terminal CLK28, and the PWM2
By disposing and isolating the digital signal group such as 9 at another corner or outer periphery of the BGA, it is possible to prevent a problem due to noise. Furthermore, driver DR30 and power supply PS
33 and the like have a high resistance portion such as a through-hole, which generates a potential difference and becomes a noise source.
By arranging it at another corner portion or outer peripheral portion of A, it is possible to avoid problems due to noise.

【００５５】尚、ＢＧＡパッケージの実装面から直接配
線引き出しの可能なパッドに上記各ブロック信号群を割
り付けることで対応することもできる。It is also possible to deal with this by assigning each of the above block signal groups to pads from which wiring can be directly drawn out from the mounting surface of the BGA package.

【００５６】そしてまた、ＢＧＡ内のＩＣのパッドレイ
アウトによっても実現できるばかりでなく、一般に多層
基板によって構成されるＢＧＡ基板内においても引き回
し方法を任意に工夫することで実現できるのである。Further, the present invention can be realized not only by the pad layout of the IC in the BGA but also in the BGA substrate generally formed by a multilayer substrate by arbitrarily devising a routing method.

【００５７】[0057]

【発明の効果】請求項１に係る発明によれば、多ピン化
に適合し、実装コストも比較的安価なＢＧＡをデジタル
・アナログ混在のＩＣに採用しても、そのピン配置に工
夫をこらすことによってＢＧＡが本来もっている容量結
合の多さによるデメリットを排除し、クロストークによ
るノイズの発生を防止することができる。According to the first aspect of the present invention, even if a BGA that is suitable for increasing the number of pins and has a relatively low mounting cost is used for a digital / analog mixed IC, the pin arrangement thereof is devised. This eliminates the disadvantage of the BGA inherently having a large amount of capacitive coupling, thereby preventing the occurrence of noise due to crosstalk.

【００５８】また、ＢＧＡ基板内での配線の置換が比較
的容易にできるため、この手法は一層現実的となる。Further, since the replacement of the wiring in the BGA substrate can be relatively easily performed, this method becomes more practical.

【００５９】請求項２に係る発明によれば、ＢＧＡ内の
ＩＣのパッドレイアウトによって割付配設パターン化を
容易に実現することができ、ノイズに弱い信号群が不具
合となるのを未然に回避できる。According to the second aspect of the present invention, allocation and patterning can be easily realized by the pad layout of the IC in the BGA, and it is possible to prevent a signal group susceptible to noise from becoming defective. .

【００６０】請求項３に係る発明によれば、ＡＤ変換
器、ＤＡ変換器、発振回路等の信号群が不具合となるの
を未然に回避できる。According to the third aspect of the invention, it is possible to prevent a signal group of an AD converter, a DA converter, an oscillation circuit, and the like from becoming defective.

【００６１】請求項４に係る発明によれば、他の信号群
に対しノイズを放出し易い信号群による悪影響を未然に
回避することができる。According to the fourth aspect of the present invention, it is possible to avoid the adverse effect of a signal group that easily emits noise to another signal group.

【００６２】請求項５に係る発明によれば、高速クロッ
ク、ＰＷＭ等の信号群による他の信号群の不具合を未然
に回避できる。According to the fifth aspect of the present invention, it is possible to avoid a problem of another signal group caused by a signal group such as a high-speed clock and a PWM signal.

【００６３】請求項６に係る発明によれば、従来のスル
ーホールを通過させた場合のように高抵抗部の電位差の
出現に伴うノイズの発生等を未然に回避できる。According to the sixth aspect of the present invention, it is possible to avoid the occurrence of noise due to the appearance of the potential difference in the high resistance portion as in the case of passing through a conventional through hole.

【００６４】請求項７に係る発明によれば、電源、グラ
ンド、アクチュエータ駆動部、発光素子駆動部等の信号
群によるノイズの発生等を未然に回避できる。According to the seventh aspect of the invention, it is possible to prevent the occurrence of noise or the like due to a signal group of the power supply, the ground, the actuator driving unit, the light emitting element driving unit, and the like.

【００６５】請求項８に係る発明によれば、両面基板の
マザーボードでの大電流をやりとりする信号群のパッド
割り付けパターンを種々に工夫することで高抵抗部の電
位差の出現に伴うノイズの発生等を未然に回避すること
ができる。According to the eighth aspect of the present invention, by variously devising the pad allocation pattern of a signal group for exchanging a large current in the motherboard of the double-sided board, generation of noise due to the appearance of the potential difference of the high resistance portion, etc. Can be avoided beforehand.

【００６６】請求項９に係る発明によれば、多層マザー
ボードに実装した電源、グランド、アクチュエータ駆動
部、発光素子駆動部等の信号群によるノイズの発生等を
未然に回避できる。According to the ninth aspect of the present invention, it is possible to avoid the occurrence of noise due to a signal group of a power supply, a ground, an actuator driving unit, a light emitting element driving unit, and the like mounted on the multilayer motherboard.

【００６７】請求項１０に係る発明によれば、粗いピッ
チでも多ピンが確保できるハンダボールによるセルフア
ライメント効果で比較的ローコストの実装が可能となる
と同時に、ＢＧＡが本来もっている容量結合の多さによ
るデメリットを排除し、クロストークによるノイズの発
生を防止することができる。According to the tenth aspect of the present invention, the self-alignment effect of the solder ball that can secure a large number of pins even at a coarse pitch enables relatively low-cost mounting, and at the same time, due to the inherent capacity coupling of the BGA. Disadvantages can be eliminated, and generation of noise due to crosstalk can be prevented.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本出願に係る発明の第１の実施の形態における
ＳＳＯＰの配線引き出し状態の平面図FIG. 1 is a plan view of an SSOP in which a wiring is drawn out according to a first embodiment of the present invention;

【図２】本出願に係る発明の第１の実施の形態における
ＱＦＰの配線引き出し状態の平面図FIG. 2 is a plan view of a QFP in a state where a wiring is drawn out according to the first embodiment of the present invention;

【図３】本出願に係る発明の第１の実施の形態における
ＢＧＡの底面図FIG. 3 is a bottom view of the BGA according to the first embodiment of the present invention;

【図４】本出願に係る発明の第１の実施の形態における
ＢＧＡ実装の断面図FIG. 4 is a sectional view of BGA mounting according to the first embodiment of the present invention;

【図５】本出願に係る発明の第１の実施の形態における
説明図であり（Ａ）はスルーホール部を示し、（Ｂ）は
等価回路を示す。FIGS. 5A and 5B are explanatory diagrams of the first embodiment of the present invention, wherein FIG. 5A shows a through-hole portion, and FIG. 5B shows an equivalent circuit.

【図６】本出願に係る発明の第１の実施の形態における
マザーボードの引き出し状態を示す概略図FIG. 6 is a schematic diagram showing a pulled-out state of a motherboard according to the first embodiment of the present invention;

【図７】本出願に係る発明の第１の実施の形態における
説明図であり（Ａ）は実装面の引き出し状態、（Ｂ）は
スルーホールを通しての裏面引き出し状態を示す。FIGS. 7A and 7B are explanatory diagrams of the first embodiment of the present invention, wherein FIG. 7A shows a state in which the mounting surface is drawn out, and FIG.

【図８】本出願に係る発明の第１の実施の形態における
シングルチップマイコンの平面図である。FIG. 8 is a plan view of the single-chip microcomputer according to the first embodiment of the present invention.

【符号の説明】[Explanation of symbols]

１７…ハンダパッド １８…スルーホ
ール １９…引き出し線 ３５…コーナー
部 ３６，３７…周辺部（外周部）17 solder pad 18 through hole 19 lead line 35 corner 36, 37 peripheral part (outer peripheral part)

Claims (10)

【特許請求の範囲】[Claims] 【請求項１】 ＩＣ素子を内包し、前記ＩＣ素子に対す
る信号の入出力を複数のパッドを介して行うＩＣパッケ
ージにおいて、 信号群をノイズに弱い信号群、ノイズを放出し易い信号
群、大電流をやりとりする信号群等の複数の群に分割
し、且つ群相互を隔離するように割付配設パターン化す
ることを特徴としたＩＣパッケージ。1. An IC package including an IC element and inputting / outputting a signal to / from the IC element through a plurality of pads, wherein the signal group is a signal group susceptible to noise, a signal group that easily emits noise, and a large current. An IC package, wherein the IC package is divided into a plurality of groups such as a group of signals to be exchanged, and is assigned and arranged so as to isolate the groups from each other. 【請求項２】 前記ノイズに弱い信号群をパッケージの
外周部またはコーナー部のパッドに割り付けることを特
徴とした請求項１記載のＩＣパッケージ。2. The IC package according to claim 1, wherein the signal group susceptible to the noise is assigned to a pad at an outer peripheral portion or a corner portion of the package. 【請求項３】 前記ノイズに弱い信号群は、ＡＤ変換
器、ＤＡ変換器、発振回路等の信号群であることを特徴
とした請求項２記載のＩＣパッケージ。3. The IC package according to claim 2, wherein the signal group vulnerable to noise is a signal group of an AD converter, a DA converter, an oscillation circuit, and the like. 【請求項４】 前記ノイズを放出し易い信号群をパッケ
ージの外周部またはコーナー部のパッドに割り付けるこ
とを特徴とした請求項１記載のＩＣパッケージ。4. The IC package according to claim 1, wherein the signal group that easily emits the noise is assigned to a pad at an outer peripheral portion or a corner portion of the package. 【請求項５】 前記ノイズを放出し易い信号群は、高速
クロック、ＰＷＭ等の信号群であることを特徴とした請
求項４記載のＩＣパッケージ。5. The IC package according to claim 4, wherein the signal group that easily emits noise is a signal group such as a high-speed clock and a PWM. 【請求項６】 大電流をやりとりする信号群をパッケー
ジの外周部またはコーナー部のパッドに割り付けること
を特徴とした請求項１記載のＩＣパッケージ。6. The IC package according to claim 1, wherein a group of signals for exchanging a large current is assigned to pads on an outer peripheral portion or a corner portion of the package. 【請求項７】 前記大電流をやりとりする信号群は、電
源、グランド、アクチュエータ駆動部、発光素子駆動部
等の信号群であることを特徴とした請求項６記載のＩＣ
パッケージ。7. The IC according to claim 6, wherein the signal group for exchanging the large current is a signal group of a power supply, a ground, an actuator driving unit, a light emitting element driving unit, and the like.
package. 【請求項８】 前記大電流をやりとりする信号群を割り
付ける際に、多層マザーボードに実装した時にマザーボ
ードの第１層である部品実装面から引き出せるパッドに
割り付けることを特徴とした請求項１、６、または７記
載のＩＣパッケージ。8. The method according to claim 1, wherein when allocating the signal group for exchanging the large current, the signal group is allocated to a pad which can be drawn out from a component mounting surface which is a first layer of the motherboard when mounted on a multilayer motherboard. Or the IC package according to 7. 【請求項９】 前記大電流をやりとりする信号群として
は、電源、グランド、アクチュエータ駆動部、発光素子
駆動部等の信号群が含まれることを特徴とした請求項８
記載のＩＣパッケージ。9. The signal group for exchanging a large current includes a signal group of a power supply, a ground, an actuator driving unit, a light emitting element driving unit, and the like.
The described IC package. 【請求項１０】 請求項１乃至９のいずれかにおいて、
全格子、中空方陣タイプを含み、ＣＰＳ等の小型タイプ
を含むことを特徴としたＩＣパッケージ。10. The method according to claim 1, wherein
An IC package including a small lattice type such as a CPS, including a whole lattice and a hollow square type.
JP25545997A 1997-09-19 1997-09-19 IC package, printed circuit board, printed circuit board on which IC package is mounted Expired - Fee Related JP3507300B2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP25545997A JP3507300B2 (en) 1997-09-19 1997-09-19 IC package, printed circuit board, printed circuit board on which IC package is mounted
US09/153,456 US6512680B2 (en) 1997-09-19 1998-09-15 Semiconductor package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP25545997A JP3507300B2 (en) 1997-09-19 1997-09-19 IC package, printed circuit board, printed circuit board on which IC package is mounted

Publications (2)

Publication Number Publication Date
JPH1197613A true JPH1197613A (en) 1999-04-09
JP3507300B2 JP3507300B2 (en) 2004-03-15

Family

ID=17279068

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Country Status (1)

Country Link
JP (1) JP3507300B2 (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001042893A1 (en) * 1999-12-10 2001-06-14 Hitachi, Ltd Semiconductor module
JP2005123591A (en) * 2003-09-25 2005-05-12 Rohm Co Ltd Semiconductor device and electronic apparatus packaging the same
WO2006018939A1 (en) * 2004-08-20 2006-02-23 Rohm Co., Ltd Semiconductor device, power supply apparatus using the same, and electronic device
US7109578B2 (en) 2003-12-25 2006-09-19 Matsushita Electric Industrial Co., Ltd. Semiconductor device and electronic equipment using the same
US7164592B2 (en) 2004-05-24 2007-01-16 Renesas Technology Corp. Semiconductor device
US9484857B2 (en) 2013-11-07 2016-11-01 Seiko Epson Corporation Semiconductor circuit device, electronic device, electronic apparatus, and moving object

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001042893A1 (en) * 1999-12-10 2001-06-14 Hitachi, Ltd Semiconductor module
JP2005123591A (en) * 2003-09-25 2005-05-12 Rohm Co Ltd Semiconductor device and electronic apparatus packaging the same
US7109578B2 (en) 2003-12-25 2006-09-19 Matsushita Electric Industrial Co., Ltd. Semiconductor device and electronic equipment using the same
US7164592B2 (en) 2004-05-24 2007-01-16 Renesas Technology Corp. Semiconductor device
KR101184126B1 (en) 2004-05-24 2012-09-18 르네사스 일렉트로닉스 가부시키가이샤 A semiconductor device
WO2006018939A1 (en) * 2004-08-20 2006-02-23 Rohm Co., Ltd Semiconductor device, power supply apparatus using the same, and electronic device
US9484857B2 (en) 2013-11-07 2016-11-01 Seiko Epson Corporation Semiconductor circuit device, electronic device, electronic apparatus, and moving object

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