JPH1197473A - Semiconductor device and manufacture thereof - Google Patents

Semiconductor device and manufacture thereof

Info

Publication number
JPH1197473A
JPH1197473A JP9254008A JP25400897A JPH1197473A JP H1197473 A JPH1197473 A JP H1197473A JP 9254008 A JP9254008 A JP 9254008A JP 25400897 A JP25400897 A JP 25400897A JP H1197473 A JPH1197473 A JP H1197473A
Authority
JP
Japan
Prior art keywords
wire bonding
bonding pad
terminal
semiconductor chip
selector
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9254008A
Other languages
Japanese (ja)
Inventor
Takeshi Miki
毅 三木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP9254008A priority Critical patent/JPH1197473A/en
Publication of JPH1197473A publication Critical patent/JPH1197473A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05553—Shape in top view being rectangular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49113—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device, in which the same core part without mask modification is used for various specifications in a semiconductor integrated circuit. SOLUTION: Wire bonding pads 13 and 14 are provided in a place adjacent to a power terminal 3 and a ground terminal 4. The output of the bonding pads 13 and 14 joined inside is connected to a switching signal at a selector 9. The output of the selector 9 is connected to an output of a wire bonding pad 2 at an input, terminal. According to a system design, the wire bonding pad 13 or 14 is connected to the power or the lead frame of the grounding as indicated in diagram (a) or (b). In this connection, a pull-down transistor 7 or a pull-up transistor 8 is selected by the selector 9 to make a change in specifications at an input terminal.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は半導体装置の製造方
法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device.

【０００２】[0002]

【従来の技術】図３の（ａ）（ｂ）は従来の半導体装置
を示す。図３の（ａ）は半導体チップのバッファ６の入
力端子をプルアップ状態にした半導体装置を示し、図３
の（ｂ）は半導体チップのバッファ６の入力端子をプル
ダウン状態にした半導体装置を示している。2. Description of the Related Art FIGS. 3A and 3B show a conventional semiconductor device. FIG. 3A shows a semiconductor device in which an input terminal of a buffer 6 of a semiconductor chip is in a pull-up state.
(B) shows a semiconductor device in which the input terminal of the buffer 6 of the semiconductor chip is in a pull-down state.

【０００３】図３において、１は外部と接続するリード
フレーム、２は集積回路の入力端子のワイヤーボンディ
ングパッド、３，４は電源およびグランド端子のワイヤ
ーボンディングパッドである。５はリードフレーム１と
半導体チップを接続するワイヤである。In FIG. 3, reference numeral 1 denotes a lead frame connected to the outside, 2 denotes wire bonding pads for input terminals of an integrated circuit, and 3 and 4 denote wire bonding pads for power and ground terminals. 5 is a wire connecting the lead frame 1 and the semiconductor chip.

【０００４】セレクタ９は、バッファ６のモードを選択
するもので、入力にはプルダウントランジスタ７とプル
アップトランジスタ８が接続されている。セレクタ９の
切換信号入力は、最終製品が半導体チップのバッファ６
の入力端子をプルアップ状態にした半導体装置の場合に
は図３の（ａ）に示すようにバッファ１０を介して半導
体チップの内部の電源ライン１１に接続されるように配
線層を形成し、最終製品が半導体チップのバッファ６の
入力端子をプルダウン状態にした半導体装置の場合には
図３の（ｂ）に示すようにバッファ１０を介して半導体
チップの内部のグランドライン１２に接続されるように
配線層が形成されている。The selector 9 selects a mode of the buffer 6, and has an input connected to a pull-down transistor 7 and a pull-up transistor 8. The switching signal input of the selector 9 is provided when the final product is a semiconductor chip buffer 6.
In the case of a semiconductor device in which the input terminals of the above are pulled up, a wiring layer is formed so as to be connected to the power supply line 11 inside the semiconductor chip via the buffer 10 as shown in FIG. When the final product is a semiconductor device in which the input terminal of the buffer 6 of the semiconductor chip is pulled down, the semiconductor device is connected to the ground line 12 inside the semiconductor chip via the buffer 10 as shown in FIG. Is formed with a wiring layer.

【０００５】なお、各ワイヤーボンディングパッドとバ
ッファ６，１０およびプルダウントランジスタ７とプル
アップトランジスタ８は、同一の半導体チップ上に形成
されている。The respective wire bonding pads, buffers 6, 10 and pull-down transistor 7 and pull-up transistor 8 are formed on the same semiconductor chip.

【０００６】プルダウントランジスタ７はソースをグラ
ンドに接続し、ゲートを電源に接続し、ドレインがセレ
クタ９の入力に接続されている。プルアップトランジス
タ８はソースを電源に接続し、ゲートをグランドに接続
し、ドレインがセレクタ９の入力に接続されている。The pull-down transistor 7 has a source connected to the ground, a gate connected to the power supply, and a drain connected to the input of the selector 9. The pull-up transistor 8 has a source connected to the power supply, a gate connected to the ground, and a drain connected to the input of the selector 9.

【０００７】[0007]

【発明が解決しようとする課題】このように、集積回路
のコア、つまり半導体チップが同一で入力端子のプルア
ップやプルダウンをシステムの仕様によって変更する場
合、システムの仕様が決定後に配線レイヤマスクを変更
し拡散、組立行程を経てサンプル出荷するため、サンプ
ル出荷するまでの時間を費やしてしまう問題がある。As described above, when the core of the integrated circuit, that is, the semiconductor chip is the same and the pull-up or pull-down of the input terminal is changed according to the system specifications, the wiring layer mask is changed after the system specifications are determined. Since the sample is shipped after the change, the diffusion, and the assembly process, there is a problem that time is spent until the sample is shipped.

【０００８】本発明は上記従来の課題を解決するもので
あり、マスク修正すること無く組立行程での修正でシス
テムの仕様に対応でき、早期のサンプル出荷を可能にす
ることのできる半導体装置の製造方法と半導体装置を提
供することを目的とする。SUMMARY OF THE INVENTION The present invention solves the above-mentioned conventional problems, and manufactures a semiconductor device capable of meeting the specifications of the system by making corrections in the assembly process without correcting the mask and enabling early sample shipment. It is an object to provide a method and a semiconductor device.

【０００９】[0009]

【課題を解決するための手段】本発明の半導体装置の製
造方法は、ワイヤーボンディング工程を変更して入力端
子のプルアップやプルダウンをシステムの仕様を変更す
ることを特徴とする。A method of manufacturing a semiconductor device according to the present invention is characterized in that a wire bonding process is changed to change the specifications of a system for pulling up or pulling down an input terminal.

【００１０】この構成により、システムの仕様に対して
マスク修正無しに、システムの内容の選択を可能にする
ことができる。[0010] With this configuration, it is possible to select the contents of the system without modifying the mask for the specifications of the system.

【００１１】[0011]

【発明の実施の形態】請求項１記載の半導体装置の製造
方法は、共通の半導体チップを使用して回路モードの異
なる半導体装置を製造するに際し、半導体チップのモー
ドを選択するセレクタの切換信号入力を、半導体チップ
の電源端子に接続された第１のワイヤーボンディングパ
ッドに隣接する第３のワイヤーボンディングパッドと半
導体チップのグランドに接続された第２のワイヤーボン
ディングパッドに隣接する第４のワイヤーボンディング
パッドとに接続された前製品を製造し、リードフレーム
の第１端子と第３のワイヤーボンディングパッド、また
はリードフレームの第２端子と第４のワイヤーボンディ
ングパッドの何れかを、最終製品のモードに応じてワイ
ヤーボンディングすることを特徴とする。According to a first aspect of the present invention, there is provided a method of manufacturing a semiconductor device, wherein a semiconductor device having a different circuit mode is manufactured using a common semiconductor chip, and a switching signal input of a selector for selecting a mode of the semiconductor chip is provided. A third wire bonding pad adjacent to the first wire bonding pad connected to the power supply terminal of the semiconductor chip, and a fourth wire bonding pad adjacent to the second wire bonding pad connected to the ground of the semiconductor chip. And manufacturing either of the first terminal and the third wire bonding pad of the lead frame or the second terminal and the fourth wire bonding pad of the lead frame according to the mode of the final product. Wire bonding.

【００１２】請求項２記載の半導体装置は、リードフレ
ームの第１端子と半導体チップの電源端子に接続された
第１のワイヤーボンディングパッドとをワイヤーボンデ
ィングし、リードフレームの第２端子と半導体チップの
グランド端子に接続された第２のワイヤーボンディング
パッドとをワイヤーボンディングし、前記の半導体チッ
プのモードを選択するセレクタを設け、第１のワイヤー
ボンディングパッドに隣接して第３のワイヤーボンディ
ングパッドを設け、第２のワイヤーボンディングパッド
に隣接して第４のワイヤーボンディングパッドを設け、
前記セレクタの切換信号入力を第３，第４のワイヤーボ
ンディングパッドに接続し、リードフレームの第１端子
と第３のワイヤーボンディングパッド、またはリードフ
レームの第２端子と第４のワイヤーボンディングパッド
の何れかを、最終製品のモードに応じてワイヤーボンデ
ィングして前記セレクタの切換状態を指定したことを特
徴とする。According to a second aspect of the present invention, in the semiconductor device, the first terminal of the lead frame and the first wire bonding pad connected to the power supply terminal of the semiconductor chip are wire-bonded, and the second terminal of the lead frame is connected to the semiconductor chip. A second wire bonding pad connected to the ground terminal is wire-bonded, a selector for selecting a mode of the semiconductor chip is provided, and a third wire bonding pad is provided adjacent to the first wire bonding pad; Providing a fourth wire bonding pad adjacent to the second wire bonding pad;
The switching signal input of the selector is connected to third and fourth wire bonding pads, and any one of the first terminal and third wire bonding pad of the lead frame or the second terminal and fourth wire bonding pad of the lead frame is connected. The switching state of the selector is designated by wire bonding according to the mode of the final product.

【００１３】以下、本発明の半導体装置の製造方法を具
体的な実施の形態を示す図１と図２に基づいて説明す
る。なお、従来例を示す図３と同一の作用を成すものに
は同一の符号を付けて説明する。Hereinafter, a method of manufacturing a semiconductor device according to the present invention will be described with reference to FIGS. 1 and 2 showing specific embodiments. It is to be noted that components having the same functions as those in FIG.

【００１４】図２は本発明の半導体装置の製造方法の最
終製品の前の前製品を示す。１３，１４は電源及びグラ
ンドのワイヤーボンディングパッド３，４に隣接して配
置されたワイヤーボンディングパッドで、何れもが集積
回路内部でバッファ１０の入力に接続されている。FIG. 2 shows a pre-product before a final product in the method of manufacturing a semiconductor device according to the present invention. Reference numerals 13 and 14 denote wire bonding pads disposed adjacent to the power and ground wire bonding pads 3 and 4, both of which are connected to the input of the buffer 10 inside the integrated circuit.

【００１５】この前製品は、第１のリードフレーム１ａ
とワイヤーボンディングパッド３、第２のリードフレー
ム１ｂとワイヤーボンディングパッド４、第３のリード
フレーム１ｃとワイヤーボンディングパッド２などをワ
イヤ５でワイヤーボンディングする工程において、最終
製品のシステムの仕様によって入力端子２をプルアップ
にする場合には、図１の（ａ）に示すようにワイヤーボ
ンディングパッド１３をリードフレーム１ａとワイヤー
１５で接続し、ワイヤーボンディングパッド１４はその
ままのオープン状態にする。この接続によってバッファ
１０の入力が”１”になりセレクタ９の切り替え信号
も”１”になる。The previous product is a first lead frame 1a.
In the step of wire bonding the second lead frame 1b and the wire bonding pad 4, the third lead frame 1c and the wire bonding pad 2, etc. with the wire 5, the input terminal 2 depends on the system specification of the final product. When pulling up, the wire bonding pad 13 is connected to the lead frame 1a by a wire 15 as shown in FIG. 1A, and the wire bonding pad 14 is left open. With this connection, the input of the buffer 10 becomes "1", and the switching signal of the selector 9 also becomes "1".

【００１６】ここでセレクタ９はプルアップトランジス
タ８を選択し、バッファ６の入力はプルアップされる。
また、他のシステムにおいて同一の入力端子をプルダウ
ン入力にする場合には、ワイヤーボンディングする工程
において、図１の（ｂ）に示すようにワイヤーボンディ
ングパッド１４をリードフレーム１ｂにワイヤ１５で接
続し、ワイヤーボンディングパッド１３はオープン状態
にする。Here, the selector 9 selects the pull-up transistor 8, and the input of the buffer 6 is pulled up.
When the same input terminal is used as a pull-down input in another system, a wire bonding pad 14 is connected to the lead frame 1b by a wire 15 as shown in FIG. The wire bonding pad 13 is kept open.

【００１７】これにより、バッファ１０の入力が”０”
になり、セレクタ９の切り替え信号も”０”になるた
め、セレクタ９はプルダウントランジスタ７を選択し、
バッファ６の入力はプルダウンされる。As a result, the input of the buffer 10 becomes "0".
And the switching signal of the selector 9 also becomes “0”, so that the selector 9 selects the pull-down transistor 7 and
The input of the buffer 6 is pulled down.

【００１８】以上のように前製品の各リードフレームと
各ワイヤーボンディングパッドとをワイヤーボンディン
グする工程を最終製品のシステムのモードに応じて変更
するだけで目的のモードに設定された半導体集積装置を
得ることができる。As described above, a semiconductor integrated device set to a desired mode can be obtained only by changing the step of wire bonding each lead frame of the previous product and each wire bonding pad according to the mode of the system of the final product. be able to.

【００１９】[0019]

【発明の効果】以上のように本発明によると、電源端子
とグランド端子にそれぞれに隣接したワイヤーボンディ
ングパッドを配置し、その出力を互いに接続しセレクタ
の切り替え信号に接続し、仕様によって隣接したパッド
にワイヤを接続することで同一のコアで異なった仕様の
集積回路を実現することができ、早期にサンプル出荷を
することができる。As described above, according to the present invention, the wire bonding pads adjacent to the power supply terminal and the ground terminal are arranged, and their outputs are connected to each other and connected to the selector switching signal. By connecting wires to the same core, integrated circuits with different specifications can be realized with the same core, and samples can be shipped early.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明の実施の形態におけるモード別の最終製
品の構成図FIG. 1 is a configuration diagram of a final product in each mode according to an embodiment of the present invention.

【図２】同実施の形態における前製品の構成図FIG. 2 is a configuration diagram of a previous product in the embodiment.

【図３】従来の半導体装置の構成図FIG. 3 is a configuration diagram of a conventional semiconductor device.

【符号の説明】[Explanation of symbols]

１ａ，１ｂ，１ｃ リードフレーム ２，３，４，１３，１４ ワイヤーボンディングパッ
ド ５，１５ ワイヤ ６，１０ バッファ ７ プルダウントランジスタ ８ プルアップトランジスタ ９ セレクタ １１ 電源ライン １２ グランドライン1a, 1b, 1c Lead frame 2, 3, 4, 13, 14 Wire bonding pad 5, 15 Wire 6, 10 Buffer 7 Pull down transistor 8 Pull up transistor 9 Selector 11 Power line 12 Ground line

Claims (2)

【特許請求の範囲】[Claims] 【請求項１】共通の半導体チップを使用して回路モード
の異なる半導体装置を製造するに際し、 半導体チップのモードを選択するセレクタの切換信号入
力を、 半導体チップの電源端子に接続された第１のワイヤーボ
ンディングパッドに隣接する第３のワイヤーボンディン
グパッドと半導体チップのグランドに接続された第２の
ワイヤーボンディングパッドに隣接する第４のワイヤー
ボンディングパッドとに接続された前製品を製造し、 リードフレームの第１端子と第３のワイヤーボンディン
グパッド、またはリードフレームの第２端子と第４のワ
イヤーボンディングパッドの何れかを、最終製品のモー
ドに応じてワイヤーボンディングする半導体装置の製造
方法。When manufacturing a semiconductor device having a different circuit mode using a common semiconductor chip, a switching signal input of a selector for selecting a mode of the semiconductor chip is connected to a first power supply terminal connected to a power supply terminal of the semiconductor chip. Manufacturing a previous product connected to the third wire bonding pad adjacent to the wire bonding pad and the fourth wire bonding pad adjacent to the second wire bonding pad connected to the ground of the semiconductor chip; A method of manufacturing a semiconductor device, wherein one of a first terminal and a third wire bonding pad or a second terminal and a fourth wire bonding pad of a lead frame is wire-bonded according to a mode of a final product. 【請求項２】リードフレームの第１端子と半導体チップ
の電源端子に接続された第１のワイヤーボンディングパ
ッドとをワイヤーボンディングし、 リードフレームの第２端子と半導体チップのグランド端
子に接続された第２のワイヤーボンディングパッドとを
ワイヤーボンディングし、 前記の半導体チップのモードを選択するセレクタを設
け、 第１のワイヤーボンディングパッドに隣接して第３のワ
イヤーボンディングパッドを設け、 第２のワイヤーボンディングパッドに隣接して第４のワ
イヤーボンディングパッドを設け、 前記セレクタの切換信号入力を第３，第４のワイヤーボ
ンディングパッドに接続し、 リードフレームの第１端子と第３のワイヤーボンディン
グパッド、またはリードフレームの第２端子と第４のワ
イヤーボンディングパッドの何れかを、最終製品のモー
ドに応じてワイヤーボンディングして前記セレクタの切
換状態を指定した半導体装置。A first wire bonding pad connected to a power terminal of the semiconductor chip and a first wire bonding pad connected to a power terminal of the semiconductor chip; and a second terminal connected to the second terminal of the lead frame and a ground terminal of the semiconductor chip. A second wire bonding pad; a selector for selecting a mode of the semiconductor chip; a third wire bonding pad adjacent to the first wire bonding pad; a second wire bonding pad; A fourth wire bonding pad is provided adjacently, a switching signal input of the selector is connected to the third and fourth wire bonding pads, and the first terminal of the lead frame and the third wire bonding pad or the lead frame are connected. 2nd terminal and 4th wire bondy One of Gupaddo, semiconductor device to the specified switching state of the selector by wire bonding according to the mode of the final product.
JP9254008A 1997-09-19 1997-09-19 Semiconductor device and manufacture thereof Pending JPH1197473A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9254008A JPH1197473A (en) 1997-09-19 1997-09-19 Semiconductor device and manufacture thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9254008A JPH1197473A (en) 1997-09-19 1997-09-19 Semiconductor device and manufacture thereof

Publications (1)

Publication Number Publication Date
JPH1197473A true JPH1197473A (en) 1999-04-09

Family

ID=17258987

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9254008A Pending JPH1197473A (en) 1997-09-19 1997-09-19 Semiconductor device and manufacture thereof

Country Status (1)

Country Link
JP (1) JPH1197473A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6603219B2 (en) 2000-03-08 2003-08-05 Matsushita Electric Industrial Co., Ltd. Semiconductor integrated circuit
JP2009246087A (en) * 2008-03-31 2009-10-22 Nec Electronics Corp Semiconductor device and operation mode setting method thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6603219B2 (en) 2000-03-08 2003-08-05 Matsushita Electric Industrial Co., Ltd. Semiconductor integrated circuit
JP2009246087A (en) * 2008-03-31 2009-10-22 Nec Electronics Corp Semiconductor device and operation mode setting method thereof

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