JP2000294933A - Multilayer circuit substrate and manufacture thereof - Google Patents
Multilayer circuit substrate and manufacture thereofInfo
- Publication number
- JP2000294933A JP2000294933A JP9714199A JP9714199A JP2000294933A JP 2000294933 A JP2000294933 A JP 2000294933A JP 9714199 A JP9714199 A JP 9714199A JP 9714199 A JP9714199 A JP 9714199A JP 2000294933 A JP2000294933 A JP 2000294933A
- Authority
- JP
- Japan
- Prior art keywords
- film
- copper
- tin
- plating
- via hole
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、多層回路基板及び
その製造方法に係わり、特にフィルム回路を複数枚重ね
て層間の接着とビアの電気的な接続とを同時に行うのに
好適な多層回路基板及びその製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer circuit board and a method of manufacturing the same, and more particularly, to a multilayer circuit board suitable for simultaneously bonding a plurality of film circuits and electrically connecting vias by stacking a plurality of film circuits. And its manufacturing method.
【０００２】[0002]
【従来の技術】従来の回路基板はプリント配線板と呼ば
れ、ガラス繊維にエポキシ樹脂を含浸した、いわゆるプ
リプレグ材と呼ばれる板上の銅箔をエッチングして所定
の回路パターンを形成した後、これを複数枚重ねて積層
接着し、しかる後にドリルで貫通穴を開けて、この穴の
壁面に銅めっきでビアを形成して層間の電気接続を行っ
た配線基板が主流であった（例えば特開平６−２８３８
６６号公報）。2. Description of the Related Art A conventional circuit board is called a printed wiring board. A predetermined circuit pattern is formed by etching a copper foil on a so-called prepreg material in which glass fiber is impregnated with an epoxy resin. In general, a wiring board in which a plurality of sheets are laminated and bonded, a through hole is formed by a drill, and a via is formed on the wall surface of the hole by copper plating to perform electrical connection between layers (for example, Japanese Patent Laid-Open No. 6-2838
No. 66).
【０００３】しかし、搭載部品の小型化、高密度化が進
み、上記のプリント配線板では配線密度が不足して部品
の搭載に問題が生じるようになっている。この問題を解
決するために、本発明者等は先に特願平１０−２１９５
号で銅箔付きポリイミドフィルムを用いた多層回路基板
の製造方法を提案した。[0003] However, with the progress of miniaturization and higher density of mounted components, the wiring density of the above-mentioned printed wiring board is insufficient, and there is a problem in mounting components. In order to solve this problem, the present inventors have previously filed Japanese Patent Application No. 10-2195.
No.2 proposed a method of manufacturing a multilayer circuit board using a polyimide film with copper foil.
【０００４】この製造方法の概略を図２に示す工程で説
明すると、まず、図２ａ〜図２ｂに示すように銅箔（２
０２）付ポリイミドフィルム（２０１）をレーザでビア
穴（２０３）加工した後、図ｃに示すように電気めっき
によりビア穴に銅（２０４）を充填する。更に連続して
銅ビアの表面に金の電気めっき（２０５）を行い接合金
属を形成する。[0004] The outline of this manufacturing method will be described with reference to the steps shown in FIG. 2. First, as shown in FIGS.
02) After processing the polyimide film (201) with a via hole (203) using a laser, the via hole is filled with copper (204) by electroplating as shown in FIG. Further, gold plating (205) is continuously performed on the surface of the copper via to form a bonding metal.
【０００５】この後、図ｄに示すようにビア面側を保護
フィルム（２０６）で被い、反対面にレジスト（２０
７）を塗布して図ｅに示すようにフォトリソ、エッチン
グにより銅箔をパターニングして配線層（２０８）を形
成する。次に、配線パターンの表面に無電解めっきで錫
めっき膜（２０９）を形成してもう一方の接合金属とす
る。Thereafter, as shown in FIG. 1D, the via surface side is covered with a protective film (206), and the resist (20) is formed on the opposite surface.
7) is applied, and the copper foil is patterned by photolithography and etching to form a wiring layer (208) as shown in FIG. Next, a tin-plated film (209) is formed on the surface of the wiring pattern by electroless plating to form another bonding metal.
【０００６】図２ｆに示すように以上の工程で得られた
配線フィルムの表面に接着樹脂（２１０）を塗布した
後、図２ｇに示すように複数枚のフィルムを重ねて熱プ
レスし、多層配線基板を得る。[0006] As shown in FIG. 2f, after applying an adhesive resin (210) to the surface of the wiring film obtained by the above steps, as shown in FIG. Obtain a substrate.
【０００７】上記提案の配線基板の製造方法は、複数枚
の配線フィルムを積層接着すると同時に、ビアが接着樹
脂を排除しながら他の層の配線と金属接合を行い隣接層
間の電気的接続を同時に行うことが特徴である。このた
めには接着材の特性は接着温度で一旦粘度が大幅に低下
して十分流動することが重要であり、接合金属としては
接着温度よりも低い温度で接合でき、且つ接着後には接
合部の融点が接着温度よりも高くなっている必要があ
る。In the above-mentioned method of manufacturing a wiring board, a plurality of wiring films are laminated and bonded, and at the same time, the vias are bonded to the wirings of the other layers by metal while excluding the adhesive resin, so that the electrical connection between the adjacent layers is simultaneously performed. It is a feature to do. For this purpose, it is important for the adhesive to be able to join at a temperature lower than the joining temperature as the joining metal, and it is important that the viscosity of the adhesive once decreases greatly at the joining temperature and that the adhesive flows sufficiently. The melting point must be higher than the bonding temperature.
【０００８】このような条件を満たすために上記の例で
は接着材として、室温で固体、接着温度で溶解して大幅
に粘度が低下するエポキシ樹脂を用いている。この樹脂
は室温で固体のために、溶媒で希釈して液体状にし、こ
の液体をロールコータで塗布した後、乾燥する製造方式
を用いている。In order to satisfy such conditions, in the above-mentioned example, an epoxy resin which is solid at room temperature and which melts at the bonding temperature to greatly reduce the viscosity is used as the adhesive. Since this resin is a solid at room temperature, a manufacturing method is used in which the resin is diluted with a solvent to form a liquid, the liquid is applied by a roll coater, and then dried.
【０００９】また、接合金属としては錫のような低融点
金属を一方の電極とし、他方の電極としては金のような
貴金属を用い、接着温度ではまず錫が溶けて金を溶解
し、金の濃度が上昇するに従って合金の融点が上昇する
ため、配線フィルムの接着完了時点で接合部の融点は接
着温度よりも高くなり、安定した接続が得られる。Also, a low melting point metal such as tin is used as one electrode as a bonding metal, and a noble metal such as gold is used as the other electrode. At the bonding temperature, tin first melts to dissolve gold, and Since the melting point of the alloy increases as the concentration increases, the melting point of the bonding portion becomes higher than the bonding temperature at the time of completion of the bonding of the wiring film, and a stable connection can be obtained.
【００１０】[0010]
【発明が解決しようとする課題】しかし、上記提案の技
術では層間の接着に液状のエポキシ樹脂を用いており、
塗布時に厚さを均一に制御することが難しく、塗布むら
が生じて余分の樹脂が積層接着時に配線基板の周辺には
み出してプレス装置を汚染した。このために接着毎にプ
レス装置を清掃する必要があり、量産技術としては問題
があった。However, in the technique proposed above, a liquid epoxy resin is used for bonding between layers,
It was difficult to control the thickness uniformly during application, and uneven application occurred, and excess resin protruded to the periphery of the wiring board during lamination and adhesion, contaminating the press device. For this reason, it is necessary to clean the press device for each bonding, and there is a problem in mass production technology.
【００１１】また、溶媒で希釈して塗布するために、塗
布後の乾燥を十分に行わないとエポキシ樹脂中に溶媒が
残り、接着中に溶媒が気化して樹脂中に気泡が発生する
場合もあった。樹脂中に気泡が残ると配線基板の耐湿度
試験を行った場合に膨れ等が発生する原因となり、信頼
性上好ましくない。[0011] Further, since the solvent is diluted in a solvent and applied, if the drying after the application is not sufficiently performed, the solvent remains in the epoxy resin, and the solvent may be vaporized during bonding and bubbles may be generated in the resin. there were. If air bubbles remain in the resin, swelling or the like may occur when a humidity resistance test of the wiring board is performed, which is not preferable in terms of reliability.
【００１２】また、ビアの接合金属として錫と金といっ
たような異なる金属を用いるために配線フィルムの製造
工程が複雑となって基板の製造コストが高くなる問題が
あった。In addition, since different metals, such as tin and gold, are used as via-bonding metals, the manufacturing process of the wiring film is complicated, and the manufacturing cost of the substrate is increased.
【００１３】したがって、本発明の目的はかかる前記提
案技術の問題点を解消することにあり、フィルム回路を
複数枚重ねて層間の接着とビアの電気的な接続を同一の
熱処理工程で行うに際して好適な多層回路基板の構成及
びその製造方法を提供することにある。Accordingly, an object of the present invention is to solve the problems of the above-mentioned proposed technique, and it is suitable when a plurality of film circuits are stacked and adhesion between layers and electrical connection of vias are performed in the same heat treatment step. And a method of manufacturing the same.
【００１４】[0014]
【課題を解決するための手段】本発明では、上記の問題
点を解決するために、先ず層間の接着樹脂として予め厚
さを均一に作った接着フィルムを配線フィルムの表面に
貼り付ける製造方法を用いた。接着フィルムとしては、
例えばエポキシ樹脂等の電気絶縁性の高い熱硬化性接着
樹脂を、例えばＰＥＴ（ポリエチレンテレフタレート）
フィルムのごとき搬送フィルム（ベースフィルム）に厚
さ２５±２μｍの精度で予め塗布したものを用いる。配
線フィルムを積層して多層回路基板とする際には、予め
接着フィルムから接着樹脂を各々の配線フィルムに転写
して使用する。According to the present invention, in order to solve the above-mentioned problems, there is firstly provided a method of manufacturing a method of bonding an adhesive film having a uniform thickness in advance as an interlayer adhesive resin to the surface of a wiring film. Using. As an adhesive film,
For example, a thermosetting adhesive resin having high electrical insulation such as an epoxy resin may be used, for example, by using PET (polyethylene terephthalate).
Use is made of a carrier film (base film) such as a film which has been applied in advance with an accuracy of 25 ± 2 μm in thickness. When the wiring films are laminated to form a multilayer circuit board, the adhesive resin is transferred from the adhesive film to each wiring film in advance and used.
【００１５】また、ビアの接合金属としては金／錫のよ
うな異種金属の接合を用いるのではなく、めっき処理で
供給可能な錫／錫の接合を用いることにした。ただし、
単純に錫／錫接合を用いると接合金属の耐熱性は錫の融
点である２３２℃となり、積層接着をこの温度の近傍で
行うとプレス圧力を取り除いた時点で接合部が解離する
ので、錫めっきの下地に銅を用いて、接着時に銅が錫中
に拡散して錫銅合金を作り、接合金属の耐熱性が向上す
るようにした。In addition, instead of using a different metal such as gold / tin as a bonding metal for the via, a tin / tin bonding that can be supplied by plating is used. However,
If a tin / tin joint is simply used, the heat resistance of the joining metal becomes 232 ° C., which is the melting point of tin. If the lamination bonding is performed in the vicinity of this temperature, the joint is dissociated when the pressing pressure is removed. Copper was diffused into tin at the time of bonding to form a tin-copper alloy, so that the heat resistance of the joint metal was improved.
【００１６】錫めっきの実用的な膜厚は０．３〜１．５
μｍ程度であるが、ビアの信頼性の高い接合を得るには
０．５〜１．０μｍとすることが好ましい。また、錫め
っきは、配線フィルムの表面に形成された配線パターン
上と配線フィルムの裏面に形成されたビアの突出部表面
とに同時に形成することが望ましく、無電解めっきが実
用的で好ましい。The practical thickness of tin plating is 0.3 to 1.5.
Although it is about μm, the thickness is preferably 0.5 to 1.0 μm in order to obtain a highly reliable junction of the via. Further, it is desirable that the tin plating is formed simultaneously on the wiring pattern formed on the surface of the wiring film and on the surface of the projecting portion of the via formed on the back surface of the wiring film, and electroless plating is practical and preferable.
【００１７】上記本発明の目的を達成する具体的な達成
手段について述べると以下の通りである。先ず、多層回
路基板の発明は、絶縁フィルムの少なくとも片面に配線
パターンを有し、絶縁フィルムの表裏面を貫通して導電
性のビア穴を有し、そのビア穴と電気的に接続された表
裏面の任意の場所に接続用電極を設けた回路基板同士
を、絶縁層を介して複数枚積層した構造の多層回路基板
であって、前記複数の互いに隣接する回路基板同士を電
気的に接続するビアの接合金属として銅下地の錫めっき
を用い、錫銅合金を形成して電気的に接続したことを特
徴とする。The specific means for achieving the object of the present invention will be described below. First, the invention of a multilayer circuit board has a wiring pattern on at least one surface of an insulating film, a conductive via hole penetrating through the front and back surfaces of the insulating film, and a surface electrically connected to the via hole. A multilayer circuit board having a structure in which a plurality of circuit boards provided with connection electrodes at arbitrary locations on the back surface are laminated via an insulating layer, and the plurality of adjacent circuit boards are electrically connected to each other. The present invention is characterized in that tin plating on a copper base is used as a bonding metal of a via, and a tin-copper alloy is formed to be electrically connected.
【００１８】また、多層回路基板の製造方法の発明は、
表面に銅被膜が形成された絶縁フィルムの裏面からビ
ア穴を形成し、貫通させずにビア穴内から銅被膜を露出
させる工程と、銅めっきにより前記ビア穴内を埋め込
み、絶縁フィルム裏面から突出するまでめっきを続けて
ビア穴に突起電極を形成する工程と、前記絶縁フィル
ム上の銅被膜を選択エッチングすることにより、前記ビ
ア穴と電気的に接続された配線パターンを形成する工程
と、前記配線パターン及びビア穴に設けられた突起電
極に錫めっきする工程と、前記錫めっきされた突起電
極を有する絶縁フィルムの少なくとも一方の面に層間接
着材として予め一定の厚さに成形されたフィルム状の接
着樹脂を形成する工程と、このようにして形成された
回路基板材を複数枚積層し、この積層体を加圧下で加熱
して層間の接着とビアの電気的な接続とを行う工程とを
有することを特徴とする。Further, the invention of a method for manufacturing a multilayer circuit board is as follows.
Forming a via hole from the back surface of the insulating film with the copper film formed on the surface, and exposing the copper film from the inside of the via hole without penetrating, filling the via hole with copper plating, until protruding from the back surface of the insulating film. Forming a protruding electrode in the via hole by continuing plating; and forming a wiring pattern electrically connected to the via hole by selectively etching a copper film on the insulating film; And a step of tin-plating the protruding electrode provided in the via hole, and a film-like adhesion previously formed to a constant thickness as an interlayer adhesive on at least one surface of the insulating film having the tin-plated protruding electrode. A step of forming a resin, laminating a plurality of circuit board materials formed in this manner, and heating the laminated body under pressure to bond between layers and electrically connect vias. Characterized by a step of performing the connection.
【００１９】[0019]
【発明の実施の形態】以下、図面に従って本発明の実施
の形態を説明する。図１は、本発明による配線フィルム
１層分を得るための製造工程と多層回路基板を得るため
の積層工程とをフィルムの断面で示した例である。Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is an example in which a manufacturing process for obtaining one layer of a wiring film according to the present invention and a laminating process for obtaining a multilayer circuit board are shown in cross section of the film.
【００２０】図１ａは、絶縁層としてのポリイミドフィ
ルム１０１上に銅箔１０２が貼り合わせられたフィルム
の断面を示している。ポリイミドフィルム１０１の厚さ
が薄いと加工処理時の取り扱いが難しくなり、厚いとビ
ア穴の加工と金属導体のめっきによる充填が困難とな
る。このため、ポリイミドフィルム１０１の厚さは２０
〜５０μｍ程度の厚さが適している。ここでは厚さ４０
μｍのポリイミドフィルムを用いた。FIG. 1A shows a cross section of a film in which a copper foil 102 is bonded on a polyimide film 101 as an insulating layer. If the thickness of the polyimide film 101 is small, it becomes difficult to handle during the processing, and if the thickness is large, it becomes difficult to process the via hole and fill the metal conductor by plating. Therefore, the thickness of the polyimide film 101 is 20
A thickness of about 50 μm is suitable. Here, thickness 40
A μm polyimide film was used.
【００２１】銅箔１０２の厚さは選択的なエッチングで
微細パターンを形成するためには３０μｍ以下で薄い方
が好ましいが、ここでは１８μｍを用いている。なお、
図１中では便宜的に銅箔側を表面、ポリイミドフィルム
側を裏面と呼ぶことにする。In order to form a fine pattern by selective etching, the thickness of the copper foil 102 is preferably 30 μm or less, but preferably 18 μm. In addition,
In FIG. 1, the copper foil side is referred to as the front side and the polyimide film side is referred to as the back side for convenience.
【００２２】図１ｂは、炭酸ガスレーザビームを直径２
００μｍに絞ってフィルム裏面から照射し、ポリイミド
フィルムを貫通して表面の銅箔１０２がストッパとなる
ブラインドビア１０３を形成した状態を示している。ビ
ア穴の径が大きいと高密度配線に適さないのでなるべく
小さくする必要があるが、小さいと穴のアスペクト比が
増大してめっきによるビアの充填が困難になるので、ア
スペクト比が１以下になるようにビア径とフィルム厚さ
を選択することが望ましい。ここでのアスペクト比は４
０μｍ／２００μｍ＝０．２である。FIG. 1b shows a carbon dioxide laser beam having a diameter of 2
The state is shown in which a blind via 103 is formed by irradiating the film from the back surface of the film with the aperture being reduced to 00 μm, penetrating the polyimide film, and the copper foil 102 on the front surface serving as a stopper. If the diameter of the via hole is large, it is not suitable for high-density wiring, so it is necessary to make the diameter as small as possible. However, if the diameter is small, the filling of the via by plating becomes difficult and the aspect ratio becomes 1 or less. It is desirable to select the via diameter and the film thickness as described above. The aspect ratio here is 4
0 μm / 200 μm = 0.2.
【００２３】図１ｃは、表面銅箔１０２を電気めっきの
電極としてビア穴１０３にめっき銅を充填して銅ビア１
０４を形成した状態を示している。銅めっきには硫酸系
めっき浴を用い、電流密度３Ａ／ｄｍ2の条件でポリイ
ミドフィルム１０１の表面より数μｍ突出させて突起状
電極となるように銅ビア１０４を形成した。この銅ビア
１０４の突起は、配線フィルムを複数層積層する際に隣
接する配線フィルム表面の配線電極とビア接合を形成す
る上で重要な役割を果たす。FIG. 1C shows a copper via 1 filled with plated copper in the via hole 103 using the surface copper foil 102 as an electrode for electroplating.
04 has been formed. For the copper plating, a sulfuric acid-based plating bath was used, and a copper via 104 was formed so as to protrude from the surface of the polyimide film 101 by several μm under a condition of a current density of 3 A / dm 2 to form a protruding electrode. The projection of the copper via 104 plays an important role in forming a via junction with a wiring electrode on an adjacent wiring film surface when a plurality of wiring films are laminated.
【００２４】図１ｄは、図１ｃの工程が完了した後に裏
面に保護フィルム１０６を貼り付け、図では省略した
が、レジスト塗布、露光、現像のいわゆるフォトリソ工
程を行って所要部分にレジスト１０７を残した状態を示
している。この保護膜１０６は、この後エッチング工程
で表面の銅箔１０２を選択的にエッチングする際に、銅
ビア１０４の突起状電極をエッチング液から保護するた
めに設けるものであり、エッチング液に耐性のある市販
のめっきマスキングテープ（粘着フィルム）が使用でき
る。In FIG. 1D, after the step of FIG. 1C is completed, a protective film 106 is attached to the back surface, and although omitted in the figure, a so-called photolithography step of resist application, exposure, and development is performed to leave the resist 107 in a required portion. It shows the state where it was turned on. The protective film 106 is provided to protect the protruding electrodes of the copper vias 104 from the etchant when the copper foil 102 on the surface is selectively etched in an etching step, and has a resistance to the etchant. Certain commercially available plating masking tapes (adhesive films) can be used.
【００２５】図１ｅは、レジスト１０７をエッチングマ
スクとして塩化鉄溶液で不要部分の銅をエッチング除去
して銅箔パターン１０８を形成し、しかる後にレジスト
１０７と保護フィルム１０６を剥離して、更にその後、
無電解めっきで銅表面に錫の層を形成した状態を示して
いる。無電解めっきは７０℃の液温に３０分間浸漬する
ことにより、銅と錫の置換反応で約１μｍのめっき膜を
得ることができる。FIG. 1E shows a copper foil pattern 108 formed by etching away unnecessary portions of copper with an iron chloride solution using the resist 107 as an etching mask, and thereafter, the resist 107 and the protective film 106 are peeled off.
This shows a state in which a tin layer is formed on a copper surface by electroless plating. In the electroless plating, a plating film of about 1 μm can be obtained by immersing in a solution temperature of 70 ° C. for 30 minutes by a substitution reaction between copper and tin.
【００２６】図１ｆは、図１ｅの工程を経て得られたフ
ィルム回路の裏面に接着フィルム１１０を貼り付けた状
態を示している。接着フィルムの貼り付け作業に関して
は図に示していないが、接着材であるエポキシ樹脂を搬
送フィルムであるＰＥＴ（ポリエチレンテレフタレー
ト）フィルムに厚さ２５±２μｍの精度で予め塗布した
フィルムを用いて、フィルム回路の裏面と接着フィルム
のエポキシ面を重ねてロールラミネータで接着する。FIG. 1f shows a state in which the adhesive film 110 is attached to the back surface of the film circuit obtained through the process of FIG. 1e. The work of attaching the adhesive film is not shown in the figure, but a film in which an epoxy resin as an adhesive material is applied in advance to a PET (polyethylene terephthalate) film as a transport film with an accuracy of 25 ± 2 μm in thickness is used. The back surface of the circuit and the epoxy surface of the adhesive film are overlapped and bonded with a roll laminator.
【００２７】このときロールラミネータの温度を８０℃
に設定するとエポキシ樹脂の粘度が低下して接着性が生
じるのでフィルム回路の裏面に接着フィルムを貼り付け
ることができる。接着フィルムをラミネートした後、搬
送フィルムを剥離した状態が図１ｆに示してある。一
方、この８０℃のラミネート温度ではエポキシ樹脂はほ
とんど硬化しないので、接着フィルムは再び温度を加え
ると接着できる、いわゆるＢステージ状態を維持してい
る。図１の例では接着フィルムをフィルム回路の裏面に
ラミネートした例を示しているが、接着フィルムはフィ
ルム回路の表面にラミネートしてもよい。At this time, the temperature of the roll laminator was set to 80 ° C.
When the value is set to, the viscosity of the epoxy resin is reduced to cause adhesion, so that an adhesive film can be attached to the back surface of the film circuit. FIG. 1f shows a state in which the carrier film is peeled off after the adhesive film is laminated. On the other hand, since the epoxy resin hardly cures at the lamination temperature of 80 ° C., the adhesive film maintains the so-called B-stage state where the adhesive film can be adhered when the temperature is applied again. Although the example of FIG. 1 shows an example in which the adhesive film is laminated on the back surface of the film circuit, the adhesive film may be laminated on the surface of the film circuit.
【００２８】図１ｇは、図１ｆまでの工程で得られたフ
ィルム回路を３枚重ねて熱圧着した後の状態を示してい
る。ただし、図では最下層のフィルム回路には銅ビアと
接着フィルムが形成されていない。熱圧着は、温度２３
０℃、圧力１００ｋｇ／ｃｍ2で１０分間行うことによ
り、先ずエポキシ樹脂が溶けて流動し、錫めっきされた
ビアと錫めっきされた銅箔パターンが接触し、錫の相互
拡散により接合が達成できる。ただし、既に述べたが、
このとき下地の銅元素も錫中に溶け込んで接合部分の金
属の融点が上昇するので１０分間の加熱により強固な接
続が達成できる。一方、エポキシ樹脂は２３０℃、１０
分間の加熱により硬化反応はほぼ終了するので圧着圧力
を取り去っても層間の接着は十分保持することが可能で
ある。FIG. 1g shows a state after three film circuits obtained in the steps up to FIG. However, in the drawing, the copper via and the adhesive film are not formed in the lowermost film circuit. Thermocompression bonding, temperature 23
By conducting the process at 0 ° C. and a pressure of 100 kg / cm 2 for 10 minutes, the epoxy resin first melts and flows, and the tin-plated via comes into contact with the tin-plated copper foil pattern, so that bonding can be achieved by the mutual diffusion of tin. . However, as already mentioned,
At this time, the underlying copper element also dissolves into the tin and the melting point of the metal at the joint increases, so that a strong connection can be achieved by heating for 10 minutes. On the other hand, epoxy resin is 230 ° C, 10
Since the curing reaction is almost completed by heating for a minute, adhesion between the layers can be sufficiently maintained even when the pressure is removed.
【００２９】以上、図１ａ〜図１ｇに示した工程により
多層配線基板を得ることができた。すなわち、層間の接
着樹脂として予め搬送フィルム上で膜厚を１０％以下の
ばらつきに正確に制御して作られた接着フィルムを用い
ることにより、積層接着時に余分な接着樹脂が基板面積
の外にはみ出るのを最小限に抑えることが可能になっ
た。As described above, a multilayer wiring board was obtained by the steps shown in FIGS. 1A to 1G. That is, by using an adhesive film that is formed in advance with a film thickness precisely controlled to 10% or less on the transport film as an interlayer adhesive resin, excess adhesive resin protrudes outside the substrate area during lamination. Can be minimized.
【００３０】また、従来は接着樹脂をロールコータで塗
布し、乾燥炉で乾燥する方法を用いていたが、本方法で
はロールラミネータで貼り付けるだけで接着層を形成す
ることが可能であり、且つ、従来方法で問題となる乾燥
むら等による樹脂中の溶媒残りが、接着時にボイドを発
生する等の不良原因も低減できる。Conventionally, a method in which an adhesive resin is applied with a roll coater and dried in a drying oven has been used. However, in this method, an adhesive layer can be formed only by sticking with a roll laminator. In addition, it is also possible to reduce the cause of defects such as residual solvent in the resin due to drying unevenness which is a problem in the conventional method, such as generation of voids at the time of bonding.
【００３１】一方、ビアの接合金属として銅下地上に無
電解錫めっきを行った金属を用いたため、従来方法によ
る２種類の異種金属を接合する方法に比べて製造工程が
簡略化できると共に、銅イオンと錫イオンが置換して錫
が析出するタイプの置換錫めっきは銅金属の表面に選択
的に析出するためにパターンめっき時に特別なマスクを
必要としない利点がある。On the other hand, since a metal obtained by electroless tin plating on a copper base is used as a bonding metal for the via, the manufacturing process can be simplified as compared with the method of bonding two kinds of dissimilar metals by the conventional method, and copper Substituted tin plating, in which ions are replaced with tin ions to deposit tin, has the advantage that a special mask is not required at the time of pattern plating since it is selectively deposited on the surface of copper metal.
【００３２】また、配線フィルムを積層する際には、銅
下地の錫めっきを接合金属に用いることにより、ビアの
接合時に下地の銅が錫中に拡散してきて接合金属の耐熱
性を向上できる効果もある。更に、無電解めっきは電気
めっきのように電源を供給する必要もないので配線パタ
ーンの設計自由度が大幅に向上できる利点もある。Further, when laminating the wiring film, by using tin plating of the copper base as the bonding metal, the base copper diffuses into the tin at the time of connecting the via, and the heat resistance of the bonding metal can be improved. There is also. Further, electroless plating does not require a power supply unlike electroplating, and thus has the advantage that the degree of freedom in designing wiring patterns can be greatly improved.
【００３３】[0033]
【発明の効果】以上詳述したように、本発明により所期
の目的を達成することができた。すなわち、フィルム回
路を複数枚重ねて層間の接着とビアの電気的な接続を同
一の熱処理工程で行うに際して有効な多層回路基板の構
成及びその製造方法を実現することができた。As described in detail above, the intended object has been achieved by the present invention. In other words, it was possible to realize a configuration of a multilayer circuit board and a method of manufacturing the multilayer circuit board which are effective when a plurality of film circuits are stacked and the bonding between layers and the electrical connection of the vias are performed in the same heat treatment step.
【図１】本発明による多層配線基板の製造工程を示した
断面図。FIG. 1 is a cross-sectional view showing a manufacturing process of a multilayer wiring board according to the present invention.
【図２】従来発明による多層配線基板の製造工程を示し
た断面図。FIG. 2 is a cross-sectional view showing a manufacturing process of a multilayer wiring board according to a conventional invention.
１０１，２０１…ポリイミドフィルム １０２，２０２…銅箔 １０３，２０３…ビア穴 １０４，２０４…銅めっきビア ２０５…金めっき膜 １０６，２０６…保護フィルム １０７，２０７…レジスト １０８，２０８…銅箔パターン １０９ …錫めっき膜 １１０ …接着フィルム ２１０…接着樹脂。 101, 201: Polyimide film 102, 202: Copper foil 103, 203: Via hole 104, 204: Copper plating via 205: Gold plating film 106, 206: Protective film 107, 207: Resist 108, 208: Copper foil pattern 109: Tin plating film 110: adhesive film 210: adhesive resin.
───────────────────────────────────────────────────── フロントページの続き (72)発明者 天明 浩之 神奈川県横浜市戸塚区吉田町292番地 株 式会社日立製作所生産技術研究所内 (72)発明者 御田 護 茨城県日立市助川町３丁目１番１号 日立 電線株式会社電線工場内 (72)発明者 佐藤 隆 茨城県日立市助川町３丁目１番１号 日立 電線株式会社電線工場内 Ｆターム(参考） 5E346 AA43 CC32 CC33 DD23 FF07 FF08 FF13 FF24 GG08 GG09 GG15 GG17 GG22 GG28 HH31 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Hiroyuki Tenmei 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Inside of Hitachi, Ltd. Production Technology Research Laboratory (72) Inventor Mamoru Mita 3-1-1 Sukekawacho, Hitachi-shi, Ibaraki No. 1 Hitachi Cable Co., Ltd. Wire Plant (72) Inventor Takashi Sato 3-1-1 Sukekawacho, Hitachi City, Ibaraki Prefecture Hitachi Cable Co., Ltd. Wire Plant F term (reference) 5E346 AA43 CC32 CC33 DD33 FF07 FF08 FF13 FF08 GG08 GG09 GG15 GG17 GG22 GG28 HH31
Claims (5)
ーンを有し、絶縁フィルムの表裏面を貫通して導電性の
ビア穴を有し、そのビア穴と電気的に接続された表裏面
の任意の場所に接続用電極を設けた回路基板同士を、絶
縁層を介して複数枚積層した構造の多層回路基板であっ
て、前記複数の互いに隣接する回路基板同士を電気的に
接続するビアの接合金属として銅下地の錫めっきを用
い、錫銅合金を形成して電気的に接続したことを特徴と
する多層回路基板。An insulating film having a wiring pattern on at least one surface thereof, a conductive via hole penetrating through the front and back surfaces of the insulating film, and an arbitrary one of the front and back surfaces electrically connected to the via hole. A multilayer circuit board having a structure in which a plurality of circuit boards provided with connection electrodes at locations are laminated via an insulating layer, and a bonding metal of a via for electrically connecting the plurality of mutually adjacent circuit boards. A multi-layer circuit board characterized by forming a tin-copper alloy and electrically connecting using tin plating on a copper base.
きを、無電解錫めっきで形成したことを特徴とする請求
項１記載の多層回路基板。2. The multilayer circuit board according to claim 1, wherein tin plating of a copper base is formed by electroless tin plating as a bonding metal of the via.
の裏面からビア穴を形成し、貫通させずにビア穴内から
銅被膜を露出させる工程と、銅めっきにより前記ビア
穴内を埋め込み、絶縁フィルム裏面から突出するまでめ
っきを続けてビア穴に突起電極を形成する工程と、前
記絶縁フィルム上の銅被膜を選択エッチングすることに
より、前記ビア穴と電気的に接続された配線パターンを
形成する工程と、前記配線パターン及びビア穴に設け
られた突起電極に錫めっきする工程と、前記錫めっき
された突起電極を有する絶縁フィルムの少なくとも一方
の面に層間接着材として予め一定の厚さに成形されたフ
ィルム状の接着樹脂を形成する工程と、このようにし
て形成された回路基板材を複数枚積層し、この積層体を
加圧下で加熱して層間の接着とビアの電気的な接続とを
行う工程とを有することを特徴とする多層回路基板の製
造方法。3. A step of forming a via hole from the back surface of the insulating film having a copper film formed on the surface, exposing the copper film from the inside of the via hole without penetrating, and embedding the inside of the via hole by copper plating. Forming a protruding electrode in the via hole by continuing plating until it protrudes from the back surface, and forming a wiring pattern electrically connected to the via hole by selectively etching a copper coating on the insulating film. And a step of tin-plating the protruding electrode provided in the wiring pattern and the via hole, and forming a predetermined thickness as an interlayer adhesive on at least one surface of the insulating film having the tin-plated protruding electrode. Forming a film-like adhesive resin, and laminating a plurality of circuit board materials thus formed, and heating the laminated body under pressure to bond the layers. Method of manufacturing a multilayer circuit board, characterized in that a step of performing the electrical connection of A.
突起電極に錫めっきする工程を、無電解錫めっきで、膜
厚０．３〜１．５μｍの錫めっきする工程としたことを
特徴とする請求項３記載の多層回路基板の製造方法。4. The method according to claim 1, wherein the step of tin-plating the wiring pattern and the protruding electrode provided in the via hole is a step of tin-plating with a thickness of 0.3 to 1.5 μm by electroless tin plating. The method for manufacturing a multilayer circuit board according to claim 3.
ッチングするに際しては、予め絶縁フィルム裏面のビア
穴に形成した突起電極をエッチング液から保護するよう
に保護膜を設けた状態でエッチングすることを特徴とす
る請求項３記載の多層回路基板の製造方法。5. When selectively etching the copper film on the insulating film, the copper film on the insulating film is etched with a protective film provided so as to protect a projecting electrode formed in a via hole on the back surface of the insulating film from an etching solution. 4. The method for manufacturing a multilayer circuit board according to claim 3, wherein:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9714199A JP2000294933A (en) | 1999-04-05 | 1999-04-05 | Multilayer circuit substrate and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9714199A JP2000294933A (en) | 1999-04-05 | 1999-04-05 | Multilayer circuit substrate and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2000294933A true JP2000294933A (en) | 2000-10-20 |
Family
ID=14184304
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9714199A Pending JP2000294933A (en) | 1999-04-05 | 1999-04-05 | Multilayer circuit substrate and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2000294933A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002319762A (en) * | 2001-04-20 | 2002-10-31 | Toppan Printing Co Ltd | Multilayer wiring board |
| JP2003318544A (en) * | 2002-04-22 | 2003-11-07 | Toppan Printing Co Ltd | Multilayer wiring board and its manufacturing method |
| JP2007048825A (en) * | 2005-08-08 | 2007-02-22 | Sumitomo Bakelite Co Ltd | Joining method, joint part structure, wiring board, and manufacturing method thereof |
| JP2010258219A (en) * | 2009-04-24 | 2010-11-11 | Nippon Chemicon Corp | Method for manufacturing electrolytic capacitor and electrolytic capacitor |
| CN113784548A (en) * | 2021-08-10 | 2021-12-10 | 深圳市信维通信股份有限公司 | Preparation method of sandwich adhesive layer and preparation method of multilayer circuit board |
-
1999
- 1999-04-05 JP JP9714199A patent/JP2000294933A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002319762A (en) * | 2001-04-20 | 2002-10-31 | Toppan Printing Co Ltd | Multilayer wiring board |
| JP2003318544A (en) * | 2002-04-22 | 2003-11-07 | Toppan Printing Co Ltd | Multilayer wiring board and its manufacturing method |
| JP2007048825A (en) * | 2005-08-08 | 2007-02-22 | Sumitomo Bakelite Co Ltd | Joining method, joint part structure, wiring board, and manufacturing method thereof |
| JP2010258219A (en) * | 2009-04-24 | 2010-11-11 | Nippon Chemicon Corp | Method for manufacturing electrolytic capacitor and electrolytic capacitor |
| CN113784548A (en) * | 2021-08-10 | 2021-12-10 | 深圳市信维通信股份有限公司 | Preparation method of sandwich adhesive layer and preparation method of multilayer circuit board |
| CN113784548B (en) * | 2021-08-10 | 2024-04-16 | 深圳市信维通信股份有限公司 | Sandwich adhesive layer preparation method and multilayer circuit board preparation method |
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