JPH11243230A - Light-emitting diode chip and method of manufacturing the same - Google Patents

Light-emitting diode chip and method of manufacturing the same

Info

Publication number
JPH11243230A
JPH11243230A JP10349480A JP34948098A JPH11243230A JP H11243230 A JPH11243230 A JP H11243230A JP 10349480 A JP10349480 A JP 10349480A JP 34948098 A JP34948098 A JP 34948098A JP H11243230 A JPH11243230 A JP H11243230A
Authority
JP
Japan
Prior art keywords
emitting diode
light emitting
chip
chips
coating layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP10349480A
Other languages
Japanese (ja)
Other versions
JP3312120B2 (en
Inventor
Atsushi Okazaki
淳 岡崎
Yoshihei Tani
善平 谷
Shiyuuzou Abe
宗造 阿部
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP34948098A priority Critical patent/JP3312120B2/en
Publication of JPH11243230A publication Critical patent/JPH11243230A/en
Application granted granted Critical
Publication of JP3312120B2 publication Critical patent/JP3312120B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/075—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
    • H01L25/0753—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Led Devices (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Led Device Packages (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a small, thin, and low-cost light-emitting diode chip capable of being mounted directly on the surface of a printed circuit board without through a bonding wire. SOLUTION: This light-emitting diode chip comprises a plurality of chips connected by a conductive material or solder 6 in an orthogonal direction of the P-N junction face at a positive and negative electrode sections 3 and 4 formed on both end faces in parallel with the P-N junction face of the chips, and the electrode 3 and 4 of both ends of the connected sequential chip have a solder coating layer 5 on their surfaces.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は、配線基板の表面に
ボンディングワイヤを介さずに直接実装できる極めて小
型かつ薄型のチップ部品型の発光ダイオード及びその製
造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an extremely small and thin chip part type light emitting diode which can be directly mounted on the surface of a wiring board without using bonding wires, and a method of manufacturing the same.

【０００２】[0002]

【従来の技術】発光ダイオードは、表示パネルや液晶表
示装置のバックライト、携帯機器のインジケータ、照光
スイッチおよびＯＡ機器の光源等として用いられ、従
来、例えば図６に示すようなものが知られている。2. Description of the Related Art Light emitting diodes are used as backlights of display panels and liquid crystal display devices, indicators of portable equipment, illumination switches, light sources of OA equipment, and the like. I have.

【０００３】この発光ダイオードは、隙間をあけて対向
する１対のリード端子の一方２６の先端に、発光ダイオ
ード２１の下面の電極２２を導電性ペースト２４で接着
し、上面の電極２３をボンディングワイヤとしての金線
２５で他方のリード端子２７の先端に接続するととも
に、これと同じものを図６(Ａ)に示すように長手方向に
並べて、これらを透明の樹脂２８内にモールドしたもの
である。この例では、図中左側のリード端子２７が陰
極,右側のリード端子２６が陽極であり、製品の長さＬ,
幅Ｗ,高さＨは、夫々Ｌ＝2.9mm，Ｗ＝1.5mm，Ｈ＝1.1mm
であり、発光ダイオード間の距離は、0.8mmである。そ
して、モールドで作られた発光ダイオードは、図示しな
い配線基板上の配線パターンに各リード端子２６,２７
を載せ、両者をはんだ付けして実装される。In this light-emitting diode, an electrode 22 on the lower surface of a light-emitting diode 21 is bonded to the tip of one of a pair of lead terminals 26 facing each other with a gap with a conductive paste 24, and the electrode 23 on the upper surface is bonded to a bonding wire. 6A is connected to the tip of the other lead terminal 27 by a gold wire 25, and the same one is arranged in the longitudinal direction as shown in FIG. 6A, and these are molded in a transparent resin 28. . In this example, the left lead terminal 27 in the figure is a cathode, and the right lead terminal 26 is an anode.
The width W and height H are L = 2.9 mm, W = 1.5 mm, H = 1.1 mm, respectively.
And the distance between the light emitting diodes is 0.8 mm. Then, the light emitting diodes made by molding are connected to respective lead terminals 26 and 27 on a wiring pattern on a wiring board (not shown).
Are mounted, and both are soldered and mounted.

【０００４】[0004]

【発明が解決しようとする課題】ところが、上記従来の
発光ダイオードは、上方に凸をなすリード端子の一方２
６の先端に発光ダイオードチップ２１の下面電極２２を
接着し、上面電極２３を金線２５でリード端子の他方２
７にボンディングし、金線２５等を外力から保護すべく
樹脂２８内にモールドするものである為、チップ自体の
高さは、0.2〜0.3mmであるにすぎないのに、製品全体の
高さが、上述の如く1.1mmと３倍程度にもなり、配線基
板上にかなりのスペースを必要とする。また、構成部材
が多い為、材料費や加工費が嵩み、製品のコストアップ
を招くという問題がある。However, the above-mentioned conventional light emitting diode has one of two lead terminals projecting upward.
6, the lower electrode 22 of the light emitting diode chip 21 is adhered to the tip of the light emitting diode chip 21.
7 and molded in the resin 28 to protect the gold wire 25 and the like from external force, the height of the chip itself is only 0.2 to 0.3 mm, but the height of the entire product However, as described above, it is about three times as large as 1.1 mm, and a considerable space is required on the wiring board. Further, since there are many constituent members, there is a problem that the material cost and the processing cost are increased and the cost of the product is increased.

【０００５】そこで、本発明の目的は、発光ダイオード
チップ自体の構造を工夫することによって、配線基板の
表面にボンディングワイヤを介さずに直接実装できて、
コストダウンが図れ、かつ実装の際のろう材の供給がい
らない極めて小型かつ薄型のチップ部品型の発光ダイオ
ードおよびその製造方法を提供することにある。Therefore, an object of the present invention is to improve the structure of the light emitting diode chip itself so that it can be directly mounted on the surface of the wiring board without using bonding wires.
An object of the present invention is to provide an extremely small and thin chip component type light emitting diode which can reduce the cost and does not require the supply of brazing material during mounting, and a method for manufacturing the same.

【０００６】[0006]

【課題を解決するための手段】上記目的を達成するた
め、請求項に１記載の発明のチップ部品型の発光ダイオ
ードは、配線基板の表面にボンディングワイヤを介さず
直接実装できるものであって、複数のチップが、そのチ
ップのＰＮ接合面と平行をなす両端面に設けられた正,
負の電極部において、上記ＰＮ接合面と直交する方向に
順次導電材料またはろう材によって接続され、接続され
た一連のチップの両端の電極部が、表面にろう材のコー
ティング層を有することを特徴とする。In order to achieve the above object, a chip component type light emitting diode according to the first aspect of the present invention can be directly mounted on a surface of a wiring board without using a bonding wire. Plural chips are provided on both ends parallel to the PN junction surface of the chip.
The negative electrode portion is sequentially connected by a conductive material or a brazing material in a direction perpendicular to the PN junction surface, and the electrode portions at both ends of a series of connected chips have a brazing material coating layer on the surface. And

【０００７】すなわち、請求項１に記載の発光ダイオー
ドは、複数のチップを導電材料またはろう材で順次接続
してなる一連のチップの両端の電極部の表面が、ろう材
でコーティングされている。従って、発光ダイオードの
寸法が、略一連のチップ自体の寸法まで小型化,薄型化
できる。また、発光ダイオードの両端の電極部および中
間のろう材接続部を、配線基板上の一方,他方および中
間の配線パターン上に夫々垂直に載せ、炉中等で上記ろ
う材の融点以上に加熱すると、両電極部および中間接続
部のろう材が溶融して各配線パターンとのろう接が行な
われる。That is, in the light emitting diode according to the first aspect, the surfaces of the electrode portions at both ends of a series of chips formed by sequentially connecting a plurality of chips with a conductive material or a brazing material are coated with a brazing material. Therefore, the size of the light emitting diode can be reduced and reduced to approximately the size of a series of chips themselves. Further, when the electrode portions at both ends of the light emitting diode and the intermediate brazing material connection portion are placed vertically on one, the other and the intermediate wiring pattern on the wiring board, respectively, and heated in a furnace or the like to the melting point of the brazing material or more, The brazing material at both electrode portions and the intermediate connecting portion is melted and soldered to each wiring pattern.

【０００８】請求項２に記載の発明のチップ部品型の発
光ダイオードは、請求項１に記載のチップ部品型の発光
ダイオードにおいて、上記一連のチップの両端面以外の
側面の少なくとも１つが、表面に絶縁材料のコーティン
グ層を有することを特徴とする。According to a second aspect of the present invention, there is provided the chip component type light emitting diode according to the first aspect, wherein at least one of the side surfaces other than both end surfaces of the series of chips is provided on the surface. It has a coating layer of an insulating material.

【０００９】請求項２に記載の発光ダイオードは、一連
のチップの両端面以外の側面の少なくとも１つが、表面
に絶縁材料のコーティング層を有するので、発光ダイオ
ードの絶縁材料でコーティングされた側面を、配線基板
面に対向させ、かつ両端の電極部および中間のろう材接
続部を、配線基板上の一方,他方および中間の配線パタ
ーン上に夫々垂直に載せ、炉中等で上記ろう材の融点以
上に加熱すると、両電極部および中間接続部のろう材が
溶融して各配線パターンとのろう接が行なわれる。この
実装時にチップに加わる外力が、側面の絶縁材料のコー
ティング層で緩和されるので、実装された発光ダイオー
ドの信頼性がより向上する。According to a second aspect of the present invention, at least one of the side faces other than the both end faces of the series of chips has a coating layer of an insulating material on the surface, so that the side face coated with the insulating material of the light emitting diode has Opposite to the wiring board surface, the electrodes at both ends and the intermediate brazing material connection are placed vertically on one, the other, and the intermediate wiring pattern on the wiring board, respectively, and in a furnace or the like, the melting point of the brazing material or higher is exceeded. When heated, the brazing material at both electrode portions and the intermediate connection portion is melted and soldered to each wiring pattern. Since the external force applied to the chip at the time of mounting is reduced by the coating layer of the insulating material on the side surface, the reliability of the mounted light emitting diode is further improved.

【００１０】また、請求項３に記載の発明の発光ダイオ
ードの製造方法は、複数枚のウエハ状態の発光ダイオー
ドの表,裏面に設けられた正,負の電極部を、ろう材また
は導電材料によってコーティングした後、これらのウエ
ハを両端面にろう材のコーティング層が現われるように
重ねて接合し、次いで重ねて接合されたウエハを縦横に
ダイシングすることを特徴とする。According to a third aspect of the present invention, there is provided a method of manufacturing a light emitting diode, wherein the positive and negative electrode portions provided on the front and rear surfaces of the plurality of light emitting diodes in a wafer state are made of a brazing material or a conductive material. After coating, these wafers are overlapped and joined so that a coating layer of brazing material appears on both end surfaces, and then the overlapped and joined wafers are vertically and horizontally diced.

【００１１】したがって、請求項３に記載の発光ダイオ
ードの製造方法によれば、複数枚のウエハ状態の発光ダ
イオードの表,裏面の電極部のろう材または導電材料に
よるコーティングと、両端面にろう材のコーティング層
が現われるようにした上記複数ウエハの重ね接合とをウ
エハの状態で一括して行なえ、しかも、従来のワイヤボ
ンディングや樹脂モールドが不要になるので、極めて小
型かつ薄型のチップ部品型の請求項１に記載の発光ダイ
オードを安価に製造することができる。Therefore, according to the method of manufacturing a light emitting diode according to the third aspect, the front and back electrode portions of the plurality of light emitting diodes in a wafer state are coated with a brazing material or a conductive material, and the brazing materials are formed on both end surfaces. The above-mentioned superposition bonding of a plurality of wafers such that the coating layer appears can be performed collectively in the state of a wafer, and furthermore, since conventional wire bonding and resin molding are not required, an extremely small and thin chip component type is required. Item 1 can be manufactured at a low cost.

【００１２】また、請求項４に記載の発明の発光ダイオ
ードの製造方法は、請求項３に記載の発光ダイオードの
製造方法において、上記のダイシングにより分離された
各チップの側面を、絶縁材料によってコーティングする
ことを特徴とする。According to a fourth aspect of the present invention, there is provided a method for manufacturing a light emitting diode according to the third aspect, wherein the side surface of each chip separated by dicing is coated with an insulating material. It is characterized by doing.

【００１３】したがって、請求項４に記載の発光ダイオ
ードの製造方法によれば、ダイシングで分離された各チ
ップの側面の絶縁材料によるコーティングをもウエハの
状態で一括して行なえので、極めて小型かつ薄型のチッ
プ部品型の請求項２に記載の発光ダイオードを安価に製
造することができる。Therefore, according to the method of manufacturing a light emitting diode of the present invention, the coating of the side surface of each chip separated by dicing with the insulating material can be performed collectively in the state of a wafer, so that it is extremely small and thin. The light emitting diode according to the second aspect of the present invention can be manufactured at low cost.

【００１４】[0014]

【発明の実施の形態】以下、本発明の実施の一形態につ
いて、図面を参照して説明する。まず、参考例について
説明する。An embodiment of the present invention will be described below with reference to the drawings. First, a reference example will be described.

【００１５】図１(Ａ)は、参考例のチップ部品型の発光
ダイオードを示す斜視図である。この発光ダイオード
は、互いに接合されるＰ型層１およびＮ型層２と、この
Ｐ型,Ｎ型層１,２の端面にＰＮ接合面と平行に互いに対
向して設けられたＰ型,Ｎ型の電極部３,４と、この電極
部３,４の表面に設けられたろう材としてのはんだのコ
ーティング層５,６と、このコーティング層５,６以外の
４つの側面の表面に設けられた絶縁材料としての絶縁樹
脂のコーティング層７(図２(Ｃ),(Ｄ)参照)からなり、
直方体状のチップを呈する。FIG. 1A is a perspective view showing a chip component type light emitting diode of a reference example. This light-emitting diode comprises a P-type layer 1 and an N-type layer 2 joined to each other, and P-type and N-type layers provided at end faces of the P-type and N-type layers 1 and 2 in parallel with a PN junction surface. Mold electrode portions 3, 4; solder coating layers 5, 6 as brazing material provided on the surfaces of the electrode portions 3, 4; and four side surfaces other than the coating layers 5, 6 It consists of a coating layer 7 of an insulating resin as an insulating material (see FIGS. 2C and 2D).
Presenting a rectangular chip.

【００１６】上記構成の発光ダイオードは、配線基板上
に次のようにして実装される。即ち、図１(Ａ)に示すよ
うに、発光ダイオードのチップを横向きにして、両端の
はんだコーティングされた電極部３,４を、配線基板８
上の一方,他方の配線パターン９a,９bに垂直に載せ、絶
縁樹脂コーティングされた底部中央を接着剤１０で配線
基板８に仮止めする。次いで、この配線基板８を、はん
だの融点以上に加熱されたリフロー炉に入れると、図１
(Ｂ)に示すように、両端の電極部３,４のはんだ５,６が
溶融して両電極部３,４と配線パターン９a,９bとのはん
だ付けが夫々行なわれる。上記発光ダイオードは、図６
で述べた従来例のような配線基板から突出するリード端
子２６,２７,ボンディングワイヤ２５,モールド樹脂２
８がないので、その寸法を略素子チップ自体の寸法まで
減じて小型化,薄型化が図れるとともに、ボンディング
ワイヤが外力や熱応力で断線することもないうえ、実装
時にチップに加わる外力が、側面の絶縁樹脂のコーティ
ング層７で緩和されるので、実装された発光ダイオード
の信頼性が向上する。さらに、配線パターンへの接続作
業が容易,迅速,高精度に行なえるとともに、クリームは
んだのスクリーン印刷等によってはんだを供給する必要
がなく、部品点数の減少による材料費,加工費の低減と
相俟って、実装作業のコストダウンを図ることができ
る。The light emitting diode having the above configuration is mounted on a wiring board as follows. That is, as shown in FIG. 1A, the light emitting diode chip is turned sideways, and the solder coated electrode portions 3 and 4 at both ends are connected to the wiring board 8.
It is placed vertically on the upper and lower wiring patterns 9a and 9b, and the center of the bottom coated with the insulating resin is temporarily fixed to the wiring substrate 8 with an adhesive 10. Next, when the wiring board 8 is put into a reflow furnace heated to a temperature equal to or higher than the melting point of the solder, FIG.
As shown in (B), the solders 5, 6 of the electrode portions 3, 4 at both ends are melted, and the soldering of the electrode portions 3, 4 and the wiring patterns 9a, 9b is performed respectively. The light emitting diode is shown in FIG.
Lead terminals 26, 27, bonding wires 25, molding resin 2 protruding from the wiring board as in the conventional example described in
Since there is no 8, the size can be reduced to substantially the size of the element chip itself to achieve a reduction in size and thickness, the bonding wire does not break due to external force or thermal stress, and the external force applied to the chip during mounting is This is alleviated by the insulating resin coating layer 7, so that the reliability of the mounted light emitting diode is improved. Furthermore, the connection to the wiring pattern can be performed easily, quickly and with high precision, and there is no need to supply solder by screen printing of cream solder, etc., which reduces material and processing costs due to a reduction in the number of parts. Thus, the cost of the mounting operation can be reduced.

【００１７】図２は、上記発光ダイオードの製造方法
を、参考例として示している。上記発光ダイオードは、
ウエハ１１状態の発光ダイオードの表,裏面に形成され
たＰ型,Ｎ型の電極部３,４を、はんだで被覆してはんだ
コーティング層５,６を設けた後、図２(Ａ)に示すよう
に、Ｎ側のはんだコーティング層６をシート１２上に載
せて貼り付ける。次に、図２(Ｂ)の如く、ウエハ１１を
縦横にダイシングして各チップに分離し、さらに、図２
(Ｃ)の如く、各チップの上面をシート１３でマスキング
し、各チップの側面方向から保護用の絶縁樹脂を注入し
て硬化させ、側面のコーティング層７を形成する。最後
に、図２(Ｄ)に示すように、上面のシートを除去すれ
ば、各チップが完成する。FIG. 2 shows a method for manufacturing the light emitting diode as a reference example. The light emitting diode,
After the P-type and N-type electrode portions 3 and 4 formed on the front and back surfaces of the light emitting diode in the state of the wafer 11 are covered with solder to provide solder coating layers 5 and 6, as shown in FIG. Thus, the N-side solder coating layer 6 is placed on the sheet 12 and attached. Next, as shown in FIG. 2 (B), the wafer 11 is diced vertically and horizontally to separate each chip.
As shown in (C), the upper surface of each chip is masked with a sheet 13, and a protective insulating resin is injected from the side surface direction of each chip and cured to form a coating layer 7 on the side surface. Finally, as shown in FIG. 2 (D), if the sheet on the upper surface is removed, each chip is completed.

【００１８】上述の製造方法では、Ｐ型,Ｎ型の電極部
３,４のはんだによるコーティングと、絶縁樹脂による
側面のコーティングとをウエハ１１の状態で一括して行
なえ、しかも、従来のワイヤボンディングや樹脂モール
ドが不要になるので、極めて小型かつ薄型のチップ部品
型の発光ダイオードを安価に製造することができる。な
お、上記参考例では、電極部３,４をコーティングする
ろう材を、はんだとしたが、これを比較的低融点の他の
ろう材にすることもできる。また、チップ側面のコーテ
ィング層７は、参考例の絶縁樹脂に限らず、絶縁材料で
あればセラミック,ガラス等でもよく、また、参考例の
ように４つの側面の総てでなく、配線基板８に対向する
１つの側面のみに設けてもよい。さらに、図２(Ｃ)の上
面のマスキングシート１３は、コーティング層７の絶縁
材料と反応しないレジスト膜であってもよく、また、マ
スキングシート１３を省略して、ダイシングでできた溝
に絶縁樹脂を滴下してチップ側面のコーティング層７を
形成することもできる。According to the above-described manufacturing method, the coating of the P-type and N-type electrode portions 3 and 4 with the solder and the coating of the side surfaces with the insulating resin can be collectively performed in the state of the wafer 11, and the conventional wire bonding is performed. Since no resin mold is required, an extremely small and thin light emitting diode of a chip component type can be manufactured at low cost. In the above-mentioned reference example, the brazing material for coating the electrode portions 3 and 4 is solder, but it can be another brazing material having a relatively low melting point. Further, the coating layer 7 on the side surface of the chip is not limited to the insulating resin of the reference example, but may be ceramic, glass, or the like as long as it is an insulating material. May be provided only on one side face facing the. Further, the masking sheet 13 on the upper surface of FIG. 2C may be a resist film that does not react with the insulating material of the coating layer 7. Alternatively, the masking sheet 13 may be omitted, and the insulating resin may be formed in the groove formed by dicing. To form the coating layer 7 on the side surface of the chip.

【００１９】次に、本発明の実施の形態について説明す
る。図３(Ａ)は、本発明の請求項１，２に記載のチップ
部品型の発光ダイオードの実施の一形態を示す斜視図で
ある。この発光ダイオードは、図１（Ａ)で述べたと同
じチップ２つを、Ｎ型の電極部４の表面に設けたはんだ
のコーティング層６同士で接合して、ＰＮ接合面と直交
する方向に伸びる長いチップとしたものである。従っ
て、図１(Ａ)で述べたと同じ部材には、同一番号を付し
て説明を省略する。Next, an embodiment of the present invention will be described. FIG. 3A is a perspective view showing an embodiment of a chip component type light emitting diode according to claims 1 and 2 of the present invention. In this light emitting diode, the same two chips as described with reference to FIG. 1A are joined together by a solder coating layer 6 provided on the surface of the N-type electrode portion 4, and extend in a direction orthogonal to the PN junction surface. It is a long chip. Therefore, the same members as those described with reference to FIG.

【００２０】上記発光ダイオードは、図３(Ｂ)に示すよ
うに、チップを横向きにして、両端のはんだコーティン
グされた電極部５,５を、配線基板８上の一方,他方の配
線パターン９a,９bに、中央のはんだコーティングされ
た電極部４,４を、中間の配線パターン９cに夫々垂直に
載せられ、絶縁樹脂コーティングされた底部両側を接着
剤１０,１０で配線基板８に仮止めされる。次いで、こ
の配線基板８が、はんだの融点以上に加熱されたリフロ
ー炉に入れられると、図３(Ｂ)に示すように、両端の電
極部３,３のはんだ５,５および中央の電極部４,４間の
はんだ６が溶融して、これらの電極部と配線パターン９
a,９b,９cとがはんだ付けされる。上記発光ダイオード
も、図１で述べた参考例と同様、従来例の如きボンディ
ングワイヤ２５(図６参照)やモールド樹脂２８等がない
ので、その寸法を略素子チップ自体の寸法にまで減じて
小型化,薄型化が図れるとともに、ボンディングワイヤ
が外力や熱応力で断線することもないうえ、実装時にチ
ップに加わる外力が、側面の絶縁樹脂のコーティング層
７で緩和されるので、実装された発光ダイオードの信頼
性が向上する。さらに、配線パターンへの接続作業が容
易,迅速,高精度にでき、部品点数の減少による材料費,
加工費の低減と相俟って、実装作業のコストダウンを図
ることができる。In the light emitting diode, as shown in FIG. 3B, the chip is turned sideways, and the solder-coated electrode portions 5, 5 at both ends are connected to one and the other wiring pattern 9a, 9b, the central solder-coated electrode portions 4, 4 are placed vertically on the intermediate wiring pattern 9c, respectively, and both sides of the bottom portion coated with the insulating resin are temporarily fixed to the wiring board 8 with adhesives 10, 10. . Next, when the wiring board 8 is put into a reflow furnace heated to a temperature not lower than the melting point of the solder, as shown in FIG. The solder 6 between the electrodes 4 and 4 is melted, and these electrode portions and the wiring pattern 9 are melted.
a, 9b, 9c are soldered. Since the light emitting diode does not have the bonding wire 25 (see FIG. 6) and the mold resin 28 as in the conventional example, similarly to the reference example described with reference to FIG. 1, the size of the light emitting diode is reduced to substantially the size of the element chip itself. In addition to reducing the thickness and thickness, the bonding wire does not break due to external force or thermal stress, and the external force applied to the chip during mounting is reduced by the coating layer 7 of the insulating resin on the side surface. Reliability is improved. Furthermore, the connection work to the wiring pattern can be done easily, quickly and with high accuracy, and the material cost due to the reduction in the number of parts,
The cost of the mounting operation can be reduced together with the reduction of the processing cost.

【００２１】図４は、図３で述べた発光ダイオードの製
造方法を、請求項３，４に記載の製造方法の実施の一形
態として示している。上記発光ダイオードは、まず、ウ
エハの表,裏面にあたるＰ,Ｎ型の電極部３,４を、夫々
はんだで被覆してはんだコーティング層５,６設けて２
枚のウエハ１１,１１を製作した後、両ウエハをはんだ
コーティング層６,６で互いに重ね合わせ、リフロー炉
内などで接合して一体のウエハ１４とし、図３（Ａ)に
示すように、Ｐ側のはんだコーティング層５をシート１
２上に載せて貼り付ける。次に、図３(Ｂ)の如く、ウエ
ハ１４を縦横にダイシングして各チップに分離し、更
に、図３(Ｃ)の如く、各チップの上面に塗布によってレ
ジスト層１５を形成し、各チップの側面方向から保護用
の絶縁樹脂を注入して硬化させ、側面のコーティング層
７を形成する。最後に、図３(Ｄ)に示すように、上面の
レジスト層１５を除去すれば、各チップが完成する。な
お、この発光ダイオードの回路図は、図５(Ａ)に示すと
おりであり、例えば一方を赤色,他方を緑色のものとす
れば、２色表示の発光ダイオードを構成できる。FIG. 4 shows a method of manufacturing the light emitting diode described in FIG. 3 as an embodiment of the manufacturing method according to the third and fourth aspects. In the light-emitting diode, first, P and N-type electrode portions 3 and 4 on the front and back surfaces of the wafer are respectively coated with solder to provide solder coating layers 5 and 6.
After the wafers 11, 11 are manufactured, the two wafers are overlaid on each other with the solder coating layers 6, 6 and joined together in a reflow furnace or the like to form an integrated wafer 14, as shown in FIG. Apply the solder coating layer 5 on the side of sheet 1
Put on 2 and paste. Next, as shown in FIG. 3B, the wafer 14 is diced vertically and horizontally to separate each chip, and as shown in FIG. 3C, a resist layer 15 is formed on the upper surface of each chip by coating. Insulating resin for protection is injected from the side of the chip and hardened to form a coating layer 7 on the side. Finally, as shown in FIG. 3D, each chip is completed by removing the resist layer 15 on the upper surface. The circuit diagram of this light-emitting diode is as shown in FIG. 5A. For example, if one is red and the other is green, a two-color display light-emitting diode can be formed.

【００２２】上記製造方法では、２枚の発光ダイオード
ウエハの表,裏面の電極部のはんだによるコーティング
と、両ウエハの重ね接合と、ダイシングで分離された各
チップの側面の絶縁樹脂によるコーティングとを、ウエ
ハの状態で一括して行なえ、しかも、従来のワイヤボン
ディングや樹脂モールドが不要になり、中央の電極部
４,４を含む電極部の接合にはんだの供給がいらず、極
めて小型かつ薄型のチップ部品型の直列接続の発光ダイ
オードを安価に製造することができる。なお、上記２色
表示の発光ダイオードを例にとれば、その長さＬ,幅Ｗ,
高さＨは、Ｌ＝0.5mm,Ｗ＝0.3mm,Ｈ＝0.3mmとなって、
図６の従来例のもののＬ,Ｗ,Ｈと比して、いずれも略１
／３に短縮している。上記実施の形態では、中間の電極
部４,４間をろう材としてのはんだで接合したが、この
電極部４,４を配線パターン９cに接続する必要がない場
合は、上記電極部間を導電材料で接合してもよい。ま
た、図２の参考例で述べたと同様、両端の電極部をコー
ティングするろう材を、はんだ以外の低融点ろう材と
し、チップ側面のコーティング層を、セラミック,ガラ
ス等の絶縁材料とし、１つの側面のみにコーティングす
るようにしてもよい。また、上面のレジスト層１５を、
マスキングシートに代えてもよく、これらを省略して、
ダイシング溝に絶縁材料を滴下してチップ側面をコーテ
ィングすることもできる。In the above-described manufacturing method, the coating of the electrode portions on the front and rear surfaces of the two light emitting diode wafers with the solder, the overlapping joining of the two wafers, and the coating of the side surfaces of the chips separated by dicing with the insulating resin are performed. It can be performed in a batch in the state of a wafer, and furthermore, the conventional wire bonding and resin molding become unnecessary, and no solder is supplied to the joining of the electrode parts including the central electrode parts 4 and 4, so that it is extremely small and thin. Chip-part series-connected light-emitting diodes can be manufactured at low cost. If the above-described two-color display light-emitting diode is taken as an example, its length L, width W,
The height H is L = 0.5mm, W = 0.3mm, H = 0.3mm,
In comparison with the L, W, and H of the conventional example shown in FIG.
/ 3. In the above embodiment, the intermediate electrode portions 4 and 4 were joined by solder as a brazing material. However, when it is not necessary to connect the electrode portions 4 and 4 to the wiring pattern 9c, a conductive material is connected between the electrode portions. You may join with a material. Also, as described in the reference example of FIG. 2, the brazing material for coating the electrode portions at both ends is a low melting point brazing material other than solder, and the coating layer on the side of the chip is an insulating material such as ceramic or glass. You may make it coat only a side surface. Further, the resist layer 15 on the upper surface is
It may be replaced with a masking sheet, omitting these,
An insulating material may be dropped on the dicing groove to coat the chip side surface.

【００２３】図５(Ｂ)〜(Ｅ)は、上述の請求項３，４の
製造方法で作られる請求項１，２に係る直列接続の発光
ダイオードの種々の変形例を、回路図で示している。こ
れらの図で、各発光ダイオード素子の接続点のうち、端
子の表示があるものは、はんだなどのろう材で接合され
るが、それ以外のものは、導電材料で接合すれば足り
る。FIGS. 5B to 5E are circuit diagrams showing various modifications of the series-connected light emitting diodes according to the first and second aspects of the present invention. ing. In these figures, of the connection points of the respective light emitting diode elements, those with the terminal indication are joined by a brazing material such as solder, but the other points need only be joined by a conductive material.

【００２４】[0024]

【発明の効果】以上の説明で明らかなように、請求項１
に記載の発明のチップ部品型の発光ダイオードは、複数
のチップが、そのチップのＰＮ接合面と平行をなす両端
面に設けられた正,負の電極部において、上記ＰＮ接合
面と直交する方向に順次導電材料またはろう材によって
接続され、接続された一連のチップの両端面の電極部
が、表面にろう材のコーティング層を有しているので、
従来のボンディングワイヤやモールド樹脂がなくて、寸
法を一連のチップ自体の寸法にまで略減少して小型化,
薄型化が図れ、ボンディングワイヤの断線の虞もなくて
信頼性が向上し、配線基板のパターンへの接続作業がは
んだ等の供給なしで容易,迅速,高精度に行なえ、部品点
数の減少による材料費,加工費の低減と相俟って、実装
作業のコストダウンを一層図ることができる。As is apparent from the above description, claim 1
In the chip component type light-emitting diode according to the invention described in (1), a plurality of chips are provided in both positive and negative electrode portions provided on both end surfaces parallel to the PN junction surface of the chip, in a direction orthogonal to the PN junction surface. Are sequentially connected by a conductive material or a brazing material, and since the electrode portions on both end surfaces of a series of connected chips have a brazing material coating layer on the surface,
Without conventional bonding wires and molding resin, the dimensions are reduced to the size of a series of chips themselves, miniaturizing,
The thickness can be reduced, the reliability is improved without the risk of breaking the bonding wire, the connection work to the pattern on the wiring board can be done easily, quickly and accurately without the supply of solder etc. The cost of the mounting operation can be further reduced in conjunction with the reduction of the cost and the processing cost.

【００２５】さらに、請求項２に記載の発明のチップ部
品型の発光ダイオードは、上記一連のチップの両端面以
外の側面の少なくとも１つが、表面に絶縁材料のコーテ
ィング層を有しているので、実装時にチップに加わる外
力が、側面の絶縁材料のコーティング層で緩和されるの
で、実装された発光ダイオードの信頼性がより向上す
る。Furthermore, in the chip component type light emitting diode according to the second aspect of the present invention, at least one of the side surfaces other than both end surfaces of the series of chips has a coating layer of an insulating material on the surface. Since the external force applied to the chip during mounting is reduced by the coating layer of the insulating material on the side surface, the reliability of the mounted light emitting diode is further improved.

【００２６】また、請求項３に記載の発明の発光ダイオ
ードの製造方法は、複数枚のウエハ状態の発光ダイオー
ドの表,裏面に設けられた正,負の電極部を、ろう材また
は導電材料によってコーティングした後、これらのウエ
ハを両端面にろう材のコーティング層が現われるように
重ねて接合し、次いで重ねて接合されたウエハを縦横に
ダイシングするので、ろう材または導電材料による中間
コーティングと、ろう材による両端電極部のコーティン
グとをウエハ状態で一括してでき、従来のワイヤボンデ
ィングや樹脂モールドが不要になって、極めて小型かつ
薄型の請求項１に記載の発光ダイオードを一層安価に製
造することができる。According to a third aspect of the present invention, in the method of manufacturing a light emitting diode, the positive and negative electrode portions provided on the front and rear surfaces of the plurality of light emitting diodes in a wafer state are made of a brazing material or a conductive material. After coating, these wafers are overlapped and bonded so that a coating layer of brazing material appears on both end surfaces, and then the overlapped and bonded wafers are diced vertically and horizontally, so that an intermediate coating with brazing material or conductive material and 2. The light-emitting diode according to claim 1, wherein the light-emitting diode according to claim 1 can be coated with the material at both ends in a wafer state, eliminating the need for conventional wire bonding and resin molding, and being extremely small and thin. Can be.

【００２７】また、請求項４に記載の発明の発光ダイオ
ードの製造方法は、上記のダイシングにより分離された
各チップの側面を、絶縁材料によってコーティングする
ので、絶縁材料による側面のコーティングをもウエハ状
態で一括してでき、極めて小型かつ薄型の請求項２に記
載の発光ダイオードを一層安価に製造することができ
る。In the method of manufacturing a light-emitting diode according to the present invention, the side surface of each chip separated by the dicing is coated with an insulating material. The light emitting diode according to the second aspect of the present invention can be manufactured at a lower cost.

【図面の簡単な説明】[Brief description of the drawings]

【図１】参考例の発光ダイオードを示す斜視図である。FIG. 1 is a perspective view showing a light emitting diode of a reference example.

【図２】図１の発光ダイオードの製造方法を示す図であ
る。FIG. 2 is a view illustrating a method of manufacturing the light emitting diode of FIG. 1;

【図３】本発明の請求項１，２に記載の発光ダイオード
の実施の一形態を示す斜視図である。FIG. 3 is a perspective view showing an embodiment of the light emitting diode according to the first and second aspects of the present invention.

【図４】図３の発光ダイオードの製造方法を示す図であ
る。FIG. 4 is a view illustrating a method of manufacturing the light emitting diode of FIG. 3;

【図５】図３の発光ダイオードの種々の変形例を示す回
路図である。FIG. 5 is a circuit diagram showing various modifications of the light emitting diode of FIG. 3;

【図６】従来の発光ダイオードを示す平面図および正面
図である。FIG. 6 is a plan view and a front view showing a conventional light emitting diode.

【符号の説明】[Explanation of symbols]

１ Ｐ型層 ２ Ｎ型層 ３ Ｐ型電極部 ４ Ｎ型電極部 ５，６ はんだのコーティング層 ７ 絶縁樹脂のコーティング層 ８ 配線基板 ９ａ，９ｂ，９ｃ 配線パターン １０ 接着剤 １１，１４ ウエハ １２，１３ シート １５ レジスト層 DESCRIPTION OF SYMBOLS 1 P-type layer 2 N-type layer 3 P-type electrode part 4 N-type electrode part 5, 6 Solder coating layer 7 Insulating resin coating layer 8 Wiring board 9a, 9b, 9c Wiring pattern 10 Adhesive 11, 14 Wafer 12, 13 sheet 15 resist layer

Claims (4)

【特許請求の範囲】[Claims] 【請求項１】 配線基板の表面にボンディングワイヤを
介さずに直接実装できるチップ部品型の発光ダイオード
であって、 複数のチップが、そのチップのＰＮ接合面と平行をなす
両端面に設けられた正,負の電極部において、上記ＰＮ
接合面と直交する方向に順次導電材料またはろう材によ
って接続され、接続された一連のチップの両端の電極部
が、表面にろう材のコーティング層を有することを特徴
とするチップ部品型の発光ダイオード。1. A light emitting diode of a chip component type which can be directly mounted on a surface of a wiring board without using a bonding wire, wherein a plurality of chips are provided on both end surfaces parallel to a PN junction surface of the chip. In the positive and negative electrode portions, the PN
A chip-part-type light-emitting diode, which is sequentially connected by a conductive material or a brazing material in a direction orthogonal to the bonding surface, and the electrode portions at both ends of a series of connected chips have a brazing material coating layer on the surface. . 【請求項２】 請求項１に記載のチップ部品型の発光ダ
イオードにおいて、 上記一連のチップの両端面以外の側面の少なくとも１つ
が、表面に絶縁材料のコーティング層を有することを特
徴とするチップ部品型の発光ダイオード。2. The chip component type light emitting diode according to claim 1, wherein at least one of the side surfaces other than both end surfaces of the series of chips has a coating layer of an insulating material on the surface. Type light emitting diode. 【請求項３】 請求項１に記載のチップ部品型の発光ダ
イオードの製造方法であって、 複数枚のウエハ状態の発光ダイオードの表,裏面に設け
られた正，負の電極部を、ろう材または導電材料によっ
てコーティングした後、これらのウエハを両端面にろう
材のコーティング層が現われるように重ねて接合し、次
いで重ねて接合されたウエハを縦横にダイシングするこ
とを特徴とするチップ部品型の発光ダイオードの製造方
法。3. The method for manufacturing a light emitting diode of a chip component type according to claim 1, wherein the positive and negative electrode portions provided on the front and back surfaces of the plurality of light emitting diodes in a wafer state are brazed. Alternatively, after coating with a conductive material, these wafers are overlapped and joined so that a coating layer of a brazing material appears on both end surfaces, and then the overlapped and joined wafers are diced vertically and horizontally, which is characterized by a chip component type. A method for manufacturing a light emitting diode. 【請求項４】 請求項３に記載のチップ部品型の発光ダ
イオードの製造方法であって、 上記ダイシングにより分離された各チップの側面を、絶
縁材料によってコーティングすることを特徴とするチッ
プ部品型の発光ダイオードの製造方法。4. The method according to claim 3, wherein a side surface of each of the chips separated by dicing is coated with an insulating material. A method for manufacturing a light emitting diode.
JP34948098A 1998-12-09 1998-12-09 Manufacturing method of light emitting diode of chip component type Expired - Fee Related JP3312120B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP34948098A JP3312120B2 (en) 1998-12-09 1998-12-09 Manufacturing method of light emitting diode of chip component type

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP34948098A JP3312120B2 (en) 1998-12-09 1998-12-09 Manufacturing method of light emitting diode of chip component type

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP11277493A Division JP3022049B2 (en) 1993-05-14 1993-05-14 Mounting method of light emitting diode of chip component type

Publications (2)

Publication Number Publication Date
JPH11243230A true JPH11243230A (en) 1999-09-07
JP3312120B2 JP3312120B2 (en) 2002-08-05

Family

ID=18404038

Family Applications (1)

Application Number Title Priority Date Filing Date
JP34948098A Expired - Fee Related JP3312120B2 (en) 1998-12-09 1998-12-09 Manufacturing method of light emitting diode of chip component type

Country Status (1)

Country Link
JP (1) JP3312120B2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10228446A1 (en) * 2002-06-26 2004-01-15 Hella Kg Hueck & Co. Arrangement with electrical components
NL1029688C2 (en) * 2005-08-05 2007-02-06 Lemnis Lighting Ip Gmbh Reactive circuit for lighting device, lights-up space by loading several LEDs with full correction current
TWI420712B (en) * 2009-12-09 2013-12-21 Epistar Corp Led structure and the led package thereof

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10228446A1 (en) * 2002-06-26 2004-01-15 Hella Kg Hueck & Co. Arrangement with electrical components
NL1029688C2 (en) * 2005-08-05 2007-02-06 Lemnis Lighting Ip Gmbh Reactive circuit for lighting device, lights-up space by loading several LEDs with full correction current
WO2007052241A2 (en) * 2005-08-05 2007-05-10 Lemnis Lighting Ip Gmbh Method for preparing an electric comprising multiple leds
WO2007052241A3 (en) * 2005-08-05 2007-08-16 Lemnis Lighting Ip Gmbh Method for preparing an electric comprising multiple leds
TWI420712B (en) * 2009-12-09 2013-12-21 Epistar Corp Led structure and the led package thereof
US8680541B2 (en) 2009-12-09 2014-03-25 Epistar Corporation LED structure and the LED package thereof

Also Published As

Publication number Publication date
JP3312120B2 (en) 2002-08-05

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