JPH11186449A - Semiconductor device and its manufacture - Google Patents

Semiconductor device and its manufacture

Info

Publication number
JPH11186449A
JPH11186449A JP35680097A JP35680097A JPH11186449A JP H11186449 A JPH11186449 A JP H11186449A JP 35680097 A JP35680097 A JP 35680097A JP 35680097 A JP35680097 A JP 35680097A JP H11186449 A JPH11186449 A JP H11186449A
Authority
JP
Japan
Prior art keywords
circuit board
integrated circuit
semiconductor device
electrode portion
solder bump
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP35680097A
Other languages
Japanese (ja)
Inventor
Kazuyuki Misumi
和幸 三角
Ryuichiro Mori
隆一郎 森
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP35680097A priority Critical patent/JPH11186449A/en
Publication of JPH11186449A publication Critical patent/JPH11186449A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73215—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device having a CSP structure whose productivity is made high, whose quality is made stable, and whose reliability is made high, and a method for manufacturing this device. SOLUTION: An IC integrated circuit 1 is fixed to a circuit board 2 by using a die bond material 3, an electrode 4 on the IC integrated circuit 1 is electrically connected through a metallic wire 7 with a first electrode 5 on the circuit board 2, and first and second solder bumps 8a and 8b are provided as the outside terminal of a resin sealed semiconductor package in a semiconductor device in a CSP structure. At the time of transfer molding using a die, the first solder bump 8a is resin-sealed so as to be brought into contact with a die 12 for sealing so that the first solder bump 8a can be exposed on the surface of sealing resin 9. Then, the second solder bump 8b is joined to the exposed first solder part 8a so that the outside terminal of a semiconductor package can be formed.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】この発明は、樹脂封止型の半
導体装置に係り、特にＣＳＰ（Chip Scale Package）構
造を有する半導体装置およびその製造方法に関するもの
である。The present invention relates to a resin-sealed semiconductor device, and more particularly to a semiconductor device having a CSP (Chip Scale Package) structure and a method of manufacturing the same.

【０００２】[0002]

【従来の技術】半導体装置の高集積化に伴い、半導体パ
ッケージの外形寸法がＩＣ集積回路の寸法に近い半導体
装置の開発が進められている。ＩＣ集積回路の寸法に近
い外形寸法を有する半導体パッケージとして、一般的に
ＣＳＰと呼ばれる樹脂封止構造を有する半導体パッケー
ジが提案されている。2. Description of the Related Art With the increase in the degree of integration of semiconductor devices, the development of semiconductor devices in which the external dimensions of a semiconductor package are close to the dimensions of an IC integrated circuit has been advanced. As a semiconductor package having an outer size close to that of an IC integrated circuit, a semiconductor package having a resin sealing structure generally called a CSP has been proposed.

【０００３】[0003]

【発明が解決しようとする課題】従来のＣＳＰ構造を有
する半導体パッケージは、ポッティング法を用いて樹脂
封止されているため、生産性が低く、また品質および信
頼性においても問題があった。A conventional semiconductor package having a CSP structure is resin-encapsulated by a potting method, and therefore has low productivity and has problems in quality and reliability.

【０００４】この発明は、上記のような問題を解決する
ためになされたもので、生産性が高く、かつ品質が安定
し信頼性の高いＣＳＰ構造を有する半導体装置およびそ
の製造方法を提供することを目的とする。SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and provides a semiconductor device having a CSP structure with high productivity, stable quality, and high reliability, and a method of manufacturing the same. With the goal.

【０００５】[0005]

【課題を解決するための手段】この発明に係わる半導体
装置は、ＩＣ集積回路と、ＩＣ集積回路より小さい面積
を有する回路基板と、ＩＣ集積回路を回路基板に固着す
るダイボンド材と、ＩＣ集積回路上に形成された電極部
と回路基板上に形成された第一電極部とを電気的に接続
する導線と、回路基板上に形成され、第一電極部に電気
的に接続された第二電極部に接合された第一半田バンプ
と、各構成要素を包含し半導体パッケージを構成する封
止樹脂を備え、第一半田バンプの一部は封止樹脂の表面
に露出するよう構成されると共に、第一半田バンプの露
出部に半導体パッケージの外部端子となる第二半田バン
プが接合されるものである。また、第一半田バンプは、
樹脂封止時の封止用金型の温度より融点が高い高融点半
田により構成され、かつ第二半田バンプは共晶半田によ
って構成されるものである。また、第一半田バンプは、
半田ペースト等の半田材を積み重ねることにより形成さ
れた箔状の半田バンプからなるものである。また、半導
体パッケージには放熱板が取り付けられているものであ
る。A semiconductor device according to the present invention comprises an IC integrated circuit, a circuit board having an area smaller than the IC integrated circuit, a die bonding material for fixing the IC integrated circuit to the circuit board, and an IC integrated circuit. A conductive wire for electrically connecting the electrode portion formed thereon and the first electrode portion formed on the circuit board; and a second electrode formed on the circuit board and electrically connected to the first electrode portion. A first solder bump joined to the portion, including a sealing resin that includes each component and constitutes a semiconductor package, and a portion of the first solder bump is configured to be exposed on the surface of the sealing resin, A second solder bump serving as an external terminal of the semiconductor package is joined to an exposed portion of the first solder bump. Also, the first solder bump is
The second solder bump is made of eutectic solder, and is made of high melting point solder having a melting point higher than the temperature of the sealing mold at the time of resin sealing. Also, the first solder bump is
It consists of foil-shaped solder bumps formed by stacking solder materials such as solder paste. Further, a heat sink is attached to the semiconductor package.

【０００６】さらにこの発明に係る半導体装置の製造方
法は、ＩＣ集積回路をダイボンド材を介して回路基板に
固着する工程と、ＩＣ集積回路上に形成された電極部と
回路基板上に形成された第一電極部を電気的に接続する
工程と、回路基板上に形成され、第一電極部に電気的に
接続された第二電極部に球状の第一半田バンプを接合す
る工程と、ＩＣ集積回路をダイボンドした回路基板を封
止用金型内に配置し、第一半田バンプを封止用金型で押
圧すると共に、封止樹脂を注入してトランスファ成形し
半導体パッケージを形成する工程と、半導体パッケージ
を上記封止用金型から離型する工程を含むものである。
また、第一半田バンプを、封止用金型と接触させた状態
で封止樹脂を注入することにより、その一部を封止樹脂
の表面に露出させるようにしたものである。また、ＩＣ
集積回路とダイボンドされる回路基板は、二乃至四分割
され、各々が支持部を介して所定の枠部に固定されてい
るものである。さらに、回路基板は、一つの枠部に複数
個支持された状態でＩＣ集積回路がダイボンドされ、封
止用金型に配置されてトランスファ成形されるものであ
る。また、ダイボンド材は、テープ状に形成されたもの
を用いるものである。Further, in the method of manufacturing a semiconductor device according to the present invention, the step of fixing the IC integrated circuit to the circuit board via the die bonding material, the step of forming the electrode portion formed on the IC integrated circuit and the step formed on the circuit board are performed. A step of electrically connecting the first electrode section, a step of joining a spherical first solder bump to a second electrode section formed on the circuit board and electrically connected to the first electrode section, Placing a circuit board die-bonded circuit in a sealing mold, pressing the first solder bumps with the sealing mold, injecting a sealing resin and performing transfer molding to form a semiconductor package, The method includes a step of releasing the semiconductor package from the sealing mold.
In addition, a portion of the first solder bump is exposed on the surface of the sealing resin by injecting the sealing resin in a state of being in contact with the sealing mold. Also, IC
The circuit board to be die-bonded to the integrated circuit is divided into two to four parts, each of which is fixed to a predetermined frame part via a supporting part. Further, the circuit board is one in which a plurality of IC integrated circuits are die-bonded while being supported by one frame portion, placed in a sealing mold, and subjected to transfer molding. The die bond material used is formed in a tape shape.

【０００７】また、ＩＣ集積回路をダイボンド材を介し
て回路基板に固着する工程と、ＩＣ集積回路上に形成さ
れた電極部と回路基板上に形成された第一電極部を電気
的に接続する工程と、回路基板上に形成され、第一電極
部に電気的に接続された第二電極部に第一半田バンプを
接合する工程と、ＩＣ集積回路の回路基板とダイボンド
されていない面に放熱板を接合する工程と、ＩＣ集積回
路および放熱板を有する回路基板を封止用金型内に配置
し封止樹脂を注入してトランスファ成形し半導体パッケ
ージを形成する工程と、半導体パッケージを封止用金型
から離型し、回路基板を支持部から切り離す工程を含む
ものである。また、放熱板の端面に、斜面状あるいは階
段状の切り欠き部が形成されているものである。Further, a step of fixing the IC integrated circuit to the circuit board via a die bonding material, and electrically connecting the electrode section formed on the IC integrated circuit to the first electrode section formed on the circuit board. Bonding the first solder bump to the second electrode portion formed on the circuit board and electrically connected to the first electrode portion; and radiating heat to the surface of the IC integrated circuit that is not die-bonded to the circuit board. Bonding a board, arranging a circuit board having an IC integrated circuit and a heat sink in a sealing mold, injecting a sealing resin and performing transfer molding to form a semiconductor package, and sealing the semiconductor package. The method includes a step of releasing the circuit board from the support mold and separating the circuit board from the supporting portion. In addition, an inclined surface or a stepped notch is formed on the end surface of the heat sink.

【０００８】[0008]

【発明の実施の形態】実施の形態１．以下、この発明の
一実施の形態である半導体装置およびその製造方法を図
について説明する。図１〜図４はこの発明の実施の形態
１を示す図で、図１は実施の形態１による半導体装置の
断面図、図２は実施の形態１による半導体装置を示す斜
視図で、一部内部構造を示している。図３は実施の形態
１による半導体装置に用いられる回路基板の形状例を示
す平面図、図４は実施の形態１による半導体装置の製造
方法を説明するための断面図である。図において、１は
ＩＣ集積回路、２は回路基板、３はＩＣ集積回路１を回
路基板２に取り付けるペースト状のダイボンド材、４は
ＩＣ集積回路１上に形成された電極部、５、６は回路基
板２上に形成された第一電極部と第二電極部で、第一電
極部５と第二電極部６は配線を介して電気的に接続され
ている。７はＩＣ集積回路１上に形成された電極部４と
回路基板２上に形成された第一電極部５を電気的に接続
する金線、８ａ、８ｂは半導体パッケージの外部端子と
なる第一半田バンプと第二半田バンプで、第一半田バン
プ８ａは回路基板２上の第二電極部６と接合し、第二半
田バンプ８ｂは第一半田バンプ８ａに接合される。９は
ＩＣ集積回路１および回路基板２を包含し半導体パッケ
ージを形成する封止樹脂、１０は回路基板２を枠（図持
せず）に支持する支持部、１１は第一半田バンプ８ａを
構成する半田ボール、１２は上下一対の封止用金型であ
る。DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 Hereinafter, a semiconductor device according to an embodiment of the present invention and a method for manufacturing the same will be described with reference to the drawings. 1 to 4 show a first embodiment of the present invention. FIG. 1 is a sectional view of a semiconductor device according to the first embodiment. FIG. 2 is a perspective view showing the semiconductor device according to the first embodiment. 2 shows the internal structure. FIG. 3 is a plan view showing an example of the shape of a circuit board used in the semiconductor device according to the first embodiment, and FIG. 4 is a cross-sectional view for explaining a method of manufacturing the semiconductor device according to the first embodiment. In the drawing, reference numeral 1 denotes an IC integrated circuit, 2 denotes a circuit board, 3 denotes a paste die bonding material for attaching the IC integrated circuit 1 to the circuit board 2, 4 denotes an electrode portion formed on the IC integrated circuit 1, and 5 and 6 denote electrodes. In the first electrode portion and the second electrode portion formed on the circuit board 2, the first electrode portion 5 and the second electrode portion 6 are electrically connected via wiring. Reference numeral 7 denotes a gold wire for electrically connecting the electrode portion 4 formed on the IC integrated circuit 1 and the first electrode portion 5 formed on the circuit board 2, and 8a and 8b denote first terminals serving as external terminals of the semiconductor package. The first solder bump 8a is joined to the second electrode portion 6 on the circuit board 2 and the second solder bump 8b is joined to the first solder bump 8a. Reference numeral 9 denotes a sealing resin that includes the IC integrated circuit 1 and the circuit board 2 to form a semiconductor package, 10 denotes a support that supports the circuit board 2 on a frame (not shown), and 11 denotes a first solder bump 8a. The solder balls 12 are a pair of upper and lower sealing dies.

【０００９】次に、製造工程について説明する。まず図
３に示すように、トランスファーが容易なように二分割
もしくは四分割され、そのコーナー部もしくは辺部を延
長して形成された支持部１０により枠に支持された状態
の回路基板２に、ダイボンド材３を用いてＩＣ集積回路
１を固着し、ＩＣ集積回路１上に形成された電極部４と
回路基板２上に形成された第一電極部５を金線７により
電気的に接続する。次に、回路基板２上に形成された第
二電極部６に半田ボール１１を接合する。次に図４
（ａ）に示すように、ＩＣ集積回路１とダイボンドさ
れ、半田ボール１１を搭載した回路基板２を封止用金型
１２内に配置する。次に図４（ｂ）に示すように、上下
一対の封止用金型１２を閉じて回路基板２を封止用金型
１２で挟み込む。このとき、半田ボール１１は封止用金
型１２と接触し、半田ボール１１は封止用金型１２に押
しつぶされた状態（第一半田バンプ８ａ）となる。次に
図４（ｃ）に示すように、封止金型１２内に封止樹脂７
を充填し、トランスファ成形する。このとき、第一半田
バンプ８ａは封止用金型１２と密着した状態にあるた
め、第一半田バンプ８ａと封止用金型１２の間には封止
樹脂９は介在しない。次に封止用金型１２を開放し（図
４（ｄ））、その後枠から回路基板２を切り離す（図４
（ｅ））。次に図４（ｆ）に示すように、封止樹脂９の
表面に露出している第一半田バンプ８ａ上に第二半田バ
ンプ（半田ボール）８ｂを接合し、半導体パッケージの
外部端子を形成する。Next, the manufacturing process will be described. First, as shown in FIG. 3, the circuit board 2 is divided into two or four parts so that the transfer is easy, and the circuit board 2 is supported by a frame by a support part 10 formed by extending the corners or sides. The IC integrated circuit 1 is fixed using the die bonding material 3, and the electrode portion 4 formed on the IC integrated circuit 1 and the first electrode portion 5 formed on the circuit board 2 are electrically connected by the gold wire 7. . Next, the solder balls 11 are joined to the second electrode portions 6 formed on the circuit board 2. Next, FIG.
As shown in FIG. 1A, a circuit board 2 die-bonded to an IC integrated circuit 1 and having a solder ball 11 mounted thereon is disposed in a sealing mold 12. Next, as shown in FIG. 4B, the pair of upper and lower sealing molds 12 is closed, and the circuit board 2 is sandwiched between the sealing molds 12. At this time, the solder ball 11 comes into contact with the sealing mold 12, and the solder ball 11 is crushed by the sealing mold 12 (first solder bump 8a). Next, as shown in FIG.
And transfer molding. At this time, since the first solder bump 8a is in close contact with the sealing mold 12, the sealing resin 9 is not interposed between the first solder bump 8a and the sealing mold 12. Next, the sealing mold 12 is opened (FIG. 4D), and then the circuit board 2 is separated from the frame (FIG. 4D).
(E)). Next, as shown in FIG. 4F, the second solder bumps (solder balls) 8b are joined to the first solder bumps 8a exposed on the surface of the sealing resin 9, thereby forming external terminals of the semiconductor package. I do.

【００１０】なお、封止用金型１２により押しつぶされ
る半田ボール１１（第一半田バンプ８ａ）を構成する半
田は、融点が低く急激に軟化する共晶半田では、封止用
金型１２に付着したり、外形を保持できず封止樹脂９の
表面に露出する電極を構成できないため、樹脂封止時の
封止用金型１２の温度より少なくとも２０゜Ｃ以上融点
が高い高融点接合材料（Ｓｎ９５％、Ａｇ５％含有、融
点２２０゜Ｃ）を用いる。また、第二半田バンプ８ｂを
構成する半田は、ＣＳＰの特徴であるセルフアライメン
トを確実に行えるようにするため、共晶半田を用いる。
また、半田ボール１１の代わりにスクリーン印刷、ある
いはスパッタ等により半田材を積み上げることにより形
成された箔状の半田バンプを用いてもよい。ただし、箔
状の半田バンプは、トランスファ成形時に半田材が封止
用金型１２と密着する厚みを有することが必要である。The solder forming the solder balls 11 (first solder bumps 8a) crushed by the sealing mold 12 adheres to the sealing mold 12 with eutectic solder having a low melting point and rapidly softening. Or an electrode exposed on the surface of the sealing resin 9 cannot be formed because the outer shape cannot be maintained, so that a high melting point bonding material (at least 20 ° C. or higher than the temperature of the sealing mold 12 at the time of resin sealing) is used. (Sn: 95%, Ag: 5%, melting point: 220 ° C) is used. Eutectic solder is used as the solder constituting the second solder bump 8b in order to ensure the self-alignment characteristic of the CSP.
Further, instead of the solder balls 11, foil-shaped solder bumps formed by stacking solder materials by screen printing, sputtering or the like may be used. However, it is necessary that the foil-shaped solder bumps have a thickness such that the solder material is in close contact with the sealing mold 12 during transfer molding.

【００１１】この発明によれば、半導体装置の封止をト
ランスファ成形とすることにより品質が安定し、信頼性
の高いＣＳＰ構造を有する半導体装置を得ることができ
る。また、現在は各社各様である半導体パッケージの実
装用パッド（回路基板の外部電極）の配列が規格化さ
れ、共通化されれば、ＩＣ集積回路が小型化された場合
でも半導体パッケージの外形が変わらないため、同じ封
止用金型を用いて半導体パッケージを製造することがで
きる。また、封止用金型１２により半田ボール１１を押
しつぶすことにより、封止用金型１２に第一半田バンプ
８ａが密着した状態で樹脂封止を行うため、封止樹脂９
の表面に外部との接続用の電極部を容易に露出させるこ
とができ、製造工程を簡略化できる。According to the present invention, a semiconductor device having a stable CSP structure with stable quality can be obtained by transfer molding the semiconductor device. In addition, the arrangement of mounting pads (external electrodes of a circuit board) of a semiconductor package, which are now various companies, is standardized and standardized, and if the IC integrated circuit is miniaturized, the external shape of the semiconductor package is reduced. Since there is no change, a semiconductor package can be manufactured using the same sealing mold. In addition, since the solder ball 11 is crushed by the sealing mold 12 to perform resin sealing in a state where the first solder bump 8 a is in close contact with the sealing mold 12, the sealing resin 9 is formed.
The electrode portion for connection to the outside can be easily exposed on the surface of the device, and the manufacturing process can be simplified.

【００１２】実施の形態２．図５はこの発明の実施の形
態２を示す半導体装置に用いられる回路基板形成時の状
態の平面図である。図において、２は回路基板、１３は
複数の回路基板２を支持部１０を介して支持する枠部で
ある。本実施の形態では、図５に示すように、複数個の
回路基板２がそのコーナー部もしくは辺部から延長され
た支持部１０を介して枠部１３に支持されている。枠部
１３に支持された状態の回路基板２に、実施の形態１と
同様にダイボンド材を用いてＩＣ集積回路を固着し、Ｉ
Ｃ集積回路上の電極部と回路基板上の電極部を金線によ
り電気的に接続すると共に半導体パッケージの外部端子
となる部分に半田ボールを配置した後、枠部１３に支持
された状態で回路基板２を封止用金型内に配置し、トラ
ンスファ成形を行い半導体パッケージを形成する。本実
施の形態によれば、複数個の回路基板２が枠部１３に支
持された状態で同時にトランスファ成形を行うため、製
造工数を削減でき、生産性の向上および製造コストの低
減を図ることができる。Embodiment 2 FIG. FIG. 5 is a plan view showing a state when a circuit board used in the semiconductor device according to the second embodiment of the present invention is formed. In the drawing, reference numeral 2 denotes a circuit board, and 13 denotes a frame portion that supports a plurality of circuit boards 2 via a support portion 10. In the present embodiment, as shown in FIG. 5, a plurality of circuit boards 2 are supported by a frame 13 via a support 10 extending from a corner or a side thereof. An IC integrated circuit is fixed to the circuit board 2 supported by the frame portion 13 using a die bonding material in the same manner as in the first embodiment.
The electrode portion on the C integrated circuit is electrically connected to the electrode portion on the circuit board by a gold wire, and the solder ball is arranged on a portion to be an external terminal of the semiconductor package. The substrate 2 is placed in a sealing mold, and transfer molding is performed to form a semiconductor package. According to the present embodiment, the transfer molding is performed simultaneously while the plurality of circuit boards 2 are supported by the frame portion 13, so that the number of manufacturing steps can be reduced, the productivity can be improved, and the manufacturing cost can be reduced. it can.

【００１３】実施の形態３．実施の形態１では、ＩＣ集
積回路１と回路基板２の固着にはペースト状のダイボン
ド材３を用いたが、テープ状のダイボンド材を用いるこ
とにより、作業性の向上、ダイボンド材の厚みの均一
化、取付安定性の向上を図ることができ、半導体装置の
品質および信頼性向上において一層の効果が得られる。Embodiment 3 In the first embodiment, the paste-type die bonding material 3 is used for fixing the IC integrated circuit 1 and the circuit board 2. However, by using a tape-shaped die bonding material, the workability is improved and the thickness of the die bonding material is uniform. And the stability of mounting can be improved, and a further effect can be obtained in improving the quality and reliability of the semiconductor device.

【００１４】実施の形態４．図６はこの発明の実施の形
態４を示す半導体装置の断面図である。図において、１
４ａ、１４ｂは放熱板で、図６（ａ）および図６（ｂ）
は、フィンのない放熱板１４ａとフィンを有する放熱板
１４ｂを取り付けた例を示している。なお、その他の構
成は図１に示す実施の形態１と同様であるので説明を省
略する。放熱板１４ａもしくは１４ｂを、樹脂封止後に
封止樹脂９が介在しないＩＣ集積回路１の裏面側（回路
基板２とダイボンドされていない面）に接合する。本実
施の形態によれば、ＩＣ集積回路１からの発熱を放熱板
１４ａもしくは１４ｂを介して効率よく外部に放熱でき
るため、ＩＣ集積回路１の長寿命化および信頼性の高い
半導体装置を提供することができる。Embodiment 4 FIG. 6 is a sectional view of a semiconductor device according to a fourth embodiment of the present invention. In the figure, 1
Reference numerals 4a and 14b denote heat sinks, which are shown in FIGS. 6 (a) and 6 (b).
Shows an example in which a radiator plate 14a having no fins and a radiator plate 14b having fins are attached. The other configuration is the same as that of the first embodiment shown in FIG. The heat radiating plate 14a or 14b is bonded to the back surface of the IC integrated circuit 1 where the sealing resin 9 does not intervene after resin sealing (the surface not die-bonded to the circuit board 2). According to the present embodiment, since heat generated from the IC integrated circuit 1 can be efficiently radiated to the outside via the heat radiating plate 14a or 14b, a semiconductor device having a long life and high reliability of the IC integrated circuit 1 is provided. be able to.

【００１５】実施の形態５．実施の形態４では、ＩＣ集
積回路１と回路基板２を樹脂封止した後に放熱板１４ａ
を取り付けたが、図７に示すように、放熱板１４をＩＣ
集積回路１の裏面側に接合した後に樹脂封止を行っても
よい。図７は実施の形態５による半導体装置の製造方法
を説明するための断面図である。図において、１４は放
熱板、１５は放熱板１４をＩＣ集積回路１に接合する接
合材料である。なお、その他の構成は図４に示す実施の
形態１と同様であるので説明を省略する。Embodiment 5 In the fourth embodiment, after the IC integrated circuit 1 and the circuit board 2 are resin-sealed,
However, as shown in FIG.
After joining to the back surface side of the integrated circuit 1, resin sealing may be performed. FIG. 7 is a cross-sectional view for illustrating the method for manufacturing the semiconductor device according to the fifth embodiment. In the figure, reference numeral 14 denotes a radiator plate, and 15 denotes a bonding material for bonding the radiator plate 14 to the IC integrated circuit 1. The other configuration is the same as that of the first embodiment shown in FIG.

【００１６】本実施の形態による半導体装置の製造方法
は、まず図７（ａ）に示すように、半田ボール１１を搭
載した回路基板２とダイボンドされたＩＣ集積回路１の
裏面側（回路基板２とダイボンドされていない面）に放
熱板１４を接合する。このとき、ＩＣ集積回路１の裏面
側にメタライズを施すことにより、半田等の接合材料１
５を用いて容易に放熱板１４をＩＣ集積回路１に接合さ
せることができる。次に図７（ｂ）に示すように、放熱
板１４が接合されたＩＣ集積回路１をダイボンドした回
路基板２を封止用金型１２内に配置する。以降は実施の
形態１と同様の方法により半導体装置を形成する（図７
（ｃ））。また、図８（ａ）および図８（ｂ）は、ＩＣ
集積回路１に接合された放熱板１４の構造を示す断面図
で、図８（ａ）に示すように放熱板１４の端面に斜め形
状の切り欠き部１６、あるいは図８（ｂ）に示すように
放熱板１４の端面に階段状の切り欠き部１６を設けるこ
とにより、樹脂封止工程において封止樹脂９が放熱板１
４の切り欠き部１６に回り込み、実装工程時等に放熱板
１４が離脱するのを防止することができる。本実施の形
態によれば、半導体装置への放熱板１４の取り付けを簡
略化することができると共に、放熱板１４の離脱を防止
することができる。In the method of manufacturing a semiconductor device according to the present embodiment, first, as shown in FIG. 7A, the back side of the IC integrated circuit 1 die-bonded to the circuit board 2 on which the solder balls 11 are mounted (the circuit board 2). The heat radiating plate 14 is bonded to the surface not die-bonded. At this time, by applying metallization to the back surface side of the IC integrated circuit 1, the bonding material 1 such as solder is formed.
5, the heat sink 14 can be easily joined to the IC integrated circuit 1. Next, as shown in FIG. 7B, the circuit board 2 on which the IC integrated circuit 1 to which the heat sink 14 has been bonded is die-bonded is placed in the sealing mold 12. Thereafter, a semiconductor device is formed by the same method as in the first embodiment (FIG. 7).
(C)). FIGS. 8A and 8B show an IC.
FIG. 8 is a cross-sectional view showing the structure of the heat radiating plate 14 joined to the integrated circuit 1. As shown in FIG. 8A, the end face of the heat radiating plate 14 has an oblique cutout 16 or as shown in FIG. By providing a stepped notch 16 on the end face of the heat sink 14, the sealing resin 9 is
4 to prevent the heat sink 14 from coming off during the mounting process and the like. According to the present embodiment, it is possible to simplify the attachment of the heat sink 14 to the semiconductor device and to prevent the heat sink 14 from being detached.

【００１７】[0017]

【発明の効果】以上のように、この発明によれば、半導
体装置の封止をトランスファ成形とすることにより品質
が安定し、信頼性の高い半導体装置を得ることができ
る。また、封止用金型で半田ボールを押しつぶすことに
より、封止用金型に半田バンプが密着した状態で樹脂封
止を行うため、封止樹脂の表面に外部との接続用の電極
部を容易に露出させることができ、製造工程を簡略化で
きる。また、請求項４に係る発明によれば、ＩＣ集積回
路からの発熱を放熱板を介して効率よく外部に放熱でき
るため、ＩＣ集積回路の長寿命化および信頼性の高い半
導体装置を提供することができる。また、請求項７およ
び８に係る発明によれば、回路基板は二乃至四分割され
ていると共に、複数個の回路基板が支持部を介して枠部
に支持された状態で同時にトランスファ成形を行うた
め、製造工数を削減でき、生産性の向上および製造コス
トの低減を図ることができる。また、請求項９に係る発
明によれば、ＩＣ集積回路と回路基板の固着にテープ状
のダイボンド材を用いることにより、作業性の向上、ダ
イボンド材の厚みの均一化、取付安定性の向上を図るこ
とができ、半導体装置の品質および信頼性向上において
一層の効果が得られる。また、請求項１０および１１に
係る発明によれば、半導体装置への放熱板の取り付けを
簡略化することができると共に、放熱板の離脱を防止す
ることができる。As described above, according to the present invention, a semiconductor device having stable quality and high reliability can be obtained by encapsulating a semiconductor device by transfer molding. Also, by crushing the solder ball with the sealing mold, the resin sealing is performed in a state where the solder bumps are in close contact with the sealing mold. It can be easily exposed, and the manufacturing process can be simplified. According to the fourth aspect of the present invention, heat generated from the IC integrated circuit can be efficiently radiated to the outside via the heat radiating plate, so that a semiconductor device having a long life and high reliability of the IC integrated circuit is provided. Can be. According to the seventh and eighth aspects of the present invention, the circuit board is divided into two or four parts, and the transfer molding is performed simultaneously in a state where the plurality of circuit boards are supported by the frame part via the support part. Therefore, the number of manufacturing steps can be reduced, and productivity can be improved and manufacturing cost can be reduced. According to the ninth aspect of the present invention, by using a tape-shaped die bonding material for fixing the IC integrated circuit to the circuit board, workability can be improved, the thickness of the die bonding material can be made uniform, and the mounting stability can be improved. As a result, a further effect can be obtained in improving the quality and reliability of the semiconductor device. According to the tenth and eleventh aspects of the present invention, it is possible to simplify the attachment of the heat sink to the semiconductor device and prevent the heat sink from being detached.

【図面の簡単な説明】[Brief description of the drawings]

【図１】 この発明の実施の形態１による半導体装置を
示す断面図である。FIG. 1 is a sectional view showing a semiconductor device according to a first embodiment of the present invention;

【図２】 この発明の実施の形態１による半導体装置を
示す斜視図である。FIG. 2 is a perspective view showing the semiconductor device according to the first embodiment of the present invention;

【図３】 この発明の実施の形態１による半導体装置の
回路基板を示す平面図である。FIG. 3 is a plan view showing a circuit board of the semiconductor device according to the first embodiment of the present invention;

【図４】 この発明の実施の形態１による半導体装置の
製造工程を示す断面図である。FIG. 4 is a sectional view illustrating a manufacturing step of the semiconductor device according to the first embodiment of the present invention;

【図５】 この発明の実施の形態２による半導体装置の
回路基板を示す平面図である。FIG. 5 is a plan view showing a circuit board of a semiconductor device according to a second embodiment of the present invention.

【図６】 この発明の実施の形態４による半導体装置を
示す断面図である。FIG. 6 is a sectional view showing a semiconductor device according to a fourth embodiment of the present invention.

【図７】 この発明の実施の形態５による半導体装置の
製造工程を示す断面図である。FIG. 7 is a sectional view illustrating a manufacturing step of a semiconductor device according to a fifth embodiment of the present invention;

【図８】 この発明の実施の形態５による半導体装置の
放熱板の形状を示す断面図である。FIG. 8 is a sectional view showing a shape of a heat sink of a semiconductor device according to a fifth embodiment of the present invention.

【符号の説明】[Explanation of symbols]

１ ＩＣ集積回路、２ 回路基板、３ ダイボンド材、
４ 電極部、５ 第一電極部、６ 第二電極部、７ 金
線、８ａ、第一半田バンプ、８ｂ 第二半田バンプ、９
封止樹脂、１０ 支持部、１１ 半田ボール、１２
封止用金型、１３ 枠部、１４、１４ａ、１４ｂ 放熱
板、１５ 接合材料、１６ 切り欠き部。1 IC integrated circuit, 2 circuit board, 3 die bonding material,
4 electrode part, 5 first electrode part, 6 second electrode part, 7 gold wire, 8a, first solder bump, 8b second solder bump, 9
Sealing resin, 10 support, 11 solder balls, 12
Sealing mold, 13 frame, 14, 14a, 14b heat sink, 15 bonding material, 16 cutout.

Claims (11)

【特許請求の範囲】[Claims] 【請求項１】 ＩＣ集積回路と、 上記ＩＣ集積回路より小さい面積を有する回路基板と、 上記ＩＣ集積回路を上記回路基板に固着するダイボンド
材と、 上記ＩＣ集積回路上に形成された電極部と上記回路基板
上に形成された第一電極部とを電気的に接続する導線
と、 上記回路基板上に形成され、上記第一電極部に電気的に
接続された第二電極部に接合された第一半田バンプと、 上記各構成要素を包含し半導体パッケージを構成する封
止樹脂を備え、 上記第一半田バンプの一部は上記封止樹脂の表面に露出
するよう構成されると共に、上記第一半田バンプの露出
部に上記半導体パッケージの外部端子となる第二半田バ
ンプが接合されることを特徴とする半導体装置。An IC integrated circuit; a circuit board having an area smaller than the IC integrated circuit; a die bonding material for fixing the IC integrated circuit to the circuit board; and an electrode portion formed on the IC integrated circuit. A conductive wire that electrically connects the first electrode portion formed on the circuit board, and a second electrode portion formed on the circuit board and electrically connected to the first electrode portion; A first solder bump, comprising a sealing resin that includes the above components and forms a semiconductor package, and a part of the first solder bump is configured to be exposed on a surface of the sealing resin; A semiconductor device, wherein a second solder bump serving as an external terminal of the semiconductor package is joined to an exposed portion of the one solder bump. 【請求項２】 第一半田バンプは、樹脂封止時の封止用
金型の温度より融点が高い高融点半田により構成され、
かつ第二半田バンプは共晶半田によって構成されること
を特徴とする請求項１記載の半導体装置。2. The first solder bump is made of a high melting point solder having a melting point higher than a temperature of a sealing mold at the time of resin sealing,
2. The semiconductor device according to claim 1, wherein the second solder bump is made of eutectic solder. 【請求項３】 第一半田バンプは、半田ペースト等の半
田材を積み重ねることにより形成された箔状の半田バン
プからなることを特徴とする請求項１または請求項２記
載の半導体装置。3. The semiconductor device according to claim 1, wherein the first solder bump comprises a foil-like solder bump formed by stacking solder materials such as solder paste. 【請求項４】 半導体パッケージには放熱板が取り付け
られていることを特徴とする請求項１〜３のいずれか一
項記載の半導体装置。4. The semiconductor device according to claim 1, wherein a heat sink is attached to the semiconductor package. 【請求項５】 ＩＣ集積回路をダイボンド材を介して回
路基板に固着する工程と、 上記ＩＣ集積回路上に形成された電極部と上記回路基板
上に形成された第一電極部を電気的に接続する工程と、 上記回路基板上に形成され、上記第一電極部に電気的に
接続された第二電極部に球状の第一半田バンプを接合す
る工程と、 上記ＩＣ集積回路をダイボンドした回路基板を封止用金
型内に配置し、上記第一半田バンプを封止用金型で押圧
すると共に、封止樹脂を注入してトランスファ成形し半
導体パッケージを形成する工程と、 上記半導体パッケージを上記封止用金型から離型する工
程を含むことを特徴とする半導体装置の製造方法。5. A step of fixing an IC integrated circuit to a circuit board via a die bonding material, and electrically connecting an electrode portion formed on the IC integrated circuit and a first electrode portion formed on the circuit board. Connecting, bonding a spherical first solder bump to a second electrode portion formed on the circuit board and electrically connected to the first electrode portion, and a circuit die-bonded to the IC integrated circuit. Disposing a substrate in a sealing mold, pressing the first solder bumps with the sealing mold, injecting a sealing resin and performing transfer molding to form a semiconductor package; and A method for manufacturing a semiconductor device, comprising a step of releasing the mold from the sealing mold. 【請求項６】 第一半田バンプを、封止用金型と接触さ
せた状態で封止樹脂を注入することにより、その一部を
上記封止樹脂の表面に露出させるようにしたことを特徴
とする請求項５記載の半導体装置の製造方法。6. The method according to claim 1, wherein a portion of the first solder bump is exposed on the surface of the sealing resin by injecting the sealing resin in a state of being in contact with the sealing mold. 6. The method for manufacturing a semiconductor device according to claim 5, wherein 【請求項７】 ＩＣ集積回路とダイボンドされる回路基
板は、二乃至四分割され、各々が支持部を介して所定の
枠部に固定されることを特徴とする請求項５または請求
項６記載の半導体装置の製造方法。7. The circuit board die-bonded to the IC integrated circuit is divided into two or four parts, each of which is fixed to a predetermined frame part via a support part. Of manufacturing a semiconductor device. 【請求項８】 回路基板は、一つの枠部に複数個支持さ
れた状態でＩＣ集積回路がダイボンドされ、封止用金型
に配置されてトランスファ成形されることを特徴とする
請求項５〜７のいずれか一項記載の半導体装置の製造方
法。8. A circuit board, wherein a plurality of IC integrated circuits are die-bonded in a state of being supported by one frame portion, placed in a sealing mold, and subjected to transfer molding. 8. The method for manufacturing a semiconductor device according to claim 7. 【請求項９】 ダイボンド材は、テープ状に形成された
ものを用いることを特徴とする請求項５〜８のいずれか
一項記載の半導体装置の製造方法。9. The method for manufacturing a semiconductor device according to claim 5, wherein the die bonding material is formed in a tape shape. 【請求項１０】 ＩＣ集積回路をダイボンド材を介して
回路基板に固着する工程と、 上記ＩＣ集積回路上に形成された電極部と上記回路基板
上に形成された第一電極部を電気的に接続する工程と、 上記回路基板上に形成され、上記第一電極部に電気的に
接続された第二電極部に第一半田バンプを接合する工程
と、 上記ＩＣ集積回路の上記回路基板とダイボンドされてい
ない面に放熱板を接合する工程と、 上記ＩＣ集積回路および放熱板を有する回路基板を封止
用金型内に配置し封止樹脂を注入してトランスファ成形
し半導体パッケージを形成する工程と、 上記半導体パッケージを上記封止用金型から離型し、上
記回路基板を支持部から切り離す工程を含むことを特徴
とする半導体装置の製造方法。10. A step of fixing an IC integrated circuit to a circuit board via a die bonding material, and electrically connecting an electrode portion formed on the IC integrated circuit and a first electrode portion formed on the circuit board. Connecting; bonding a first solder bump to a second electrode portion formed on the circuit board and electrically connected to the first electrode portion; and die bonding with the circuit board of the IC integrated circuit. Bonding a heat sink to a surface that is not formed, and placing a circuit board having the IC integrated circuit and the heat sink in a sealing mold, injecting a sealing resin and performing transfer molding to form a semiconductor package. And a step of releasing the semiconductor package from the sealing mold and separating the circuit board from a supporting portion. 【請求項１１】 放熱板の端面に、斜面状あるいは階段
状の切り欠き部が形成されていることを特徴とする請求
項１０記載の半導体装置の製造方法。11. The method for manufacturing a semiconductor device according to claim 10, wherein an inclined surface or a step-shaped notch is formed at an end surface of the heat sink.
JP35680097A 1997-12-25 1997-12-25 Semiconductor device and its manufacture Pending JPH11186449A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP35680097A JPH11186449A (en) 1997-12-25 1997-12-25 Semiconductor device and its manufacture

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP35680097A JPH11186449A (en) 1997-12-25 1997-12-25 Semiconductor device and its manufacture

Publications (1)

Publication Number Publication Date
JPH11186449A true JPH11186449A (en) 1999-07-09

Family

ID=18450843

Family Applications (1)

Application Number Title Priority Date Filing Date
JP35680097A Pending JPH11186449A (en) 1997-12-25 1997-12-25 Semiconductor device and its manufacture

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Country Link
JP (1) JPH11186449A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1205973A1 (en) * 2000-11-10 2002-05-15 United Test Center Inc. Low-profile semiconductor device and method for manufacturing the same
US6525412B2 (en) 2000-11-30 2003-02-25 Kabushiki Kaisha Toshiba Semiconductor device having chip scale package
JP2005150748A (en) * 2003-11-18 2005-06-09 Samsung Electronics Co Ltd Semiconductor chip package having decoupling capacitor and method for manufacturing same
JP2008283187A (en) * 2007-05-09 2008-11-20 Samsung Electronics Co Ltd Printed circuit board, and semiconductor package having it
US7642635B2 (en) 2003-02-28 2010-01-05 Elpida Memory, Inc. Stacked semiconductor package
TWI683401B (en) * 2017-11-15 2020-01-21 台灣積體電路製造股份有限公司 Semiconductor structure and method of forming the same

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1205973A1 (en) * 2000-11-10 2002-05-15 United Test Center Inc. Low-profile semiconductor device and method for manufacturing the same
US6525412B2 (en) 2000-11-30 2003-02-25 Kabushiki Kaisha Toshiba Semiconductor device having chip scale package
US6656766B2 (en) 2000-11-30 2003-12-02 Kabushiki Kaisha Toshiba Semiconductor device having chip scale package
US7642635B2 (en) 2003-02-28 2010-01-05 Elpida Memory, Inc. Stacked semiconductor package
JP2005150748A (en) * 2003-11-18 2005-06-09 Samsung Electronics Co Ltd Semiconductor chip package having decoupling capacitor and method for manufacturing same
JP4606849B2 (en) * 2003-11-18 2011-01-05 三星電子株式会社 Semiconductor chip package having decoupling capacitor and manufacturing method thereof
JP2008283187A (en) * 2007-05-09 2008-11-20 Samsung Electronics Co Ltd Printed circuit board, and semiconductor package having it
KR101336572B1 (en) * 2007-05-09 2013-12-03 삼성전자주식회사 Semiconductor package
TWI683401B (en) * 2017-11-15 2020-01-21 台灣積體電路製造股份有限公司 Semiconductor structure and method of forming the same

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