JPH1116949A - Acf-bonding structure - Google Patents
Acf-bonding structureInfo
- Publication number
- JPH1116949A JPH1116949A JP9169826A JP16982697A JPH1116949A JP H1116949 A JPH1116949 A JP H1116949A JP 9169826 A JP9169826 A JP 9169826A JP 16982697 A JP16982697 A JP 16982697A JP H1116949 A JPH1116949 A JP H1116949A
- Authority
- JP
- Japan
- Prior art keywords
- acf
- electrode
- conductive particles
- bonding
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
- H01L2224/83101—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus as prepeg comprising a layer connector, e.g. provided in an insulating plate member
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/321—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by conductive adhesives
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3452—Solder masks
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、ガラスや樹脂等の
基板に半導体パッケージや半導体チップなどの電子部品
を異方導電性フィルムを用いて接合するＡＣＦ接合構造
に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an ACF bonding structure for bonding an electronic component such as a semiconductor package or a semiconductor chip to a substrate such as glass or resin using an anisotropic conductive film.
【０００２】[0002]
【従来の技術】異方導電性フィルム（以下、「ＡＣＦ」
と記す）は、金属コートプラスチック粒子や金属粒子を
熱硬化性樹脂等の樹脂に分散した接着フィルムであり、
その異方導電性及び接着性を利用して、電子部品と基板
の電気的接続に広く利用されている。以下、従来のＡＣ
Ｆ接合方式について説明する。2. Description of the Related Art An anisotropic conductive film (hereinafter, "ACF")
Is an adhesive film in which metal-coated plastic particles or metal particles are dispersed in a resin such as a thermosetting resin,
Utilizing its anisotropic conductivity and adhesiveness, it is widely used for electrical connection between electronic components and substrates. Hereinafter, the conventional AC
The F joining method will be described.
【０００３】図３は従来のプリント配線基板に半導体部
品をＡＣＦを用いて接合する前の状態を示す断面図であ
り、図４は同ＡＣＦの硬化メカニズム図である。FIG. 3 is a sectional view showing a state before a semiconductor component is joined to a conventional printed wiring board using an ACF, and FIG. 4 is a curing mechanism diagram of the ACF.
【０００４】図３において、１は半導体部品、２はバン
プ、３はパッド、４はプリント配線基板、５は電極、６
はＡＣＦ、７は導電粒子である。In FIG. 3, 1 is a semiconductor component, 2 is a bump, 3 is a pad, 4 is a printed wiring board, 5 is an electrode, 6
Is an ACF, and 7 is a conductive particle.
【０００５】従来の半導体部品１をプリント配線基板４
にＡＣＦ６を用いて接合する方法として、まずプリント
配線基板４とＡＣＦ６を熱をかけながら仮圧着する。次
にこの仮圧着したプリント配線基板４とＡＣＦ６に半導
体部品１を熱を加えずに仮圧着する。最後に圧着用の治
具を用いて熱をかけながら本圧着を行う。このとき、加
熱・加圧によってＡＣＦ６中のエポキシ樹脂及び接着剤
が溶融しながらバンプ２と電極５の間から流れ出し（図
４（ａ），（ｂ），（ｃ））、分散されている導電粒子
７がバンプ２と電極５の電極間に捕獲される（図４
（ｄ））。A conventional semiconductor component 1 is connected to a printed wiring board 4
As a method of joining using the ACF 6, first, the printed wiring board 4 and the ACF 6 are temporarily press-bonded while applying heat. Next, the semiconductor component 1 is pre-bonded to the pre-pressed printed wiring board 4 and the ACF 6 without applying heat. Finally, the main bonding is performed while applying heat using a jig for crimping. At this time, the epoxy resin and the adhesive in the ACF 6 flow out from between the bumps 2 and the electrodes 5 while being melted by heating and pressing (FIGS. 4A, 4B, and 4C), and the dispersed conductive material. Particles 7 are trapped between the bump 2 and the electrode 5 (FIG. 4).
(D)).
【０００６】ここで、ＡＣＦ６における導電粒子７の充
填量と導電率の関係からＡＣＦ６の導電粒子７充填量に
対する導電率の依存性には異方性がある。すなわち、フ
ィルム膜厚方向で高い導電性を示す一方、面内方向では
導電粒子７が互いに孤立しているため、高い絶縁性を示
す。導電粒子７とバンプ２・電極５の間の機械的接触
は、ＡＣＦ６内のエポキシ樹脂の硬化収縮力と接着剤の
高い接着力により保持されている。このようにＡＣＦ６
を用いることにより、半導体部品１とプリント配線基板
４の電気的及び機械的接合を行っている。Here, from the relationship between the filling amount of the conductive particles 7 in the ACF 6 and the electric conductivity, the dependency of the electric conductivity on the filling amount of the conductive particles 7 in the ACF 6 is anisotropic. That is, the conductive particles 7 exhibit high conductivity in the film thickness direction, while exhibiting high insulation properties in the in-plane direction because the conductive particles 7 are isolated from each other. The mechanical contact between the conductive particles 7 and the bumps 2 and the electrodes 5 is maintained by the curing shrinkage force of the epoxy resin in the ACF 6 and the high adhesive force of the adhesive. Thus, ACF6
Is used to electrically and mechanically join the semiconductor component 1 and the printed wiring board 4.
【０００７】[0007]
【発明が解決しようとする課題】しかしながら上記従来
方法では、高接続密度化・小型化・薄型化が要求されて
いる半導体実装分野において、接続ピッチの細密化が進
んだ場合、バンプやパターンの寸法も小さくなり導電粒
子の捕獲数は少なくなる。その結果、接続信頼性や電気
的特性の低下が考えられる。However, in the above-mentioned conventional method, in the field of semiconductor mounting where high connection density, miniaturization and thinning are required, when the connection pitch becomes finer, dimensions of bumps and patterns are increased. And the number of captured conductive particles decreases. As a result, the connection reliability and the electrical characteristics may be reduced.
【０００８】したがって本発明は、ＡＣＦを用いた電子
部品のファインピッチ実装において、電子部品と基板の
接合信頼性を確保できるとともに、電気的特性の低下を
防止できるＡＣＦ接合構造を提供することを目的とす
る。SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide an ACF bonding structure that can secure the bonding reliability between an electronic component and a substrate and prevent a decrease in electrical characteristics in fine pitch mounting of electronic components using an ACF. And
【０００９】[0009]
【課題を解決するための手段】本発明は、電子部品と基
板を導電粒子を含む異方導電性フィルムを用い、前記導
電粒子を前記電子部品と前記基板の電極の間に介在させ
ることにより電気的な接合を行うにあたり、前記基板上
に形成された電極近傍に前記電極の厚みよりも厚い絶縁
部材を設けることにより前記電極を凹部とし、前記電子
部品と前記基板の接合時におけるＡＣＦの溶融による導
電粒子の流れを抑制して、前記電子部品と前記基板との
接合時における前記凹部の導電粒子数を増大させるよう
にした。この構成により、ＡＣＦを用いたファインピッ
チ接合においても、電子部品と基板の接合信頼性および
電気的特性が十分に確保されたＡＣＦ接合構造を実現で
きる。According to the present invention, an electronic component and a substrate are formed by using an anisotropic conductive film containing conductive particles, and the conductive particles are interposed between the electronic component and an electrode of the substrate. In performing a typical joining, by providing an insulating member thicker than the thickness of the electrode in the vicinity of the electrode formed on the substrate, the electrode is formed into a concave portion, and the ACF is melted at the time of joining the electronic component and the substrate. The flow of the conductive particles is suppressed, and the number of the conductive particles in the recess at the time of joining the electronic component and the substrate is increased. With this configuration, even in the fine pitch bonding using the ACF, it is possible to realize the ACF bonding structure in which the bonding reliability and the electrical characteristics of the electronic component and the substrate are sufficiently ensured.
【００１０】[0010]
【発明の実施の形態】請求項１に記載の発明は、電子部
品と基板を導電粒子を含む異方導電性フィルムを用い、
前記導電粒子を前記電子部品と前記基板の電極の間に介
在させることにより電気的な接合を行うにあたり、前記
基板上に形成された電極近傍に前記電極の厚みよりも厚
い絶縁部材を設けることにより前記電極周辺を凹部と
し、前記電子部品と前記基板の接合時ＡＣＦの溶融によ
る導電粒子の流れを抑制し前記電子部品と前記基板との
接合時における前記凹部の導電粒子数を増大させる。こ
の構成により、ファインピッチ実装においても電気的接
合に関与する導電粒子の捕獲数を確保し、接合信頼性お
よび電気的特性を十分に確保できる。The invention according to claim 1 uses an anisotropic conductive film containing conductive particles for an electronic component and a substrate.
In performing electrical bonding by interposing the conductive particles between the electronic component and the electrode of the substrate, by providing an insulating member thicker than the thickness of the electrode near the electrode formed on the substrate. A concave portion is formed around the electrode to suppress the flow of conductive particles due to melting of the ACF at the time of joining the electronic component and the substrate, thereby increasing the number of conductive particles in the concave portion at the time of joining the electronic component and the substrate. With this configuration, even in fine pitch mounting, the number of captured conductive particles involved in electrical bonding can be ensured, and bonding reliability and electrical characteristics can be sufficiently ensured.
【００１１】請求項２に記載の発明は、前記電極に前記
絶縁部材の一部もしくは全部が重なるように設けること
により、前記凹部の深さを深くした。この構成により、
ファインピッチ実装においても電気的接合に関与する導
電粒子の捕獲数を確保し、接合信頼性および電気的特性
を十分に確保できる。In the invention according to claim 2, the depth of the concave portion is increased by providing the electrode so that a part or the whole of the insulating member overlaps. With this configuration,
Even in fine pitch mounting, the number of captured conductive particles involved in electrical bonding can be ensured, and bonding reliability and electrical characteristics can be sufficiently ensured.
【００１２】（実施の形態１）図１は、本発明の実施の
形態１のＡＣＦを用いて半導体部品をプリント配線基板
に実装した状態の断面図である。図１において、１は半
導体部品、２はバンプ、３はパッド、４はプリント配線
基板、５は電極、６はＡＣＦ、７は導電粒子、８はレジ
ストを示す。(Embodiment 1) FIG. 1 is a sectional view showing a state in which a semiconductor component is mounted on a printed wiring board using an ACF according to Embodiment 1 of the present invention. In FIG. 1, reference numeral 1 denotes a semiconductor component, 2 denotes a bump, 3 denotes a pad, 4 denotes a printed wiring board, 5 denotes an electrode, 6 denotes an ACF, 7 denotes conductive particles, and 8 denotes a resist.
【００１３】図１に示すように、半導体部品１のパッド
３上にボンディングされたバンプ２が接合するプリント
配線基板４上のパターンの電極５に開口部を持った絶縁
部材であるレジスト８を印刷法や写真法等により設け
る。このとき、通常レジスト８の高さは２３〜２５μ
ｍ、電極５の高さは１８μｍであり、レジスト８のほう
が電極５より５〜７μｍ高く、したがって電極５は凹部
となっており、レジスト８をバンプ２と電極５の間から
流れ出る導電粒子７のストッパーとする。つまり、半導
体部品１の本圧着時における加熱・加圧による導電粒子
７の流れ出しをレジスト８で妨げることにより、導電粒
子７がバンプ２と電極５の間の凹部から流れ出ることを
抑制し、電気的接合に関与する導電粒子７の捕獲数を確
保する。As shown in FIG. 1, a resist 8 which is an insulating member having an opening is printed on an electrode 5 of a pattern on a printed wiring board 4 to which a bump 2 bonded to a pad 3 of a semiconductor component 1 is joined. It is provided by a method or a photographic method. At this time, the height of the resist 8 is usually 23 to 25 μm.
m, the height of the electrode 5 is 18 μm, and the height of the resist 8 is 5 to 7 μm higher than that of the electrode 5. Therefore, the electrode 5 is a concave portion, and the resist 8 is formed of the conductive particles 7 flowing out from between the bump 2 and the electrode 5. Stopper. That is, the resist 8 prevents the conductive particles 7 from flowing out due to heating and pressurization during the final press-fitting of the semiconductor component 1, thereby suppressing the conductive particles 7 from flowing out of the concave portion between the bump 2 and the electrode 5, thereby providing an electrical connection. The number of captured conductive particles 7 involved in bonding is ensured.
【００１４】このように、バンプ２と電極５の間の電気
的接合に関与する導電粒子７の捕獲数を確保すること
で、ファインピッチ実装によりバンプ２や電極５の寸法
が小さくなっても、接合信頼性及び電気的特性を低下さ
せることのないＡＣＦ６を用いた半導体部品１とプリン
ト配線基板４の接合が実現できる。As described above, by ensuring the number of captured conductive particles 7 involved in the electrical connection between the bump 2 and the electrode 5, even if the dimensions of the bump 2 and the electrode 5 are reduced by the fine pitch mounting, The joining of the semiconductor component 1 and the printed wiring board 4 using the ACF 6 without lowering the joining reliability and the electrical characteristics can be realized.
【００１５】（実施の形態２）図２は、本発明の実施の
形態２のＡＣＦを用いて半導体部品をプリント配線基板
に実装した状態の断面図である。図２に示すように、半
導体部品１のパッド３上にボンディングされたバンプ２
が接合するプリント配線基板４上の電極５に開口部を持
ったレジスト８を印刷法や写真法等により設ける。ここ
で、レジスト８の開口部寸法を電極５の寸法より小さく
し、電極５とレジスト８を重ねることで、電極の高さ１
８μｍをキャンセルすることができ、従ってレジスト８
の高さそのものが凹部の深さ２３〜２５μｍとなり、よ
り深い凹部が電極５上に形成される。したがってこのレ
ジスト８による壁をバンプ２と電極５の間から流れ出る
導電粒子７のストッパーとする。つまり、半導体部品１
本圧着時におけるの加熱・加圧による導電粒子７の流れ
出しを妨げることにより、導電粒子７がバンプ２と電極
５の間から流れ出ることを抑制し、電気的接合に関与す
る導電粒子７の捕獲数を十分確保する。(Embodiment 2) FIG. 2 is a sectional view showing a state in which a semiconductor component is mounted on a printed wiring board using an ACF according to Embodiment 2 of the present invention. As shown in FIG. 2, the bump 2 bonded on the pad 3 of the semiconductor component 1
Is provided with a resist 8 having an opening in the electrode 5 on the printed wiring board 4 to be joined by a printing method or a photographic method. Here, the size of the opening of the resist 8 is made smaller than the size of the electrode 5, and the electrode 5 and the resist 8 are overlapped, so that the electrode height 1
8 μm can be cancelled, and therefore resist 8
The height of the recess itself is 23 to 25 μm, and a deeper recess is formed on the electrode 5. Therefore, the wall of the resist 8 serves as a stopper for the conductive particles 7 flowing out from between the bump 2 and the electrode 5. That is, the semiconductor component 1
By preventing the conductive particles 7 from flowing out due to heating and pressurization during the final press bonding, the conductive particles 7 are prevented from flowing out between the bumps 2 and the electrodes 5, and the number of captured conductive particles 7 involved in electrical bonding To secure enough.
【００１６】このように、バンプ２と電極５の間の電気
的接合に関与する導電粒子７の捕獲数を確保すること
で、ファインピッチ実装によりバンプ２や電極５の寸法
が小さくなっても、接合信頼性及び電気的特性を低下さ
せることのないＡＣＦ６を用いた半導体部品１とプリン
ト配線基板４の接合が実現できる。As described above, by ensuring the number of captured conductive particles 7 involved in the electrical connection between the bump 2 and the electrode 5, even if the dimensions of the bump 2 and the electrode 5 are reduced by the fine pitch mounting, The joining of the semiconductor component 1 and the printed wiring board 4 using the ACF 6 without lowering the joining reliability and the electrical characteristics can be realized.
【００１７】[0017]
【発明の効果】以上のように本発明によれば、ＡＣＦ溶
融時にバンプと電極の間から流れ出る導電粒子を抑制
し、電気的接合に関与する導電粒子数を確保することに
より、接合信頼性及び電気的特性を十分に確保できる。As described above, according to the present invention, it is possible to suppress the conductive particles flowing out between the bump and the electrode when the ACF is melted, and to secure the number of the conductive particles involved in the electrical bonding, thereby improving the reliability of the bonding. Sufficient electrical characteristics can be secured.
【図１】本発明の実施の形態１のＡＣＦを用いて半導体
部品をプリント配線基板に実装した状態の断面図FIG. 1 is a cross-sectional view of a state in which a semiconductor component is mounted on a printed wiring board using an ACF according to Embodiment 1 of the present invention.
【図２】本発明の実施の形態２のＡＣＦを用いて半導体
部品をプリント配線基板に実装した状態の断面図FIG. 2 is a cross-sectional view showing a state where a semiconductor component is mounted on a printed wiring board using the ACF according to the second embodiment of the present invention;
【図３】従来のプリント配線基板に半導体部品をＡＣＦ
を用いて接合する前の状態を示す断面図FIG. 3 shows a conventional printed circuit board in which a semiconductor component is ACF.
Sectional view showing the state before joining using
【図４】従来のＡＣＦの硬化メカニズム図FIG. 4 is a diagram showing a curing mechanism of a conventional ACF.
１ 半導体部品 ２ バンプ ３ パッド ４ プリント配線基板 ５ 電極 ６ ＡＣＦ ７ 導電粒子 ８ レジスト DESCRIPTION OF SYMBOLS 1 Semiconductor component 2 Bump 3 Pad 4 Printed wiring board 5 Electrode 6 ACF 7 Conductive particle 8 Resist
Claims (2)
性フィルムを用い、前記導電粒子を前記電子部品と前記
基板の電極の間に介在させることにより電気的な接合を
行うにあたり、前記基板上に形成された電極近傍に前記
電極の厚みよりも厚い絶縁部材を設けることにより前記
電極を凹部とし、前記電子部品と前記基板の接合時にお
けるＡＣＦの溶融による導電粒子の流れを抑制して、前
記電子部品と前記基板との接合時における前記凹部の導
電粒子数を増大させることを特徴とするＡＣＦ接合構
造。An electronic component and a substrate are formed by using an anisotropic conductive film containing conductive particles, and the conductive particles are interposed between electrodes of the electronic component and the substrate to perform electrical bonding. By providing an insulating member thicker than the thickness of the electrode in the vicinity of the electrode formed on the substrate, the electrode is formed as a concave portion, and the flow of conductive particles due to melting of ACF at the time of joining the electronic component and the substrate is suppressed. An ACF joining structure, wherein the number of conductive particles in the concave portion at the time of joining the electronic component and the substrate is increased.
部が重なるように設けることにより、前記凹部の深さを
深くしたことを特徴とする請求項１記載のＡＣＦ接合構
造。2. The ACF bonding structure according to claim 1, wherein a depth of the concave portion is increased by providing the insulating member so as to partially or entirely overlap the electrode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16982697A JP3725300B2 (en) | 1997-06-26 | 1997-06-26 | ACF junction structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16982697A JP3725300B2 (en) | 1997-06-26 | 1997-06-26 | ACF junction structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH1116949A true JPH1116949A (en) | 1999-01-22 |
| JP3725300B2 JP3725300B2 (en) | 2005-12-07 |
Family
ID=15893631
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16982697A Expired - Fee Related JP3725300B2 (en) | 1997-06-26 | 1997-06-26 | ACF junction structure |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3725300B2 (en) |
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6409866B1 (en) | 1999-05-28 | 2002-06-25 | Sony Chemicals Corp. | Process for mounting semiconductor device |
| US6769469B2 (en) * | 1999-08-09 | 2004-08-03 | Sony Chemicals Corp. | Process for mounting semiconductor device and mounting apparatus |
| JP2006298954A (en) * | 2005-04-15 | 2006-11-02 | Tatsuta System Electronics Kk | Electroconductive adhesive sheet and circuit board |
| US20090174073A1 (en) * | 2008-01-08 | 2009-07-09 | Woong Sun Lee | Substrate for semiconductor package having coating film and method for manufacturing the same |
| US20120153443A1 (en) * | 2006-11-22 | 2012-06-21 | Tessera, Inc. | Packaged semiconductor chips with array |
| US8405196B2 (en) | 2007-03-05 | 2013-03-26 | DigitalOptics Corporation Europe Limited | Chips having rear contacts connected by through vias to front contacts |
| US8847380B2 (en) | 2010-09-17 | 2014-09-30 | Tessera, Inc. | Staged via formation from both sides of chip |
| US9099296B2 (en) | 2010-12-02 | 2015-08-04 | Tessera, Inc. | Stacked microelectronic assembly with TSVS formed in stages with plural active chips |
| US9224649B2 (en) | 2010-12-08 | 2015-12-29 | Tessera, Inc. | Compliant interconnects in wafers |
| US9269692B2 (en) | 2010-12-02 | 2016-02-23 | Tessera, Inc. | Stacked microelectronic assembly with TSVS formed in stages and carrier above chip |
| US9355948B2 (en) | 2010-09-17 | 2016-05-31 | Tessera, Inc. | Multi-function and shielded 3D interconnects |
| US9640437B2 (en) | 2010-07-23 | 2017-05-02 | Tessera, Inc. | Methods of forming semiconductor elements using micro-abrasive particle stream |
-
1997
- 1997-06-26 JP JP16982697A patent/JP3725300B2/en not_active Expired - Fee Related
Cited By (22)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6409866B1 (en) | 1999-05-28 | 2002-06-25 | Sony Chemicals Corp. | Process for mounting semiconductor device |
| US6769469B2 (en) * | 1999-08-09 | 2004-08-03 | Sony Chemicals Corp. | Process for mounting semiconductor device and mounting apparatus |
| KR100616792B1 (en) * | 1999-08-09 | 2006-08-29 | 소니 케미카루 가부시키가이샤 | Apparatus and method for mounting semiconductor element |
| JP2006298954A (en) * | 2005-04-15 | 2006-11-02 | Tatsuta System Electronics Kk | Electroconductive adhesive sheet and circuit board |
| US9070678B2 (en) | 2006-11-22 | 2015-06-30 | Tessera, Inc. | Packaged semiconductor chips with array |
| US9548254B2 (en) | 2006-11-22 | 2017-01-17 | Tessera, Inc. | Packaged semiconductor chips with array |
| US8569876B2 (en) | 2006-11-22 | 2013-10-29 | Tessera, Inc. | Packaged semiconductor chips with array |
| US8653644B2 (en) * | 2006-11-22 | 2014-02-18 | Tessera, Inc. | Packaged semiconductor chips with array |
| US20120153443A1 (en) * | 2006-11-22 | 2012-06-21 | Tessera, Inc. | Packaged semiconductor chips with array |
| US8405196B2 (en) | 2007-03-05 | 2013-03-26 | DigitalOptics Corporation Europe Limited | Chips having rear contacts connected by through vias to front contacts |
| US20090174073A1 (en) * | 2008-01-08 | 2009-07-09 | Woong Sun Lee | Substrate for semiconductor package having coating film and method for manufacturing the same |
| US9640437B2 (en) | 2010-07-23 | 2017-05-02 | Tessera, Inc. | Methods of forming semiconductor elements using micro-abrasive particle stream |
| US8847380B2 (en) | 2010-09-17 | 2014-09-30 | Tessera, Inc. | Staged via formation from both sides of chip |
| US9355948B2 (en) | 2010-09-17 | 2016-05-31 | Tessera, Inc. | Multi-function and shielded 3D interconnects |
| US9362203B2 (en) | 2010-09-17 | 2016-06-07 | Tessera, Inc. | Staged via formation from both sides of chip |
| US9847277B2 (en) | 2010-09-17 | 2017-12-19 | Tessera, Inc. | Staged via formation from both sides of chip |
| US10354942B2 (en) | 2010-09-17 | 2019-07-16 | Tessera, Inc. | Staged via formation from both sides of chip |
| US9269692B2 (en) | 2010-12-02 | 2016-02-23 | Tessera, Inc. | Stacked microelectronic assembly with TSVS formed in stages and carrier above chip |
| US9368476B2 (en) | 2010-12-02 | 2016-06-14 | Tessera, Inc. | Stacked microelectronic assembly with TSVs formed in stages with plural active chips |
| US9620437B2 (en) | 2010-12-02 | 2017-04-11 | Tessera, Inc. | Stacked microelectronic assembly with TSVS formed in stages and carrier above chip |
| US9099296B2 (en) | 2010-12-02 | 2015-08-04 | Tessera, Inc. | Stacked microelectronic assembly with TSVS formed in stages with plural active chips |
| US9224649B2 (en) | 2010-12-08 | 2015-12-29 | Tessera, Inc. | Compliant interconnects in wafers |
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