JP3383774B2 - Semiconductor element mounting method - Google Patents
Semiconductor element mounting methodInfo
- Publication number
- JP3383774B2 JP3383774B2 JP30366998A JP30366998A JP3383774B2 JP 3383774 B2 JP3383774 B2 JP 3383774B2 JP 30366998 A JP30366998 A JP 30366998A JP 30366998 A JP30366998 A JP 30366998A JP 3383774 B2 JP3383774 B2 JP 3383774B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- anisotropic conductive
- bump
- circuit board
- condition
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/27—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/27—Manufacturing methods
- H01L2224/274—Manufacturing methods by blanket deposition of the material of the layer connector
- H01L2224/2743—Manufacturing methods by blanket deposition of the material of the layer connector in solid form
- H01L2224/27436—Lamination of a preform, e.g. foil, sheet or layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Wire Bonding (AREA)
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、電子回路用プリン
ト基板に半導体素子を実装する半導体素子の実装方法に
関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor element mounting method for mounting a semiconductor element on a printed circuit board for electronic circuits.
【０００２】[0002]
【従来の技術】今日、電子回路基板は、あらゆる製品に
使用されるようになりかつ、携帯機器の増加から、ＩＣ
チップをパッケージでなく、裸のまま回路基板に搭載す
るフリップチップ実装方法が求められている。2. Description of the Related Art Today, electronic circuit boards have come to be used in all products and due to the increase in portable devices, IC
There is a demand for a flip-chip mounting method in which a chip is mounted on a circuit board as it is without being packaged.
【０００３】従来の電子機器の回路基板へＩＣチップを
接合する方法について、以下に説明する。A conventional method of joining an IC chip to a circuit board of an electronic device will be described below.
【０００４】図５（ａ）、（ｂ）に示される特公昭６２
−６６５２号公報記載の方法のように、異方性導電シー
ト６を回路基板４に貼り付け、半導体素子１を圧着ヘッ
ド１０で熱圧着することによって、バンプ３と回路基板
電極５間の接合を行うことが従来知られている。なお、
２は半導体素子１側の電極、７は剥離テープである。Japanese Patent Publication No. Sho 62 shown in FIGS. 5 (a) and 5 (b).
As in the method described in Japanese Patent No. 6652, the anisotropic conductive sheet 6 is attached to the circuit board 4, and the semiconductor element 1 is thermocompression bonded by the pressure bonding head 10 to bond the bumps 3 to the circuit board electrodes 5. It is conventionally known to do. In addition,
Reference numeral 2 is an electrode on the semiconductor element 1 side, and 7 is a peeling tape.
【０００５】その際図５（ｃ）のグラフに示されるよう
に、温度Ｔを１８０℃で圧力Ｐを７５ｇｆ／バンプに設
定した圧着ヘッド１０で２０ｓｅｃの間熱圧着してい
る。At this time, as shown in the graph of FIG. 5 (c), thermocompression bonding is performed for 20 seconds by the pressure bonding head 10 in which the temperature T is 180 ° C. and the pressure P is 75 gf / bump.
【０００６】又、図６（ａ）、（ｂ）に示される半導体
実装方法のように、異方性導電ペースト１５を使用する
ものであって、絶縁樹脂中に導電性粒子を加えて構成す
る異方性導電ペースト１５を回路基板４に塗布し、半導
体素子１を圧着ヘッド１０で熱圧着することによって、
バンプ３と回路基板４の電極５間の接合を行うことが従
来知られている。なお、２は半導体素子１側の電極であ
る。Further, as in the semiconductor mounting method shown in FIGS. 6A and 6B, an anisotropic conductive paste 15 is used, which is constructed by adding conductive particles to an insulating resin. By applying the anisotropic conductive paste 15 to the circuit board 4 and thermocompression-bonding the semiconductor element 1 with the pressure-bonding head 10,
It is conventionally known to bond the bumps 3 to the electrodes 5 of the circuit board 4. Reference numeral 2 is an electrode on the semiconductor element 1 side.
【０００７】その際図６（ｃ）のグラフに示されるよう
に、温度Ｔを１８０℃で圧力Ｐを７５ｇｆ／バンプに設
定した圧着ヘッド１０で２０ｓｅｃの間熱圧着してい
る。At this time, as shown in the graph of FIG. 6 (c), thermocompression bonding is performed for 20 seconds by the pressure bonding head 10 in which the temperature T is 180 ° C. and the pressure P is 75 gf / bump.
【０００８】[0008]
【発明が解決しようとする課題】このように、電気製品
の小型化を実現するために、従来の技術に示したフリッ
プチップ実装が提案され、実用化されているが、以下の
ような問題点を生じている。As described above, in order to realize the miniaturization of electric products, the flip chip mounting shown in the prior art has been proposed and put into practical use, but the following problems are encountered. Is occurring.
【０００９】第一点は、半導体素子１の載置時に加熱と
加圧を同時に行い、バンプ３と回路基板上電極５の電気
的接続と、基板４と半導体素子１間の封止樹脂（異方性
導電シート６、異方性導電ペースト１５）の硬化を同時
に行うために、図５（ｅ）、図６（ｅ）に示すように樹
脂の方向的に自由な硬化収縮１８に逆らって荷重１７が
加えられるため、樹脂硬化後に内部歪みを生じかつ、十
分な硬化を阻害し硬化率が上がらなくなる。このため、
接合信頼性を劣化させてしまっている。The first point is that the semiconductor element 1 is heated and pressed at the same time when it is mounted, the bumps 3 and the electrodes 5 on the circuit board are electrically connected, and the sealing resin between the substrate 4 and the semiconductor element 1 is different. In order to simultaneously cure the anisotropic conductive sheet 6 and the anisotropic conductive paste 15), the load is applied against the directionally free curing shrinkage 18 of the resin as shown in FIGS. 5 (e) and 6 (e). Since 17 is added, internal strain occurs after the resin is cured, and sufficient curing is hindered so that the curing rate cannot be increased. For this reason,
The joint reliability is deteriorated.
【００１０】第二点は、半導体素子１の載置時に加熱と
加圧を同時に行い、バンプ３と回路基板上電極５の電気
的接続と、基板４と半導体素子１間の封止樹脂の硬化を
同時に行うために、図５（ｄ）、図６（ｄ）に示すよう
にバンプ３、半導体素子１を介して加熱温度と加圧が回
路基板４にかかり、加熱が基板樹脂の軟化、加圧で基板
電極５を変形１６させてしまうことである。このよう
な、電極変形が発生した場合、多層基板の場合、回路基
板４の表層と内層の二層間の絶縁性を損なう恐れがあ
る。また、電極自身の破損による導電性を損なう恐れが
ある。さらに、微細配線を可能にしているビルドアップ
基板においては、通常のガラスエポキシ基板に比べ、表
層の絶縁層にはガラス繊維を含まず、また、表層配線が
微細なことにより電極５の変形が大きくなる。The second point is that the semiconductor element 1 is heated and pressed at the same time when it is mounted, the bumps 3 are electrically connected to the electrodes 5 on the circuit board, and the sealing resin between the substrate 4 and the semiconductor element 1 is cured. 5D and 6D, heating temperature and pressure are applied to the circuit board 4 via the bumps 3 and the semiconductor element 1 to heat and soften the board resin. That is, the substrate electrode 5 is deformed 16 by the pressure. When such electrode deformation occurs, in the case of a multi-layer substrate, there is a risk of impairing the insulation between the two layers of the surface layer and the inner layer of the circuit board 4. Further, there is a possibility that the electrode itself may be damaged and the conductivity may be impaired. Further, in the build-up substrate that enables fine wiring, the surface insulating layer does not contain glass fiber and the electrode 5 is largely deformed because the surface layer wiring is fine as compared with a normal glass epoxy substrate. Become.
【００１１】本発明は、上記従来の問題点に鑑みて、回
路基板上の電極の変形を抑制しかつ、高い接合信頼性を
得る半導体素子の実装方法を提供することを目的とす
る。In view of the above-mentioned conventional problems, it is an object of the present invention to provide a semiconductor element mounting method that suppresses the deformation of electrodes on a circuit board and obtains high junction reliability.
【００１２】[0012]
【課題を解決するための手段】本発明は、上記目的を達
成するために、以下のように構成している。In order to achieve the above object, the present invention is configured as follows.
【００１３】本願の第一発明は、熱硬化性の異方性導電
シートを回路基板に貼り付け、半導体素子のバンプと前
記回路基板上の電極を異方性導電シートを介して接する
ように載置し、半導体素子からの加熱、加圧で異方性導
電シートを硬化して、半導体素子を圧着し、前記バンプ
と前記電極とを接合する半導体素子の実装方法におい
て、半導体素子の圧着工程を、第一段階条件は、加熱温
度が１６０〜２４０℃かつ、加圧条件が５０〜１００ｇ
／バンプ、第二段階条件は、加熱温度が１６０〜２４０
℃かつ、加圧条件が５０ｇ／バンプ以下、の二段階工程
で行うことを特徴とする。In the first invention of the present application, a thermosetting anisotropic conductive sheet is attached to a circuit board, and the bumps of the semiconductor element and the electrodes on the circuit board are mounted so as to be in contact with each other via the anisotropic conductive sheet. In the mounting method of the semiconductor element, the anisotropic conductive sheet is cured by heating and pressure from the semiconductor element, the semiconductor element is pressure-bonded, and the bump and the electrode are bonded. The first stage condition is that the heating temperature is 160 to 240 ° C. and the pressurizing condition is 50 to 100 g.
/ Bump, the second stage conditions, the heating temperature is 160 ~ 240
It is characterized in that it is carried out in a two-step process in which the temperature is 50 ° C. and the pressure is 50 g / bump or less.
【００１４】本願の第二発明は、熱硬化性の異方性導電
シートを回路基板に貼り付け、半導体素子のバンプと前
記回路基板上の電極を異方性導電シートを介して接する
ように載置し、半導体素子からの加熱、加圧で異方性導
電シートを硬化して、半導体素子を圧着し、前記バンプ
と前記電極とを接合する半導体素子の実装方法におい
て、半導体素子の圧着工程を、第一段階条件は、加熱温
度が異方性導電シートの軟化温度以上で基板のガラス転
移温度未満かつ、加圧条件が５０〜１００ｇ／バンプ、
第二段階条件は、加熱条件が基板のガラス転移温度以上
で２４０℃以下かつ、加圧条件が５０ｇ／バンプ以下、
の二段階工程で行うことを特徴とする。In the second invention of the present application, a thermosetting anisotropic conductive sheet is attached to a circuit board, and the bumps of the semiconductor element and the electrodes on the circuit board are mounted so as to be in contact with each other via the anisotropic conductive sheet. In the mounting method of the semiconductor element, the anisotropic conductive sheet is cured by heating and pressure from the semiconductor element, the semiconductor element is pressure-bonded, and the bump and the electrode are bonded. The first stage condition is that the heating temperature is equal to or higher than the softening temperature of the anisotropic conductive sheet and lower than the glass transition temperature of the substrate, and the pressure condition is 50 to 100 g / bump.
The second stage condition is that the heating condition is not less than the glass transition temperature of the substrate and not more than 240 ° C. and the pressing condition is not more than 50 g / bump,
It is characterized in that it is carried out in a two-step process.
【００１５】本願の第三発明は、熱硬化性の異方性導電
ペーストを回路基板に塗布し、半導体素子のバンプと前
記回路基板上の電極を異方性導電ペーストを介して接す
るように載置し、半導体素子からの加熱、加圧で異方性
導電ペーストを硬化して、半導体素子を圧着し、前記バ
ンプと前記電極とを接合する半導体素子の実装方法にお
いて、半導体素子の圧着工程を、第一段階条件は、加熱
温度が１６０〜２４０℃かつ、加圧条件が５０〜１００
ｇ／バンプ、第二段階条件は、加熱温度が１６０〜２４
０℃かつ、加圧条件が５０ｇ／バンプ以下、の二段階工
程で行うことを特徴とする。According to a third aspect of the present invention, a thermosetting anisotropic conductive paste is applied to a circuit board, and the bumps of the semiconductor element and the electrodes on the circuit board are placed in contact with each other via the anisotropic conductive paste. In the method for mounting a semiconductor element, the anisotropic conductive paste is cured by heating and pressure from the semiconductor element, the semiconductor element is pressure-bonded, and the bump and the electrode are bonded together. The first stage condition is that the heating temperature is 160 to 240 ° C. and the pressurizing condition is 50 to 100.
g / bump, the second stage condition is that the heating temperature is 160 to 24
It is characterized in that it is performed in a two-step process of 0 ° C. and a pressure condition of 50 g / bump or less.
【００１６】本願の第四発明は、熱硬化性の異方性導電
ペーストを回路基板に塗布し、半導体素子のバンプと前
記回路基板上の電極を異方性導電ペーストを介して接す
るように載置し、半導体素子からの加熱、加圧で異方性
導電ペーストを硬化して、半導体素子を圧着し、前記バ
ンプと前記電極とを接合する半導体素子の実装方法にお
いて、半導体素子の圧着工程を、第一段階条件は、加熱
温度が異方性導電ペーストの軟化温度以上で基板のガラ
ス転移温度未満かつ、加圧条件が５０〜１００ｇ／バン
プ、第二段階条件は、加熱温度が基板のガラス転移温度
以上で２４０℃以下かつ、加圧条件は５０ｇ／バンプ以
下、の二段階条件で行うことを特徴とする。According to a fourth aspect of the present invention, a thermosetting anisotropic conductive paste is applied to a circuit board, and the bumps of the semiconductor element and the electrodes on the circuit board are placed in contact with each other through the anisotropic conductive paste. In the method for mounting a semiconductor element, the anisotropic conductive paste is cured by heating and pressure from the semiconductor element, the semiconductor element is pressure-bonded, and the bump and the electrode are bonded together. The first stage condition is that the heating temperature is equal to or higher than the softening temperature of the anisotropic conductive paste and lower than the glass transition temperature of the substrate, and the pressurizing condition is 50 to 100 g / bump, and the second stage condition is that the heating temperature is the glass of the substrate. It is characterized in that it is carried out under the two-stage conditions of a transition temperature or higher and 240 ° C. or lower and a pressurization condition of 50 g / bump or lower.
【００１７】上記第一発明及び、第三発明によれば、半
導体素子上バンプと基板電極とを電気的に接触させ、封
止目的の樹脂を半硬化させた後に、圧着荷重を低荷重に
して、自由に封止樹脂を硬化させるため、樹脂中の内部
歪みを減少させることができる。According to the first and third inventions, the bumps on the semiconductor element and the substrate electrodes are electrically contacted with each other, and the resin for sealing is semi-cured, and then the pressure-bonding load is reduced. Since the sealing resin is freely cured, internal strain in the resin can be reduced.
【００１８】上記第二発明及び、第四発明によれば、基
板ガラス転移温度未満で半導体素子上バンプと基板電極
の電気的接触した後に、圧着荷重を低荷重にして、樹脂
を硬化させるため、基板電極変形を抑制することができ
る。According to the above-mentioned second and fourth inventions, after the electrical contact between the bumps on the semiconductor element and the substrate electrodes at a temperature lower than the substrate glass transition temperature, the pressure bonding load is reduced to cure the resin, The substrate electrode deformation can be suppressed.
【００１９】[0019]
【発明の実施の形態】つぎに、本発明の実施形態を図面
を参照しながら説明する。DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the present invention will be described with reference to the drawings.
【００２０】本発明の第一実施形態にかかる回路基板４
への半導体素子１の実装方法を図１（ａ）〜（ｅ）を用
いて説明する。Circuit board 4 according to the first embodiment of the present invention
A method for mounting the semiconductor element 1 on the semiconductor device 1 will be described with reference to FIGS.
【００２１】図１（ａ）において、半導体素子１のＡｌ
パッド（半導体素子側電極）２上に直径２５μｍのＡｕ
線を用いて、ワイヤボンディング装置によりバンプ３を
形成した。In FIG. 1A, the Al of the semiconductor element 1 is
Au having a diameter of 25 μm is formed on the pad (semiconductor element side electrode) 2.
The wire 3 was used to form the bump 3 by a wire bonding apparatus.
【００２２】図１（ｂ）において、ガラスエポキシ基板
４（ＮＥＣ製、ＦＲ−４）上に、厚み８０μｍの異方性
導電シート６（ソニーケミカル製、ＭＪ−９３２）を半
導体素子１実装領域に置き、温度８０℃、荷重１．５ｋ
ｇｆ／ｃｍ2に設定した貼付ヘッド８で貼り付けた。In FIG. 1B, an anisotropic conductive sheet 6 (manufactured by NEC Chemical, MJ-932) having a thickness of 80 μm is mounted on a glass epoxy substrate 4 (manufactured by NEC, FR-4) in a semiconductor element 1 mounting region. Place, temperature 80 ℃, load 1.5k
The application was performed with the application head 8 set to gf / cm 2 .
【００２３】図１（ｃ）において、異方性導電シート６
上のセパレーター７と呼ばれるフィルムを剥がした。In FIG. 1C, the anisotropic conductive sheet 6 is used.
The film called Separator 7 above was peeled off.
【００２４】図１（ｄ）において、基板４上の基板電極
５と半導体素子１に形成したバンプ３が接するように位
置合わせして半導体素子マウントヘッド９により載置し
た。In FIG. 1D, the substrate electrodes 5 on the substrate 4 and the bumps 3 formed on the semiconductor element 1 are aligned so as to be in contact with each other and mounted by the semiconductor element mount head 9.
【００２５】図１（ｅ）において、温度条件を異方性導
電シート６の硬化温度である１８０℃に設定した圧着ヘ
ッド１０で、第一段階の圧力１１としての７５ｇｆ／バ
ンプで１０ｓｅｃ間荷重を加え、異方性導電シート６が
６０〜８０％硬化した後、ひき続き同一温度、同一の圧
着ヘッド１０で第二段階の圧力１２として３０ｇｆ／バ
ンプで１０ｓｅｃ間荷重を加え、異方性導電シート６を
９０％以上硬化させた。In FIG. 1 (e), with the pressure bonding head 10 in which the temperature condition is set to 180 ° C. which is the curing temperature of the anisotropic conductive sheet 6, a load of 10 seconds at 75 gf / bump as the pressure 11 of the first stage. In addition, after the anisotropic conductive sheet 6 is cured by 60 to 80%, a load of 30 gf / bumps for 10 seconds is applied as the second stage pressure 12 at the same temperature and the same pressure bonding head 10 for a period of 10 seconds. 6 was cured by 90% or more.
【００２６】以上、図１（ｅ）に示す二段階の圧着工程
により、圧着ヘッド１０の荷重に阻害されること無く異
方性導電シート６の硬化収縮を行うことができ、圧着後
の異方性導電シート６内に圧着荷重と異方性導電シート
６の樹脂の方向的に自由な硬化収縮による内部歪みを減
少させることができた。従来の圧着工程では、表面実装
部品のはんだ付けリフローソルダーリング後に半導体素
子１上のバンプ３と基板電極５間に接合破断を生じる
か、又は、接続抵抗値を、圧着後の１５倍以上に上げて
しまうことがあったが、前記二段階の圧着工程では、リ
フローソルダーリング後の接続抵抗値は、１．２倍に止
まり、耐熱性を向上することができた。As described above, the anisotropic conductive sheet 6 can be cured and shrunk without being hindered by the load of the pressure bonding head 10 by the two-stage pressure bonding process shown in FIG. It was possible to reduce the internal strain due to the pressure bonding load in the conductive conductive sheet 6 and the directionally free curing shrinkage of the resin of the anisotropic conductive sheet 6. In the conventional crimping process, after the soldering reflow soldering of the surface mount component, a joint breakage occurs between the bump 3 on the semiconductor element 1 and the substrate electrode 5, or the connection resistance value is increased to 15 times or more after the crimping. However, in the two-step crimping process, the connection resistance value after the reflow soldering was only 1.2 times, and the heat resistance could be improved.
【００２７】本発明の第二実施形態にかかる回路基板４
への半導体素子１の実装方法を図２（ａ）〜（ｅ）を用
いて説明する。Circuit board 4 according to the second embodiment of the present invention
A method for mounting the semiconductor element 1 on the semiconductor device 1 will be described with reference to FIGS.
【００２８】図２（ａ）において、半導体素子１のＡｌ
パッド（半導体素子側電極）２上に直径２５μｍのＡｕ
線を用いて、ワイヤボンディング装置によりバンプ３を
形成した。In FIG. 2A, the Al of the semiconductor element 1 is
Au having a diameter of 25 μm is formed on the pad (semiconductor element side electrode) 2.
The wire 3 was used to form the bump 3 by a wire bonding apparatus.
【００２９】図２（ｂ）において、ガラスエポキシ基板
４（ＮＥＣ製、ＦＲ−４）上に、厚み８０μｍの異方性
導電シート６（ソニーケミカル製、ＭＪ−９３２）を半
導体素子１実装領域に置き、温度８０℃、荷重１．５ｋ
ｇｆ／ｃｍ2に設定した貼付ヘッド８で貼り付けた。In FIG. 2B, an anisotropic conductive sheet 6 (manufactured by NEC Chemical, MJ-932) having a thickness of 80 μm is mounted on the glass epoxy substrate 4 (manufactured by NEC, FR-4) in the semiconductor element 1 mounting region. Place, temperature 80 ℃, load 1.5k
The application was performed with the application head 8 set to gf / cm 2 .
【００３０】図２（ｃ）において、異方性導電シート６
上のセパレーター７と呼ばれるフィルムを剥がした。In FIG. 2 (c), the anisotropic conductive sheet 6 is used.
The film called Separator 7 above was peeled off.
【００３１】図２（ｄ）において、基板４上の基板電極
５と半導体素子１に形成したバンプ３が接するように位
置合わせして半導体素子マウントヘッド９により載置し
た。In FIG. 2D, the substrate electrodes 5 on the substrate 4 and the bumps 3 formed on the semiconductor element 1 are aligned so as to be in contact with each other and mounted by the semiconductor element mount head 9.
【００３２】図２（ｅ）において、第一段階の温度条件
を異方性導電シート６の軟化温度以上で基板４のガラス
転移温度以下の温度である８０℃に設定して圧着ヘッド
１０で、第一段階の圧力１１として７５ｇｆ／バンプで
１０ｓｅｃ間荷重を加えて半導体素子１上のバンプ３と
基板電極５を電気的に接触させ、第二段階の温度条件を
異方性導電シート６の硬化温度以上である１８０℃に
し、圧力１２として３０ｇｆ／バンプで１０ｓｅｃ間荷
重を加えて、異方性導電シート６を硬化させた。In FIG. 2 (e), the pressure condition of the first step is set to 80 ° C., which is a temperature higher than the softening temperature of the anisotropic conductive sheet 6 and lower than the glass transition temperature of the substrate 4, and the pressure bonding head 10 is used. A pressure of 75 gf / bump is applied for 10 seconds as a pressure 11 in the first step to electrically contact the bump 3 on the semiconductor element 1 with the substrate electrode 5, and the anisotropic conductive sheet 6 is cured under the temperature condition in the second step. The temperature was set to 180 ° C. or higher, and a load of 30 gf / bump was applied for 10 seconds at a pressure of 12 to cure the anisotropic conductive sheet 6.
【００３３】以上、図２（ｅ）に示す二段階の圧着工程
により、半導体素子上バンプ３と基板電極５を基板４の
ガラス転移温度Ｔ（エポキシ樹脂のガラス転移温度Ｔ
は、１３０〜１４５℃である。）未満の温度で接触させ
てから、低荷重で異方性導電シート６を硬化させること
により、従来の圧着工程のような加熱と荷重より基板電
極５を変形させ、電気導電性を損なう恐れなどがなく半
導体素子１を基板４に実装することができた。As described above, the glass transition temperature T of the bumps 3 on the semiconductor element and the substrate electrode 5 (the glass transition temperature T of the epoxy resin T) of the substrate 4 is changed by the two-step pressure bonding process shown in FIG. 2 (e).
Is 130 to 145 ° C. By contacting the anisotropic conductive sheet 6 at a temperature of less than 1) and then curing the anisotropic conductive sheet 6 with a low load, the substrate electrode 5 may be deformed by the heat and load as in the conventional pressure bonding step, and the electrical conductivity may be impaired. The semiconductor element 1 could be mounted on the substrate 4 without any problem.
【００３４】本発明の第三実施形態にかかる回路基板４
への半導体素子１の実装方法を図３（ａ）〜（ｅ）を用
いて説明する。Circuit board 4 according to the third embodiment of the present invention
A method for mounting the semiconductor element 1 on the semiconductor device 1 will be described with reference to FIGS.
【００３５】図３（ａ）において、半導体素子上バンプ
３は、半導体素子１のＡｌパッド（半導体素子側電極）
２上に直径２５μｍのＡｕ線を用いて、ワイヤボンディ
ング装置によりバンプ３を形成した。In FIG. 3A, the bump 3 on the semiconductor element is an Al pad (semiconductor element side electrode) of the semiconductor element 1.
Bumps 3 were formed on the substrate 2 by using a wire bonding device using a 25 μm diameter Au wire.
【００３６】図３（ｂ）において、ガラスエポキシ基板
４（ＮＥＣ製、ＦＲ−４）を示している。In FIG. 3B, a glass epoxy substrate 4 (NEC, FR-4) is shown.
【００３７】図３（ｃ）において、異方性導電ペースト
１５（東芝ケミカル製、ＸＡＰ−００７２）を半導体素
子１実装領域にディスペンス法により塗布した。In FIG. 3C, anisotropic conductive paste 15 (XAP-0072, manufactured by Toshiba Chemical Co., Ltd.) was applied to the semiconductor element 1 mounting region by a dispensing method.
【００３８】図３（ｄ）において、基板４上の基板電極
５と半導体素子１に形成したバンプ３が接するように位
置合わせして半導体素子マウントヘッド９により載置し
た。In FIG. 3D, the semiconductor device mount head 9 was placed by aligning the substrate electrodes 5 on the substrate 4 and the bumps 3 formed on the semiconductor device 1 so as to be in contact with each other.
【００３９】図３（ｅ）において、温度条件を異方性導
電ペースト１５の硬化温度（１６０℃〜２４０℃）であ
る１８０℃に設定し、圧着ヘッド１０で、第一段階の圧
力１１としての７５ｇｆ／バンプで１０ｓｅｃ間荷重を
加え、異方性導電ペースト１５が６０〜８０％硬化した
後、第二段階の圧力１２として３０ｇｆ／バンプで１０
ｓｅｃ間荷重を加え、異方性導電ペースト１５を９０％
以上硬化させた。In FIG. 3E, the temperature condition is set to 180 ° C., which is the curing temperature (160 ° C. to 240 ° C.) of the anisotropic conductive paste 15, and the pressure 11 is used as the pressure 11 at the first stage by the pressure bonding head 10. A load of 75 gf / bump is applied for 10 seconds to cure the anisotropic conductive paste 15 by 60 to 80%, and then a pressure of 30 gf / bump is applied as the second stage pressure 12.
90% of anisotropic conductive paste 15 by applying a load for sec
The above was cured.
【００４０】以上、図３（ｅ）に示す二段階の圧着工程
により、圧着ヘッド１０の荷重に阻害されること無く異
方性導電ペースト１５の硬化収縮を行うことができ、圧
着後の異方性導電ペースト１５内に圧着荷重と異方性導
電ペースト１５の樹脂の方向的に自由な硬化収縮による
内部歪みを減少させることができた。従来の圧着工程で
は、表面実装部品のはんだ付けリフローソルダーリング
後に半導体素子１上のバンプ３と基板電極５間に接合破
断を生じるか、又は、接続抵抗値を、圧着後の１５倍以
上に上げてしまうことがあったが、前記二段階の圧着工
程では、リフローソルダーリング後の接続抵抗値は、
１．２倍に止まり、耐熱性を向上することができた。As described above, the anisotropic conductive paste 15 can be cured and shrunk without being hindered by the load of the pressure bonding head 10 by the two-stage pressure bonding process shown in FIG. It was possible to reduce the internal strain due to the compression load in the conductive conductive paste 15 and the directionally free curing shrinkage of the resin of the anisotropic conductive paste 15. In the conventional crimping process, after the soldering reflow soldering of the surface mount component, a joint breakage occurs between the bump 3 on the semiconductor element 1 and the substrate electrode 5, or the connection resistance value is increased to 15 times or more after the crimping. However, in the two-step crimping process, the connection resistance value after reflow soldering was
The heat resistance was improved to 1.2 times, and the heat resistance could be improved.
【００４１】本発明の第四実施形態にかかる回路基板４
への半導体素子１の実装方法を図４（ａ）〜（ｅ）を用
いて説明する。Circuit board 4 according to the fourth embodiment of the present invention
A method for mounting the semiconductor element 1 on the semiconductor device 1 will be described with reference to FIGS.
【００４２】図４（ａ）において、半導体素子上バンプ
３は、半導体素子１のＡｌパッド（半導体素子側電極）
２上に直径２５μｍのＡｕ線を用いて、ワイヤボンディ
ング装置によりバンプ３を形成した。In FIG. 4A, the bump 3 on the semiconductor element is an Al pad (semiconductor element side electrode) of the semiconductor element 1.
Bumps 3 were formed on the substrate 2 by using a wire bonding device using a 25 μm diameter Au wire.
【００４３】図４（ｂ）において、ガラスエポキシ基板
４（ＮＥＣ製、ＦＲ−４）を示している。FIG. 4B shows a glass epoxy substrate 4 (FR-4, manufactured by NEC).
【００４４】図４（ｃ）において、異方性導電ペースト
１５（東芝ケミカル製、ＸＡＰ−００７２）を半導体素
子１実装領域にディスペンス法により塗布した。In FIG. 4 (c), anisotropic conductive paste 15 (XAP-0072, manufactured by Toshiba Chemical Co., Ltd.) was applied to the semiconductor element 1 mounting region by a dispensing method.
【００４５】図４（ｄ）において、基板４上の基板電極
５と半導体素子１に形成したバンプ３が接するように位
置合わせして半導体素子マウントヘッド９により載置し
た。In FIG. 4 (d), the substrate electrodes 5 on the substrate 4 and the bumps 3 formed on the semiconductor element 1 are aligned so that they are in contact with each other, and the semiconductor element mount head 9 mounts them.
【００４６】図４（ｅ）において、第一段階の温度条件
を異方性導電ペースト１５の軟化温度以上（好ましく
は、１５℃以上）で基板４のガラス転移温度未満である
４０℃に設定して圧着ヘッド１０で、第一段階の圧力１
１として７５ｇｆ／バンプで荷重を加えて半導体素子上
バンプ３と基板電極５を１０ｓｅｃ間電気的に接触さ
せ、第二段階の温度条件を異方性導電ペースト１５の硬
化温度（基板４のガラス転移温度以上で２４０℃以下）
である１８０℃にし、圧力１２として３０ｇｆ／バンプ
で、異方性導電ペースト１５を硬化させた。In FIG. 4 (e), the temperature condition of the first stage is set to 40 ° C., which is higher than the softening temperature of the anisotropic conductive paste 15 (preferably higher than 15 ° C.) and lower than the glass transition temperature of the substrate 4. With the pressure bonding head 10, the first pressure 1
As a result, a load of 75 gf / bump is applied to electrically contact the bumps 3 on the semiconductor element and the substrate electrodes 5 for 10 seconds, and the second stage temperature condition is set to the curing temperature of the anisotropic conductive paste 15 (glass transition of the substrate 4). (Temperature above 240 ° C)
Then, the anisotropic conductive paste 15 was cured at a temperature of 180 ° C. and a pressure of 30 gf / bump.
【００４７】以上、図４（ｅ）に示す二段階の圧着工程
により、半導体素子１上のバンプ３と基板電極５を基板
４のガラス転移温度（エポキシ樹脂のガラス転移温度
は、１３０〜１４５℃である。）未満の温度で接触させ
てから、低荷重で異方性導電ペースト１５を硬化させる
ことにより、従来の圧着工程のような加熱と荷重より基
板電極５を変形させ、電気導電性を損なう恐れなどがな
く半導体素子１を基板４に実装することができた。As described above, the glass transition temperature of the bump 3 and the substrate electrode 5 on the semiconductor element 1 (the glass transition temperature of the epoxy resin is 130 to 145 ° C.) of the substrate 4 by the two-step pressure bonding process shown in FIG. 4E. Then, the anisotropic conductive paste 15 is cured with a low load after contacting at a temperature lower than 100 ° C., so that the substrate electrode 5 is deformed by the heating and the load as in the conventional pressure bonding step, and the electrical conductivity is improved. The semiconductor element 1 could be mounted on the substrate 4 without fear of damage.
【００４８】[0048]
【発明の効果】以上のように本発明は、半導体素子上バ
ンプと基板電極の電気的接触と封止目的の樹脂を半硬化
させた後に、圧着荷重を低荷重にして、自由に封止樹脂
を硬化させ、樹脂中の内部歪みを減少させることができ
るため、半導体素子上バンプと基板電極の接合信頼性を
向上させることができ、また半導体素子の圧着工程につ
いては、異方性導電シート、あるいは異方性導電ペース
トの軟化温度以上基板ガラス転移温度未満で半導体素子
上バンプと基板電極と電気的接触後に、圧着荷重を低荷
重にして、樹脂を硬化させ、基板電極変形を抑制するこ
とができるため、半導体素子の基板電極への圧着工程に
於いての基板電極変形を防止することができる。As described above, according to the present invention, after the resin for the purpose of electrical contact between the bumps on the semiconductor element and the substrate electrode and the resin for sealing are semi-cured, the pressure bonding load is reduced and the sealing resin is freely applied. Can be hardened and internal strain in the resin can be reduced, so that the bonding reliability between the bumps on the semiconductor element and the substrate electrode can be improved, and in the crimping step of the semiconductor element, an anisotropic conductive sheet, Alternatively, after electrical contact between the bumps on the semiconductor element and the substrate electrode at a temperature above the softening temperature of the anisotropic conductive paste and below the glass transition temperature of the substrate, the pressure load is reduced to cure the resin and suppress the substrate electrode deformation. Therefore, it is possible to prevent the substrate electrode from being deformed in the step of crimping the semiconductor element to the substrate electrode.
【図１】（ａ）〜（ｅ）は本発明の第一実施形態にかか
る回路基板への半導体素子の実装方法を示す説明図。1A to 1E are explanatory views showing a method of mounting a semiconductor element on a circuit board according to a first embodiment of the present invention.
【図２】（ａ）〜（ｅ）は本発明の第二実施形態にかか
る回路基板への半導体素子の実装方法を示す説明図。2A to 2E are explanatory views showing a method for mounting a semiconductor element on a circuit board according to a second embodiment of the present invention.
【図３】（ａ）〜（ｅ）は本発明の第三実施形態にかか
る回路基板への半導体素子の実装方法を示す説明図。3A to 3E are explanatory views showing a method for mounting a semiconductor element on a circuit board according to a third embodiment of the present invention.
【図４】（ａ）〜（ｅ）は本発明の第四実施形態にかか
る回路基板への半導体素子の実装方法を示す説明図。4A to 4E are explanatory views showing a method of mounting a semiconductor element on a circuit board according to a fourth embodiment of the present invention.
【図５】（ａ）〜（ｅ）は従来の回路基板への半導体素
子の実装方法を示す説明図。5A to 5E are explanatory views showing a conventional method for mounting a semiconductor element on a circuit board.
【図６】（ａ）〜（ｅ）は従来の回路基板への半導体素
子の実装方法を示す説明図。6A to 6E are explanatory views showing a conventional method for mounting a semiconductor element on a circuit board.
１ 半導体素子 ３ バンプ ４ 回路基板 ５ 電極 ６ 異方性導電シート １５ 異方性導電ペースト Ｔ 加熱温度 Ｐ 加圧条件 1 Semiconductor element 3 bumps 4 circuit board 5 electrodes 6 Anisotropic conductive sheet 15 Anisotropic conductive paste T heating temperature P Pressurization condition
───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 平７−297227（ＪＰ，Ａ) 特開 平９−162235（ＪＰ，Ａ) 特開 平10−144727（ＪＰ，Ａ) 特開 平11−330162（ＪＰ，Ａ) 特開 平11−307584（ＪＰ，Ａ) 実開 平５−77939（ＪＰ，Ｕ) (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 21/60 ─────────────────────────────────────────────────── ─── Continuation of the front page (56) Reference JP-A-7-297227 (JP, A) JP-A-9-162235 (JP, A) JP-A-10-144727 (JP, A) JP-A-11- 330162 (JP, A) Japanese Patent Laid-Open No. 11-307584 (JP, A) Actual Development No. 5-77939 (JP, U) (58) Fields investigated (Int.Cl. 7 , DB name) H01L 21/60
Claims (4)
に貼り付け、半導体素子のバンプと前記回路基板上の電
極を異方性導電シートを介して接するように載置し、半
導体素子からの加熱、加圧で異方性導電シートを硬化し
て、半導体素子を圧着し、前記バンプと前記電極とを接
合する半導体素子の実装方法において、半導体素子の圧
着工程を、 第一段階条件は、加熱温度が１６０〜２４０℃かつ、加
圧条件が５０〜１００ｇ／バンプ、 第二段階条件は、加熱温度が１６０〜２４０℃かつ、加
圧条件が５０ｇ／バンプ以下、の二段階工程で行うこと
を特徴とする半導体素子の実装方法。1. A thermosetting anisotropic conductive sheet is attached to a circuit board, and a bump of the semiconductor element and an electrode on the circuit board are placed so as to be in contact with each other via the anisotropic conductive sheet. In the method for mounting a semiconductor element, in which the anisotropic conductive sheet is cured by heating and pressing from above, the semiconductor element is pressure-bonded, and the bump and the electrode are bonded, Is a heating temperature of 160 to 240 ° C. and a pressurizing condition of 50 to 100 g / bump, and a second stage condition is a heating temperature of 160 to 240 ° C. and a pressurizing condition of 50 g / bump or less. A method for mounting a semiconductor element, which is characterized by carrying out.
に貼り付け、半導体素子のバンプと前記回路基板上の電
極を異方性導電シートを介して接するように載置し、半
導体素子からの加熱、加圧で異方性導電シートを硬化し
て、半導体素子を圧着し、前記バンプと前記電極とを接
合する半導体素子の実装方法において、半導体素子の圧
着工程を、 第一段階条件は、加熱温度が異方性導電シートの軟化温
度以上で基板のガラス転移温度未満かつ、加圧条件が５
０〜１００ｇ／バンプ、 第二段階条件は、加熱条件が基板のガラス転移温度以上
で２４０℃以下かつ、加圧条件が５０ｇ／バンプ以下、
の二段階工程で行うことを特徴とする半導体素子の実装
方法。2. A thermosetting anisotropic conductive sheet is attached to a circuit board, and the bumps of the semiconductor element are placed so as to be in contact with the electrodes on the circuit board via the anisotropic conductive sheet. In the method for mounting a semiconductor element, in which the anisotropic conductive sheet is cured by heating and pressing from above, the semiconductor element is pressure-bonded, and the bump and the electrode are bonded, Means that the heating temperature is equal to or higher than the softening temperature of the anisotropic conductive sheet and lower than the glass transition temperature of the substrate, and the pressure condition is 5
0 to 100 g / bump, the second stage condition is that the heating condition is the glass transition temperature of the substrate or higher and 240 ° C. or lower, and the pressurization condition is 50 g / bump or lower
A method for mounting a semiconductor element, which is performed in a two-step process.
板に塗布し、半導体素子のバンプと前記回路基板上の電
極を異方性導電ペーストを介して接するように載置し、
半導体素子からの加熱、加圧で異方性導電ペーストを硬
化して、半導体素子を圧着し、前記バンプと前記電極と
を接合する半導体素子の実装方法において、半導体素子
の圧着工程を、 第一段階条件は、加熱温度が１６０〜２４０℃かつ、加
圧条件が５０〜１００ｇ／バンプ、 第二段階条件は、加熱温度が１６０〜２４０℃かつ、加
圧条件が５０ｇ／バンプ以下、の二段階工程で行うこと
を特徴とする半導体素子の実装方法。3. A thermosetting anisotropic conductive paste is applied to a circuit board, and the bumps of the semiconductor element are placed so as to be in contact with the electrodes on the circuit board via the anisotropic conductive paste.
In the method of mounting a semiconductor element, the anisotropic conductive paste is cured by heating and pressing from the semiconductor element, the semiconductor element is pressure-bonded, and the bump and the electrode are bonded. The stage conditions include a heating temperature of 160 to 240 ° C. and a pressure condition of 50 to 100 g / bump, and a second stage condition of a heating temperature of 160 to 240 ° C. and a pressure condition of 50 g / bump or less. A method for mounting a semiconductor element, which is performed in a process.
板に塗布し、半導体素子のバンプと前記回路基板上の電
極を異方性導電ペーストを介して接するように載置し、
半導体素子からの加熱、加圧で異方性導電ペーストを硬
化して、半導体素子を圧着し、前記バンプと前記電極と
を接合する半導体素子の実装方法において、半導体素子
の圧着工程を、 第一段階条件は、加熱温度が異方性導電ペーストの軟化
温度以上で基板のガラス転移温度未満かつ、加圧条件が
５０〜１００ｇ／バンプ、 第二段階条件は、加熱温度が基板のガラス転移温度以上
で２４０℃以下かつ、加圧条件は５０ｇ／バンプ以下、
の二段階条件で行うことを特徴とする半導体素子の実装
方法。4. A thermosetting anisotropic conductive paste is applied to a circuit board, and the bumps of the semiconductor element and the electrodes on the circuit board are placed so as to be in contact with each other via the anisotropic conductive paste.
In the method of mounting a semiconductor element, the anisotropic conductive paste is cured by heating and pressing from the semiconductor element, the semiconductor element is pressure-bonded, and the bump and the electrode are bonded. The stage conditions are such that the heating temperature is equal to or higher than the softening temperature of the anisotropic conductive paste and lower than the glass transition temperature of the substrate, and the pressing condition is 50 to 100 g / bump. The second stage condition is that the heating temperature is equal to or higher than the glass transition temperature of the substrate. 240 ° C or less and the pressurizing condition is 50 g / bump or less,
The method for mounting a semiconductor element, which is performed under the following two-step conditions.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP30366998A JP3383774B2 (en) | 1998-10-26 | 1998-10-26 | Semiconductor element mounting method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP30366998A JP3383774B2 (en) | 1998-10-26 | 1998-10-26 | Semiconductor element mounting method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2000133682A JP2000133682A (en) | 2000-05-12 |
| JP3383774B2 true JP3383774B2 (en) | 2003-03-04 |
Family
ID=17923809
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP30366998A Expired - Fee Related JP3383774B2 (en) | 1998-10-26 | 1998-10-26 | Semiconductor element mounting method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3383774B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP6393039B2 (en) * | 2014-02-12 | 2018-09-19 | デクセリアルズ株式会社 | Manufacturing method of connecting body, connecting method and connecting body |
-
1998
- 1998-10-26 JP JP30366998A patent/JP3383774B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JP2000133682A (en) | 2000-05-12 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP4056424B2 (en) | Manufacturing method of semiconductor device | |
| US6153938A (en) | Flip-chip connecting method, flip-chip connected structure and electronic device using the same | |
| JP3886401B2 (en) | Method for manufacturing connection structure | |
| JP3494940B2 (en) | Tape carrier type semiconductor device, manufacturing method thereof, and liquid crystal module using the same | |
| JP2000113919A (en) | Electrical connection device and electrically connecting method | |
| US6528889B1 (en) | Electronic circuit device having adhesion-reinforcing pattern on a circuit board for flip-chip mounting an IC chip | |
| JP3727587B2 (en) | Mounting method of semiconductor device | |
| JP2000195584A (en) | Electrical connection device and electrical connection method | |
| JP2000277649A (en) | Semiconductor and manufacture of the same | |
| JPH1116949A (en) | Acf-bonding structure | |
| JPH10270497A (en) | Semiconductor element fixing method | |
| JP2001257239A (en) | Manufacturing method of semiconductor device | |
| JP3116926B2 (en) | Package structure and semiconductor device, package manufacturing method, and semiconductor device manufacturing method | |
| JP3279470B2 (en) | Semiconductor device and manufacturing method thereof | |
| JP3383774B2 (en) | Semiconductor element mounting method | |
| JP4479582B2 (en) | Manufacturing method of electronic component mounting body | |
| JP4035949B2 (en) | Wiring board, semiconductor device using the same, and manufacturing method thereof | |
| JP3741553B2 (en) | Semiconductor device connection structure and connection method, and semiconductor device package using the same | |
| JP3438583B2 (en) | Anisotropic conductive film connection method | |
| JP3012809B2 (en) | Method for forming electrode structure of semiconductor device | |
| JP2000223534A (en) | Apparatus for mounting semiconductor and method of mounting semiconductor chip | |
| JPH11288975A (en) | Bonding method and device | |
| JP2967560B2 (en) | Connection structure of film carrier | |
| JP2002252326A (en) | Method for manufacturing semiconductor device | |
| JP2004253598A (en) | Method for packaging electronic component |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20071220 Year of fee payment: 5 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20081220 Year of fee payment: 6 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20091220 Year of fee payment: 7 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20091220 Year of fee payment: 7 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20101220 Year of fee payment: 8 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20101220 Year of fee payment: 8 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20111220 Year of fee payment: 9 |
|
| LAPS | Cancellation because of no payment of annual fees |