JP2986466B2 - Circuit board flattening method and semiconductor device manufacturing method - Google Patents
Circuit board flattening method and semiconductor device manufacturing methodInfo
- Publication number
- JP2986466B2 JP2986466B2 JP32565298A JP32565298A JP2986466B2 JP 2986466 B2 JP2986466 B2 JP 2986466B2 JP 32565298 A JP32565298 A JP 32565298A JP 32565298 A JP32565298 A JP 32565298A JP 2986466 B2 JP2986466 B2 JP 2986466B2
- Authority
- JP
- Japan
- Prior art keywords
- circuit board
- adhesive layer
- semiconductor device
- manufacturing
- semiconductor element
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/921—Connecting a surface with connectors of different types
- H01L2224/9212—Sequential connecting processes
- H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
- H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/06—Polymers
- H01L2924/078—Adhesive characteristics other than chemical
- H01L2924/0781—Adhesive characteristics other than chemical being an ohmic electrical conductor
- H01L2924/07811—Extrinsic, i.e. with electrical conductive fillers
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0058—Laminating printed circuit boards onto other substrates, e.g. metallic substrates
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/38—Improvement of the adhesion between the insulating substrate and the metal
- H05K3/386—Improvement of the adhesion between the insulating substrate and the metal by the use of an organic polymeric bonding layer, e.g. adhesive
Landscapes
- Wire Bonding (AREA)
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、回路基板平坦化方
法及び半導体装置の製造方法に関する。The present invention relates to a method for planarizing a circuit board and a method for manufacturing a semiconductor device.
【０００２】[0002]
【従来の技術】半導体装置は、情報通信機器、事務用電
子機器、家庭用電子機器、測定装置、組み立てロボット
等の産業用電子機器、医療用電子機器、電子玩具などの
小型化に寄与し、かつ小型化を容易にする。2. Description of the Related Art Semiconductor devices contribute to the miniaturization of industrial electronic devices such as information communication devices, office electronic devices, home electronic devices, measuring devices, assembling robots, medical electronic devices, and electronic toys. In addition, miniaturization is facilitated.
【０００３】半導体装置を作製するには半導体素子とそ
れを搭載する配線基板が必要である。半導体素子を配線
基板に搭載する技術は、従来はワイヤボンディング法が
主流であったが、最近は半導体素子の実装面積が小さく
できるフリップチップ法が主流となりつつある。半導体
素子を搭載する配線基板において、ワイヤボンディング
法による半導体素子の実装では、半導体素子上の電極か
らワイヤにより半導体素子の外側に位置する配線基板の
電極へ広げるので配線基板上の電極の配置は半導体素子
の電極ピッチより粗いピッチの配置でよい。これに対し
て、フリップチップ法による半導体素子の実装では、半
導体素子の電極配置と配線基板の電極配置が一対一でな
ければならない。したがって、フリップチップ法で半導
体素子を搭載する配線基板は高密度な基板、すなわちフ
ァインラインが形成される基板が望ましい。さらに半導
体装置を小型にするためにはインナービアにより配線層
を接続した基板が必要である。In order to manufacture a semiconductor device, a semiconductor element and a wiring board on which the semiconductor element is mounted are required. Conventionally, a wire bonding method has been mainly used for mounting a semiconductor element on a wiring board. However, recently, a flip chip method capable of reducing a mounting area of a semiconductor element has become mainstream. When mounting a semiconductor element by a wire bonding method on a wiring board on which a semiconductor element is mounted, the arrangement of the electrodes on the wiring board is made of a semiconductor because an electrode on the semiconductor element is spread by a wire to an electrode of a wiring board located outside the semiconductor element. An arrangement with a pitch which is coarser than the electrode pitch of the element may be sufficient. On the other hand, in mounting a semiconductor element by the flip chip method, the electrode arrangement of the semiconductor element and the electrode arrangement of the wiring board must be one-to-one. Therefore, it is desirable that the wiring substrate on which the semiconductor element is mounted by the flip-chip method be a high-density substrate, that is, a substrate on which fine lines are formed. Further, in order to reduce the size of the semiconductor device, a substrate in which wiring layers are connected by inner vias is required.
【０００４】前述の要望を満足させるのはセラミック多
層配線基板であるが、セラミック基板は一般にガラスエ
ポキシ基板等の樹脂基板と比べてコストの低価格化には
限界があり、一般民生機器への導入は限定されているの
が現状である。A ceramic multilayer wiring board satisfies the above-mentioned demand, but the ceramic board is generally limited in terms of cost reduction as compared with a resin board such as a glass epoxy board, and has been introduced into general consumer equipment. Is currently limited.
【０００５】[0005]
【発明が解決しようとする課題】樹脂基板はその製造方
法からセラミック基板より低コスト化できる可能性があ
るが、樹脂基板はセラミック基板より剛性が低いので配
線密度の不均一化や板厚が薄くなると変形し半導体素子
をフリップチップ実装するのは困難となる。Although there is a possibility that the cost of the resin substrate can be reduced from that of the ceramic substrate due to the manufacturing method, the resin substrate has lower rigidity than the ceramic substrate, so that the wiring density becomes uneven and the plate thickness becomes thin. Then, it becomes difficult to flip-chip mount the semiconductor element.
【０００６】本発明は上記従来の半導体装置の課題を解
決し、半導体装置を安定に作製できる製造方法を提供す
ることを目的とする。An object of the present invention is to solve the above-mentioned problems of the conventional semiconductor device and to provide a manufacturing method capable of stably manufacturing a semiconductor device.
【０００７】[0007]
【課題を解決するための手段】第１の本発明（請求項１
対応）は、両面に配線層を有する回路基板を接着層を介
して表面が平坦な板上に固定させる工程を備え、その固
定の際に上から平らな部材で前記回路基板を押圧するこ
とを特徴とする回路基板平坦化方法である。Means for Solving the Problems The first invention (claim 1)
Corresponding) includes a step of fixing a circuit board having a wiring layer on both sides to a flat-surfaced plate via an adhesive layer, and pressing the circuit board with a flat member from above during the fixing. This is a method for flattening a circuit board.
【０００８】第２の本発明（請求項２対応）は、両面に
配線層を有する回路基板を接着層を介して表面が平坦な
板上に固定させる工程と、前記固定した前記回路基板の
露出した配線上に半導体素子上の複数の電極がフェース
ダウンで一対一に接続されるように搭載し接合させる工
程と、前記回路基板と前記半導体素子の隙間を絶縁樹脂
ペーストで充填する工程と、前記絶縁樹脂ペーストを硬
化させる工程と、前記半導体素子を搭載した回路基板
を、前記の表面が平坦な板上の接着層との界面から剥離
する工程とを備え、前記回路基板の固定の際に上から平
らな部材で前記回路基板を押圧することを特徴とする半
導体装置の製造方法である。According to a second aspect of the present invention (corresponding to claim 2), there is provided a step of fixing a circuit board having wiring layers on both sides on a plate having a flat surface via an adhesive layer, and exposing the fixed circuit board. Mounting and joining a plurality of electrodes on the semiconductor element face-down on the wiring thus formed, and bonding the circuit board and the semiconductor element with an insulating resin paste; and Curing the insulating resin paste, and peeling off the circuit board on which the semiconductor element is mounted from the interface with the adhesive layer on the flat surface of the board, and fixing the circuit board. A method for manufacturing a semiconductor device, comprising pressing the circuit board with a flat member.
【０００９】第３の本発明（請求項３対応）は、両面に
配線層を有する回路基板を接着層を介して表面が平坦な
マザーボード上に固定させる工程と、前記固定した前記
回路基板の露出した配線上に半導体素子上の複数の電極
がフェースダウンで一対一に接続されるように搭載し接
合させる工程と、前記回路基板と前記半導体素子の隙間
を絶縁樹脂ペーストで充填する工程と、前記絶縁樹脂ペ
ーストを硬化させる工程とを備え、前記回路基板の固定
の際に上から平らな部材で前記回路基板を押圧すること
を特徴とする半導体装置の製造方法である。A third aspect of the present invention (corresponding to claim 3) is a step of fixing a circuit board having wiring layers on both sides to a flat motherboard via an adhesive layer, and exposing the fixed circuit board. Mounting and joining a plurality of electrodes on the semiconductor element face-down on the wiring thus formed, and bonding the circuit board and the semiconductor element with an insulating resin paste; and Curing the insulating resin paste, and pressing the circuit board with a flat member from above when fixing the circuit board.
【００１０】[0010]
【発明の実施の形態】以下、本発明の実施の形態を図を
参照して説明する。 （実施の形態１）図１〜図５は第１の実施の形態の半導
体装置の製造工程をその順で説明した各工程での断面の
模式図である。Embodiments of the present invention will be described below with reference to the drawings. (Embodiment 1) FIGS. 1 to 5 are schematic views of cross sections in respective steps for explaining a manufacturing process of a semiconductor device according to a first embodiment in that order.
【００１１】図１の工程：両面に配線層１２１を有する
回路基板１２は両面の配線層１２１がインナービアによ
り電気的に接続されており、基板材料はエポキシ樹脂を
主成分としアラミド繊維がエポキシ樹脂中に分散された
構造である。なお、アラミド繊維の代わりにガラス繊維
を用いてもかまわない。回路基板１２のサイズは１２ｍ
ｍ×１２ｍｍ×０．４ｍｍで、１２ｍｍ×１２ｍｍの領
域での平坦性は約３０ミクロンあった。次に平坦性が５
ミクロン以下のガラス板１１を準備した。ガラス板１１
のサイズは４０ｍｍ×４０ｍｍ×１．５ｍｍであった。
回路基板１２とガラス板１１の間に半硬化状態のエポキ
シ樹脂が主成分の接着シート１３（日東シンコー製Ｂ−
ＥＬ１０）を積層した。接着シート１３のサイズは１３
ｍｍ×１３ｍｍ×０．０４ｍｍであった。積層するとき
は約５０℃に加熱した方が作業性が良い。Step of FIG. 1: The circuit board 12 having the wiring layers 121 on both sides is electrically connected to the wiring layers 121 on both sides by inner vias. The structure is dispersed inside. In addition, glass fiber may be used instead of aramid fiber. The size of the circuit board 12 is 12 m
It was mx 12 mm x 0.4 mm and the flatness in the 12 mm x 12 mm area was about 30 microns. Next, flatness is 5
A glass plate 11 having a size of 1 μm or less was prepared. Glass plate 11
Was 40 mm × 40 mm × 1.5 mm.
An adhesive sheet 13 containing a semi-cured epoxy resin as a main component between the circuit board 12 and the glass plate 11 (Bitto Shinko B-
EL10). The size of the adhesive sheet 13 is 13
mm × 13 mm × 0.04 mm. When laminating, heating to about 50 ° C. provides better workability.
【００１２】図２の工程：積層した回路基板１２と接着
シート１３とガラス板１１を、回路基板１２が平坦にな
るように加圧しながら加熱して半硬化状態の接着シート
１３を硬化させた。この時の条件は１５０℃、２０ｇ／
ｃｍ2であった。なお、接着シート１３を硬化させると
きに減圧させた方が気泡の混入なく回路基板１２とガラ
ス板１１を密着させることができる。接着シート１３の
硬化後は回路基板１２がガラス板１１によく密着してお
り回路基板１２の平坦性は１０ミクロン以下であった。
なお、プレス用基板１０でもって回路基板１２を上から
押圧して平坦化を確実とする。Step of FIG. 2: The laminated circuit board 12, the adhesive sheet 13 and the glass plate 11 are heated while applying pressure so that the circuit board 12 becomes flat, thereby curing the adhesive sheet 13 in a semi-cured state. The condition at this time is 150 ° C., 20 g /
cm 2 . When the pressure is reduced when the adhesive sheet 13 is cured, the circuit board 12 and the glass plate 11 can be brought into close contact with each other without air bubbles. After the adhesive sheet 13 was cured, the circuit board 12 was in good contact with the glass plate 11, and the flatness of the circuit board 12 was 10 microns or less.
Note that the circuit board 12 is pressed from above with the pressing substrate 10 to ensure flattening.
【００１３】図３の工程：平坦化された回路基板１２上
に半導体素子１４をフェースダウンで搭載した。搭載方
法は半導体素子１４の電極上に金バンプを形成し、金バ
ンプの先端に導電性接着剤を塗布し、金バンプと回路基
板１２上の配線電極とを導電性接着剤で接合する方法を
採用した。導電性接着剤は銀を導電材料とする内製品
で、硬化温度は１２０℃とした。Step of FIG. 3: A semiconductor element 14 is mounted face down on a flattened circuit board 12. The mounting method includes forming a gold bump on the electrode of the semiconductor element 14, applying a conductive adhesive to the tip of the gold bump, and joining the gold bump and the wiring electrode on the circuit board 12 with the conductive adhesive. Adopted. The conductive adhesive was an internal product using silver as a conductive material, and the curing temperature was 120 ° C.
【００１４】図４の工程：半導体素子１４と回路基板１
２との隙間に絶縁樹脂ペースト１５を充填した後、熱処
理により絶縁樹脂ペースト１５を硬化させた。絶縁樹脂
ペースト１５はエポキシ樹脂を主成分とし二酸化珪素を
充填材として含有する内製品で硬化温度は１５０℃とし
た。このようにして接着シート１３を介してガラス板１
１に密着した半導体装置１６が得られた。この絶縁樹脂
ペースト１５は硬化したのち、半導体装置が曲がること
を防止する機能を発揮する。FIG. 4 process: semiconductor element 14 and circuit board 1
2 was filled with the insulating resin paste 15, and then the insulating resin paste 15 was cured by heat treatment. The insulating resin paste 15 is an internal product containing an epoxy resin as a main component and silicon dioxide as a filler, and has a curing temperature of 150 ° C. In this manner, the glass plate 1 is
The semiconductor device 16 closely contacted with No. 1 was obtained. After the insulating resin paste 15 has hardened, it has a function of preventing the semiconductor device from bending.
【００１５】図５の工程：半導体装置１６をガラス板１
１から外すために、硬化した接着シート１３を約１００
℃に加熱した。硬化した接着シート１３のガラス転移温
度は約７０℃であるので７０℃以上であれば接着シート
１３は構造が軟化して半導体装置１６を容易に外すこと
ができた。Step of FIG. 5: The semiconductor device 16 is
1. Remove the cured adhesive sheet 13 from the
Heated to ° C. Since the glass transition temperature of the cured adhesive sheet 13 is about 70 ° C., if the temperature is 70 ° C. or more, the structure of the adhesive sheet 13 is softened, and the semiconductor device 16 can be easily removed.
【００１６】本実施の形態ではガラス板を使用していた
が平坦性が良好であれば、焼結アルミナ板やＳＵＳ板で
もよい。さらに、平坦性を有する板として、マザーボー
ドを利用することも可能である。その場合は、最終工程
で回路基板１２と半導体素子１４をその板から外す必要
はなく、そのまま使用出来る便利さがある。その際、接
着層の材料としては異方性導電接着剤を用いることが望
ましい。Although a glass plate is used in this embodiment, a sintered alumina plate or a SUS plate may be used as long as the flatness is good. Further, a mother board can be used as a flat plate. In that case, there is no need to remove the circuit board 12 and the semiconductor element 14 from the board in the final step, and there is the convenience of being able to use it as it is. At this time, it is desirable to use an anisotropic conductive adhesive as a material for the adhesive layer.
【００１７】なお、比較実験として上記実施の形態で使
用した接着シートよりも接着力の弱い接着シートおよび
熱可塑性の接着シートでも同様の実験を行った。その結
果を表１に示す。As a comparative experiment, the same experiment was performed with an adhesive sheet having a lower adhesive strength than the adhesive sheet used in the above embodiment and a thermoplastic adhesive sheet. Table 1 shows the results.
【００１８】[0018]
【表１】 [Table 1]
【００１９】各接着シートの接着力は直径５ｍｍの円筒
状のステンレス製部品の底面を接着シートで固定し、垂
直に引っ張ってステンレス製部品が接着シートから剥離
したときの力を測定した。実装性は実施の形態１で述べ
た半導体素子の搭載方法において半導体素子と回路基板
との接続が取れているかどうかで判断した。The adhesive strength of each adhesive sheet was measured by fixing the bottom surface of a cylindrical stainless steel part having a diameter of 5 mm with the adhesive sheet, and pulling vertically to separate the stainless steel part from the adhesive sheet. The mountability was determined based on whether or not the connection between the semiconductor element and the circuit board was established in the semiconductor element mounting method described in the first embodiment.
【００２０】また、本実施の形態では５０ｍｍ×５０ｍ
ｍのサイズのガラス板上に１２ｍｍ×１２ｍｍのサイズ
の回路基板を１個だけ接着したが、図７に示すように複
数個接着しても同様の結果が得られることは言うまでも
ない。Further, in the present embodiment, 50 mm × 50 m
Although only one circuit board having a size of 12 mm × 12 mm was bonded on a glass plate having a size of m, it is needless to say that the same result can be obtained by bonding a plurality of circuit boards as shown in FIG.
【００２１】さらに、本実施の形態では回路基板の両面
に形成された配線がインナービアにより電気的に接続さ
れていたが、内層を経由して接続された、いわゆる多層
配線基板であっても同様の結果が得られることは言うま
でもない。 （実施の形態２）実施の形態２においては、接着シート
を使用せずに接着ペーストを使用した。接着ペーストは
ロックタイト製３０１６で、エポキシ樹脂を主成分とす
る無溶剤タイプの熱硬化絶縁樹脂ペーストである。Further, in the present embodiment, the wirings formed on both sides of the circuit board are electrically connected by the inner vias. However, the same applies to a so-called multilayer wiring board connected via an inner layer. Needless to say, the result is obtained. (Embodiment 2) In Embodiment 2, an adhesive paste is used without using an adhesive sheet. The adhesive paste is Loctite 3016, a non-solvent type thermosetting insulating resin paste mainly composed of epoxy resin.
【００２２】まず、ガラス板上に１３ｍｍ×１３ｍｍの
領域に接着ペーストをスクリーン印刷にて塗布した。こ
のときの膜厚は約５０ミクロンであった。この状態で約
５０℃で熱処理を行い、接着ペーストを半硬化状態と
し、回路基板を積層した。あとは実施の形態１と同じプ
ロセスで半導体装置を作製し、実施の形態１と同様の結
果を得た。First, an adhesive paste was applied to a 13 mm × 13 mm area on a glass plate by screen printing. The film thickness at this time was about 50 microns. In this state, heat treatment was performed at about 50 ° C. to make the adhesive paste into a semi-cured state, and the circuit boards were laminated. After that, a semiconductor device was manufactured by the same process as that of the first embodiment, and the same result as that of the first embodiment was obtained.
【００２３】なお、接着ペーストを半硬化状態にしない
で、回路基板とガラス板を積層したときも同様の結果が
得られたことも確認した。 （実施の形態３）本発明の第３の実施の形態の半導体装
置の製造方法について、図６に基づいて説明する。図６
は第３の実施の形態の半導体装置の一製造工程での断面
の模式図である。It was also confirmed that the same result was obtained when the circuit board and the glass plate were laminated without setting the adhesive paste in a semi-cured state. (Embodiment 3) A method of manufacturing a semiconductor device according to a third embodiment of the present invention will be described with reference to FIG. FIG.
FIG. 10 is a schematic diagram of a cross section in one manufacturing step of the semiconductor device of the third embodiment.
【００２４】回路基板２２が接着層２３を介して平坦な
ガラス板２１に密着して回路基板２２の平坦性を良好な
ものにしている。回路基板２２上に半導体素子２４を搭
載し、半導体素子２４と回路基板２２との隙間に絶縁樹
脂が充填されている。The circuit board 22 is brought into close contact with the flat glass plate 21 via the adhesive layer 23, thereby improving the flatness of the circuit board 22. The semiconductor element 24 is mounted on the circuit board 22, and a gap between the semiconductor element 24 and the circuit board 22 is filled with an insulating resin.
【００２５】実施の形態１と異なるところは、接着層の
材料構成で、本実施の形態の接着層には熱膨張率が、接
着層の材料の熱膨張率より大き大きい充填材２６が含有
されていることである。使用した接着層は内製品で、そ
の材料構成は約７０ｐｐｍ／℃のエポキシ樹脂と充填材
２６として約１５０ｐｐｍ／℃のガラスビーズである。The difference from the first embodiment lies in the material composition of the adhesive layer. The adhesive layer of the present embodiment contains a filler 26 having a larger coefficient of thermal expansion than the material of the adhesive layer. That is. The adhesive layer used was an in-house product, the material composition of which was about 70 ppm / ° C. epoxy resin and about 150 ppm / ° C. glass beads as filler 26.
【００２６】この材料構成の接着層２３を使用すること
により、半導体装置２７をガラス板２１から外すときの
加熱処理で、接着層２３中の高熱膨張率の充填材２６が
膨張し、より簡単に半導体装置２７を外すことができ
た。 （実施の形態４）本発明の第４の実施の形態の半導体装
置の製造方法について、図８に基づいて説明する。図８
は第４の実施の形態の半導体装置の製造工程の断面の模
式図である。By using the adhesive layer 23 having this material composition, the filler 26 having a high coefficient of thermal expansion in the adhesive layer 23 expands by the heat treatment when the semiconductor device 27 is detached from the glass plate 21, so that it can be more easily formed. The semiconductor device 27 could be removed. (Embodiment 4) A method of manufacturing a semiconductor device according to a fourth embodiment of the present invention will be described with reference to FIG. FIG.
FIG. 9 is a schematic cross-sectional view of a manufacturing step of the semiconductor device according to the fourth embodiment.
【００２７】回路基板４２が平坦でかつ回路基板４２の
電極と対応するように開口部４６が設けてある焼結アル
ミナ板４１上に接着層４３を介して密着し平坦性を良好
にした。平坦性が良好な回路基板４２上に半導体素子４
４を搭載した。この状態で、焼結アルミナ板４１に開口
部４６があるので、半導体素子４４と回路基板４２の配
線層１２１との電気的接続の検査が行える。The circuit board 42 was adhered on a sintered alumina plate 41 having an opening 46 so as to correspond to the electrodes of the circuit board 42 through an adhesive layer 43 to improve the flatness. The semiconductor element 4 is mounted on the circuit board 42 having good flatness.
4 was installed. In this state, since the sintered alumina plate 41 has the opening 46, the electrical connection between the semiconductor element 44 and the wiring layer 121 of the circuit board 42 can be inspected.
【００２８】検査の結果、接続不良があった場合は、ま
だ半導体素子４４と回路基板４２が接着されていないの
で、容易に半導体素子４４または回路基板４２を取り替
えて接続が得られるまで繰り返すことができる。こうし
て接続が得られたものだけ半導体素子４４と回路基板４
２との隙間に絶縁樹脂４５を充填し接着した。As a result of the inspection, if there is a connection failure, since the semiconductor element 44 and the circuit board 42 are not yet bonded, the semiconductor element 44 or the circuit board 42 is easily replaced and repeated until a connection is obtained. it can. Only the semiconductor element 44 and the circuit board 4 that have been connected in this way are connected.
The insulating resin 45 was filled in the gap between the two and bonded.
【００２９】[0029]
【発明の効果】以上説明した通り、本発明の半導体装置
の製造方法によれば、平坦性の悪い樹脂基板について
も、安定に半導体素子のフリップチップ実装ができると
いう効果がある。As described above, according to the method of manufacturing a semiconductor device of the present invention, there is an effect that flip-chip mounting of semiconductor elements can be stably performed even on a resin substrate having poor flatness.
【００３０】本発明の半導体装置の製造方法において、
接着層の接着力が１．５ｋｇｆ／５mmΦ以上である場合
は、反りの大きい樹脂基板でも平坦にでき、安定に半導
体素子のフリップチップ実装ができるという効果があ
る。In the method of manufacturing a semiconductor device according to the present invention,
When the adhesive strength of the adhesive layer is 1.5 kgf / 5 mmΦ or more, there is an effect that even a resin substrate having a large warpage can be flattened and a flip chip mounting of a semiconductor element can be performed stably.
【００３１】本発明の半導体装置の製造方法において、
接着層の絶縁樹脂中に充填材が含有され、充填材の熱膨
張率が前記絶縁樹脂の熱膨張率より大きい場合は、半導
体装置を平坦板から外すのは熱処理により容易に行える
という効果がある。In the method of manufacturing a semiconductor device according to the present invention,
When the filler is contained in the insulating resin of the adhesive layer and the coefficient of thermal expansion of the filler is larger than the coefficient of thermal expansion of the insulating resin, there is an effect that the semiconductor device can be easily removed from the flat plate by heat treatment. .
【００３２】本発明の半導体装置の製造方法において、
平坦板の所望箇所に開口部が設けてある場合は、半導体
素子と回路基板との接続の検査が行えるので、不良品を
作製することがないという効果がある。In the method for manufacturing a semiconductor device according to the present invention,
When an opening is provided at a desired position of the flat plate, the connection between the semiconductor element and the circuit board can be inspected, so that there is an effect that a defective product is not produced.
【図１】本発明の第１の実施の形態の半導体装置の製造
工程の第一工程での断面の模式図FIG. 1 is a schematic view of a cross section in a first step of a manufacturing process of a semiconductor device according to a first embodiment of the present invention;
【図２】本発明の第１の実施の形態の半導体装置の製造
工程の第二工程での断面の模式図FIG. 2 is a schematic view of a cross section in a second step of the manufacturing process of the semiconductor device according to the first embodiment of the present invention;
【図３】本発明の第１の実施の形態の半導体装置の製造
工程の第三工程での断面の模式図FIG. 3 is a schematic cross-sectional view illustrating a third step in the manufacturing process of the semiconductor device according to the first embodiment of the present invention;
【図４】本発明の第１の実施の形態の半導体装置の製造
工程の第四工程での断面の模式図FIG. 4 is a schematic diagram of a cross section in a fourth step of the manufacturing process of the semiconductor device according to the first embodiment of the present invention;
【図５】本発明の第１の実施の形態の半導体装置の製造
工程の第五工程での断面の模式図FIG. 5 is a schematic diagram of a cross section in a fifth step of the manufacturing process of the semiconductor device according to the first embodiment of the present invention;
【図６】本発明の第３の実施の形態の半導体装置の一製
造工程での断面の模式図FIG. 6 is a schematic cross-sectional view of a semiconductor device according to a third embodiment of the present invention in one manufacturing step.
【図７】1枚の平坦板に複数個の半導体装置を作製する
ときの一工程での断面の模式図FIG. 7 is a schematic cross-sectional view of one step in manufacturing a plurality of semiconductor devices on one flat plate.
【図８】本発明の第４の実施の形態の半導体装置の製造
工程の断面の模式図FIG. 8 is a schematic cross-sectional view illustrating a manufacturing process of a semiconductor device according to a fourth embodiment of the present invention.
１１、２１、３１ ガラス板（平坦板） ４１ 開口部を有する焼結アルミ
ナ板 １２、２２、３２、４２ 回路基板 １３、３３ 接着シート ２３、４３ 接着層 １４、２４、３４、４４ 半導体素子 １５、２５、３５、４５ 絶縁樹脂（ペースト） １６、２７ 半導体装置 ２６ 高熱膨張率の充填材 ４６ 開口部 １２１ 配線層11, 21, 31 Glass plate (flat plate) 41 Sintered alumina plate having openings 12, 22, 32, 42 Circuit board 13, 33 Adhesive sheet 23, 43 Adhesive layer 14, 24, 34, 44 Semiconductor element 15, 25, 35, 45 Insulating resin (paste) 16, 27 Semiconductor device 26 Filler with high coefficient of thermal expansion 46 Opening 121 Wiring layer
───────────────────────────────────────────────────── フロントページの続き (72)発明者 天見 和由 大阪府門真市大字門真1006番地 松下電 器産業株式会社内 (72)発明者 福村 泰司 大阪府門真市大字門真1006番地 松下電 器産業株式会社内 (56)参考文献 特開 平７−111278（ＪＰ，Ａ) 特開 平10−223807（ＪＰ，Ａ) (58)調査した分野(Int.Cl.6，ＤＢ名) H01L 23/32 H01L 21/60 311 ────────────────────────────────────────────────── ─── Continued on the front page (72) Inventor Kazuyoshi Amami 1006 Kazuma Kadoma, Osaka Prefecture Inside Matsushita Electric Industrial Co., Ltd. (56) References JP-A 7-111278 (JP, A) JP-A 10-223807 (JP, A) (58) Fields investigated (Int. Cl. 6 , DB name) H01L 23/32 H01L 21/60 311
Claims (11)
介して表面が平坦な板上に固定させる工程を備え、その
固定の際に上から平らな部材で前記回路基板を押圧する
ことを特徴とする回路基板平坦化方法。A step of fixing a circuit board having a wiring layer on both sides to a flat-surfaced board via an adhesive layer, and pressing the circuit board with a flat member from above during the fixing. A circuit board flattening method characterized by the above-mentioned.
介して表面が平坦な板上に固定させる工程と、前記固定
した前記回路基板の露出した配線上に半導体素子上の複
数の電極がフェースダウンで一対一に接続されるように
搭載し接合させる工程と、前記回路基板と前記半導体素
子の隙間を絶縁樹脂ペーストで充填する工程と、前記絶
縁樹脂ペーストを硬化させる工程と、前記半導体素子を
搭載した回路基板を、前記の表面が平坦な板上の接着層
との界面から剥離する工程とを備え、前記回路基板の固
定の際に上から平らな部材で前記回路基板を押圧するこ
とを特徴とする半導体装置の製造方法。2. A step of fixing a circuit board having a wiring layer on both sides to a flat-surfaced board via an adhesive layer, and forming a plurality of electrodes on a semiconductor element on exposed wires of the fixed circuit board. Mounting and bonding so that they are connected face-to-face one-to-one, filling a gap between the circuit board and the semiconductor element with an insulating resin paste, curing the insulating resin paste, Separating the circuit board on which the element is mounted from the interface with the adhesive layer on the flat plate, and pressing the circuit board with a flat member from above when fixing the circuit board. A method for manufacturing a semiconductor device, comprising:
介して表面が平坦なマザーボード上に固定させる工程
と、前記固定した前記回路基板の露出した配線上に半導
体素子上の複数の電極がフェースダウンで一対一に接続
されるように搭載し接合させる工程と、前記回路基板と
前記半導体素子の隙間を絶縁樹脂ペーストで充填する工
程と、前記絶縁樹脂ペーストを硬化させる工程とを備
え、前記回路基板の固定の際に上から平らな部材で前記
回路基板を押圧することを特徴とする半導体装置の製造
方法。3. A step of fixing a circuit board having a wiring layer on both sides to a mother board having a flat surface via an adhesive layer, and forming a plurality of electrodes on a semiconductor element on exposed wires of the fixed circuit board. A step of mounting and bonding so that they are connected face-down one-to-one, a step of filling a gap between the circuit board and the semiconductor element with an insulating resin paste, and a step of curing the insulating resin paste, A method of manufacturing a semiconductor device, comprising pressing the circuit board with a flat member from above when fixing the circuit board.
Φ以上であることを特徴とする請求項２又は３記載の半
導体装置の製造方法。4. The adhesive strength of said adhesive layer is 1.5 kgf / 5 mm.
4. The method for manufacturing a semiconductor device according to claim 2, wherein Φ is not less than Φ.
であって熱処理により前記回路基板と前記平坦板を接着
する請求項２、３又は４記載の半導体装置の製造方法。5. The method for manufacturing a semiconductor device according to claim 2, wherein said adhesive layer is initially a thermosetting paste, and said circuit board and said flat plate are bonded by heat treatment.
性樹脂フィルムであって熱処理により前記回路基板と前
記平坦板を接着する請求項２、３又は４記載の半導体装
置の製造方法。6. The method of manufacturing a semiconductor device according to claim 2, wherein the adhesive layer is a thermosetting resin film in a semi-cured state, and the circuit board and the flat plate are bonded by heat treatment.
含有された構造であり、前記充填材の熱膨張率が前記接
着層の材料の熱膨張率より大きい請求項２又は４に記載
の半導体装置の製造方法。7. The adhesive layer has a structure in which a filler is contained in a material of the adhesive layer, and a thermal expansion coefficient of the filler is larger than a thermal expansion coefficient of the material of the adhesive layer. 13. The method for manufacturing a semiconductor device according to item 5.
板を前記接着層を介して固定し、前記複数個の回路基板
上に前記半導体素子を搭載する請求項２〜７のいずれか
に記載の半導体装置の製造方法。8. The semiconductor device according to claim 2, wherein a plurality of said circuit boards are fixed to said one flat plate via said adhesive layer, and said semiconductor element is mounted on said plurality of circuit boards. 13. A method for manufacturing a semiconductor device according to
な板上に固定させる工程では、１５０℃までその接着層
を加熱して硬化接着させ、前記半導体素子を搭載した回
路基板を、前記の表面が平坦な板上の接着層との界面か
ら剥離する工程では、１００℃までその接着層を加熱し
て柔らかくさせることを特徴とする請求項２、４、５、
又は６記載の半導体装置の製造方法。9. In the step of fixing the circuit board on a flat-surfaced board via an adhesive layer, the adhesive layer is heated to 150 ° C. to be cured and adhered, and the circuit board on which the semiconductor element is mounted is formed by: In the step of separating the surface from the interface with the adhesive layer on the flat plate, the adhesive layer is heated to 100 ° C. to soften the adhesive layer.
7. A method for manufacturing a semiconductor device according to item 6.
置に対応する箇所に開口部が設けられ、前記半導体素子
を搭載した後、前記絶縁樹脂ペーストで充填する前に、
その開口部を利用して前記半導体素子と前記回路基板と
の接続の検査を行うことを特徴とする請求項２〜９のい
ずれかに記載の半導体装置の製造方法。10. An opening is provided in the flat plate at a position corresponding to a position of an electrode on the circuit board, and after the semiconductor element is mounted, before filling with the insulating resin paste,
The method for manufacturing a semiconductor device according to claim 2, wherein the inspection of the connection between the semiconductor element and the circuit board is performed using the opening.
項２〜１０のいずれかに記載の半導体装置の製造方法。11. The method according to claim 2, wherein the circuit board is a multilayer wiring board.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP32565298A JP2986466B2 (en) | 1997-11-19 | 1998-11-16 | Circuit board flattening method and semiconductor device manufacturing method |
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP31863097 | 1997-11-19 | ||
| JP9-318630 | 1997-11-19 | ||
| JP32565298A JP2986466B2 (en) | 1997-11-19 | 1998-11-16 | Circuit board flattening method and semiconductor device manufacturing method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH11219985A JPH11219985A (en) | 1999-08-10 |
| JP2986466B2 true JP2986466B2 (en) | 1999-12-06 |
Family
ID=26569444
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP32565298A Expired - Fee Related JP2986466B2 (en) | 1997-11-19 | 1998-11-16 | Circuit board flattening method and semiconductor device manufacturing method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2986466B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7105221B2 (en) * | 2001-07-19 | 2006-09-12 | Toray Industries, Inc. | Circuit board, laminated member for circuit board, and method for making laminated member for circuit board |
-
1998
- 1998-11-16 JP JP32565298A patent/JP2986466B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH11219985A (en) | 1999-08-10 |
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