JPH11112150A - Multilayered substrate and its manufacture - Google Patents

Multilayered substrate and its manufacture

Info

Publication number
JPH11112150A
JPH11112150A JP28434097A JP28434097A JPH11112150A JP H11112150 A JPH11112150 A JP H11112150A JP 28434097 A JP28434097 A JP 28434097A JP 28434097 A JP28434097 A JP 28434097A JP H11112150 A JPH11112150 A JP H11112150A
Authority
JP
Japan
Prior art keywords
wiring pattern
wiring
wiring board
board
conductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP28434097A
Other languages
Japanese (ja)
Inventor
Morimitsu Wakabayashi
守光 若林
Hajime Yamamoto
肇 山本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hokuriku Electric Industry Co Ltd
Original Assignee
Hokuriku Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hokuriku Electric Industry Co Ltd filed Critical Hokuriku Electric Industry Co Ltd
Priority to JP28434097A priority Critical patent/JPH11112150A/en
Publication of JPH11112150A publication Critical patent/JPH11112150A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/321—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by conductive adhesives
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4614—Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination

Abstract

PROBLEM TO BE SOLVED: To provide an inexpensive multilayered substrate which has a simple constitution and can increase the packaging density. SOLUTION: A multilayered substrate comprises a first wiring board 10 having a first wiring pattern 11 formed of a conductor such as copper foil, etc., and a second wiring board 20 having a second wiring pattern 11 formed of copper foil, etc., and to be electrically conducted to the first wiring board 10. Protrusions 15 formed of conductor paste containing copper or silver are partially provided at prescribed spots of the first wiring pattern 11 to be conducted electrically to the second wiring pattern 11, and anisotropic conductors 22 having conductivity in their thickness directions only are provided at the portions corresponding to the protrusions 15 on the second wiring board 20. Then, an insulator of a resin 12 is laminated upon the wiring pattern 11 except the portions which are to be brought into contact with the protrusions 15, and the portions where the protrusions 15 are to be formed.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】この発明は、絶縁性の基板表
面に銅箔等の配線パターンが形成され、各絶縁基板が複
数の層に積層された多層基板とその製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer substrate in which a wiring pattern such as a copper foil is formed on the surface of an insulating substrate, and each insulating substrate is laminated in a plurality of layers, and a method of manufacturing the same.

【０００２】[0002]

【従来の技術】従来、絶縁層を介して複数のプリント配
線が形成された多層基板において、表裏の配線パターン
を導通させたスルーホールを設ける方法としては、基板
に対してドリル穴加工やスルーホールのめっきが必要で
あった。また、部品接続ランドと接続するために、ラン
ド部分と別の場所にスルーホールを設けなければならな
かった。2. Description of the Related Art Conventionally, in a multilayer board having a plurality of printed wirings formed thereon via an insulating layer, a method of providing a through-hole for conducting a wiring pattern on the front and back sides is performed by drilling a hole or through-hole in the board. Plating was required. Further, in order to connect to the component connection land, a through hole must be provided in a place different from the land portion.

【０００３】また、透孔を用いないで導電材料を挟む形
でスルーホールを形成する方法も発表されている。この
方法として、例えばＢ2ＩＴ法やＡＬＩＶＨ法等があ
る。Ｂ2ＩＴ法は、尖鋭な形状の導電部を形成し、絶縁
物を突き破る形で表裏の回路を導通させるものである。
また、ＡＬＩＶＨ法は、ドリルによるビア加工とメッキ
が不要で、例えば炭酸ガスレーザー等で穴開けをし、こ
こに導電体ペーストを充填するものである。Further, a method of forming a through hole by sandwiching a conductive material without using a through hole has been disclosed. As this method, there are, for example, the B 2 IT method and the ALIVH method. In the B 2 IT method, a sharp conductive portion is formed, and the front and back circuits are made conductive by breaking through an insulator.
The ALIVH method does not require via processing and plating with a drill. For example, a hole is formed with a carbon dioxide laser or the like, and the hole is filled with a conductive paste.

【０００４】[0004]

【発明が解決しようとする課題】上記従来の技術の前者
の場合、絶縁基板に透孔を形成し、その透孔のスルーホ
ールの内壁面にメッキを施すための工程が複雑であり、
全体として工数がかかるものであった。また、上記従来
の技術の後者のＢ2ＩＴ法の場合、尖鋭な形の導電部の
形成は容易ではなく、設備も多くを必要とし、さらに、
信頼性にもかけるものである。従って、全体としてコス
トもかかるものであった。また、上記従来の技術の後者
のＡＬＩＶＨの場合、透孔の形成にレーザーを用いるた
め、製造装置が大型化し、さらに製法が全く異なるため
従来の基板技術では対応できないものであった。In the former case of the prior art, a process for forming a through hole in an insulating substrate and plating an inner wall surface of the through hole of the through hole is complicated.
As a whole, man-hours were required. Also, in the case of the latter B 2 IT method of the related art, it is not easy to form a sharp conductive portion, and many facilities are required.
It also depends on reliability. Therefore, the cost is high as a whole. In the case of the latter ALIVH, the laser is used to form the through-hole, so that the manufacturing apparatus becomes large and the manufacturing method is completely different, so that the conventional substrate technology cannot be used.

【０００５】この発明は、上記従来の技術に鑑みて成さ
れたもので、簡単な構成で実装密度を上げることがで
き、コストも安価な多層基板とその製造方法を提供する
ことを目的とする。SUMMARY OF THE INVENTION The present invention has been made in view of the above conventional technology, and has as its object to provide a multilayer board which can increase the mounting density with a simple structure and is inexpensive, and a method of manufacturing the same. .

【０００６】[0006]

【課題を解決するための手段】この発明は、銅箔等の導
電体による第一の配線パターンを有する第一の配線基板
と、この第一の配線基板と電気的導通を行うべき銅箔等
の第二の配線パターンを有する第二の配線基板を設け、
上記第二の配線パターンと電気的導通を行うべき上記第
一の配線パターンの部分の所定の個所の少なくとも一部
に、銅や銀を含有する導電体ペーストにより凸部を設
け、上記第二の配線基板上で上記凸部に対応する部分
に、厚さ方向のみに導電性を有する異方性導電体を付着
した多層基板である。そして、両者の上記対応部分を合
わせて上記第一の配線パターンと第二の配線パターンを
電気的に導通させたものである。さらに、上記凸部が接
触すべき部分及び上記凸部を形成すべき部分を除く、少
なくとも上記配線パターン上に絶縁体の樹脂を積層した
多層基板である。そして、上記第一の配線基板と第二の
配線基板とが、さらに複数組積層され、上記各組間も上
記異方性導電体により導通されているものである。SUMMARY OF THE INVENTION The present invention relates to a first wiring board having a first wiring pattern made of a conductor such as a copper foil, and a copper foil or the like to be electrically connected to the first wiring board. Providing a second wiring board having a second wiring pattern of
At least a part of a predetermined portion of a portion of the first wiring pattern to be electrically connected to the second wiring pattern is provided with a convex portion using a conductive paste containing copper or silver, and the second The multilayer substrate has an anisotropic conductor having conductivity only in the thickness direction attached to a portion corresponding to the convex portion on the wiring board. Then, the first wiring pattern and the second wiring pattern are electrically connected to each other by matching the corresponding portions. Further, the multilayer substrate is obtained by laminating an insulating resin on at least the wiring pattern, except for a portion where the convex portion contacts and a portion where the convex portion is to be formed. A plurality of sets of the first wiring board and the second wiring board are further laminated, and conduction is provided between the sets by the anisotropic conductor.

【０００７】またこの発明は、第一配線パターンを有す
る第一の配線基板と、この第一の配線基板と電気的導通
を行うべき第二の配線パターンを有する第二の配線基板
を備え、上記第二の配線パターンと電気的導通を行うべ
き上記第一の配線パターンに導電体ペーストにより凸部
を設け、上記第二の配線基板上で上記凸部に対応する部
分に、厚さ方向のみに導電性を有する異方性導電体を付
着し、両者の上記対応部分を合わせた状態で加圧して厚
さ方向にのみ導電性を与え、上記第一の配線パターンと
上記第二の配線パターンを電気的に導通させる多層基板
の製造方法である。Further, the present invention comprises a first wiring board having a first wiring pattern, and a second wiring board having a second wiring pattern to be electrically connected to the first wiring board. The first wiring pattern to be electrically connected to the second wiring pattern is provided with a convex portion using a conductive paste, and a portion corresponding to the convex portion on the second wiring substrate is provided only in the thickness direction. Attach an anisotropic conductor having conductivity, pressurize in a state where the corresponding portions of both are combined to give conductivity only in the thickness direction, and form the first wiring pattern and the second wiring pattern This is a method for manufacturing a multilayer substrate to be electrically connected.

【０００８】またこの発明は、第一の配線パターンを有
する第一の配線基板と、この第一の配線基板と電気的導
通を行うべき第二の配線パターンを有する第二の配線基
板を備え、上記第二の配線パターンと電気的導通を行う
べき上記第一の配線パターンに導電体ペーストにより凸
部を設け、この凸部を形成した後、更に上記凸部の少な
くとも頂部を覆うように異方性導電体を付着し、この異
方性導電体を上記第二の配線基板の配線パターンに対面
させて加圧して、厚さ方向にのみ導電性を与え、上記第
一の配線基板と第二の配線パターンを接続する多層基板
の製造方法である。さらに、上記凸部が接触すべき部分
及び上記凸部を形成すべき部分を除く、少なくとも上記
配線パターン上に接着性を有する絶縁体を付着し、上記
第一の配線基板と第二の配線基板を電気的に導通させる
多層基板の製造方法である。Further, the present invention comprises a first wiring board having a first wiring pattern, and a second wiring board having a second wiring pattern to be electrically connected to the first wiring board, The first wiring pattern to be electrically connected to the second wiring pattern is provided with a convex portion by a conductive paste, and after forming the convex portion, anisotropically so as to cover at least the top of the convex portion. The anisotropic conductor is applied, and the anisotropic conductor is pressed against the wiring pattern of the second wiring board to impart conductivity only in the thickness direction. This is a method for manufacturing a multi-layer board for connecting the wiring patterns. Further, an adhesive having an adhesive property is adhered on at least the wiring pattern except for a portion where the convex portion contacts and a portion where the convex portion is to be formed, and the first wiring substrate and the second wiring substrate are attached. This is a method for manufacturing a multilayer substrate that electrically conducts.

【０００９】またこの発明は、第一の配線パターンを有
する第一の配線基板と、この第一の配線基板と電気的導
通を行うべき第二の配線パターンを有する第二の配線基
板を備え、上記第一の配線パターンと上記第二の配線パ
ターンとの少なくとも一方にこの両者の間で電気的導通
を行うべき部分に導電体ペーストにより凸部を設け、そ
の後、上記第一の配線パターンと上記第二の配線パター
ンの間に異方性導電体を介在させて加圧し、上記第一の
配線パターンと上記第二の配線パターンとを接続する多
層基板の製造方法である。さらに、上記凸部が接触すべ
き部分及び上記凸部を形成すべき部分を除く、少なくと
も上記配線パターン上に接着性を有する絶縁体を付着
し、上記第一の配線基板と第二の配線基板とを接合する
ものである。The present invention also includes a first wiring board having a first wiring pattern, and a second wiring board having a second wiring pattern to be electrically connected to the first wiring board, At least one of the first wiring pattern and the second wiring pattern is provided with a projection by a conductive paste at a portion where electrical conduction is to be performed between the first wiring pattern and the second wiring pattern. This is a method for manufacturing a multilayer board for connecting the first wiring pattern and the second wiring pattern by applying pressure by interposing an anisotropic conductor between the second wiring patterns. Further, an adhesive having an adhesive property is adhered on at least the wiring pattern except for a portion where the convex portion contacts and a portion where the convex portion is to be formed, and the first wiring substrate and the second wiring substrate are attached. Is to be joined.

【００１０】またこの発明は、第一の配線パターンを有
する第一の配線基板を備え、第二の配線パターンと電気
的導通を行うべき上記第一の配線パターンに導電体ペー
ストによる凸部を設け、上記第一の配線パターン面に厚
さ方向のみに導電性を有する異方性導電体を付着し、さ
らにその上に導電体を積層して加圧し、上記導電体をエ
ッチングして上記第二の配線パターンを形成し、上記第
一の配線パターンと上記第二の配線パターンを電気的に
導通させる多層基板の製造方法である。そして、上記第
二の配線パターンのうちさらにその上に積層される配線
パターンと接続する部分に上記凸部を形成し、この凸部
形成部部を除いて絶縁体を付着し、上記凸部に上記異方
性導電体を付着して加圧し、これらの動作を繰り返して
多層基板を形成するものである。The present invention further includes a first wiring board having a first wiring pattern, wherein a projection made of a conductive paste is provided on the first wiring pattern to be electrically connected to the second wiring pattern. Attaching an anisotropic conductor having conductivity only in the thickness direction to the first wiring pattern surface, further laminating a conductor thereon and pressing it, etching the conductor, and etching the second conductor. And a method of manufacturing a multilayer substrate in which the first wiring pattern and the second wiring pattern are electrically connected to each other. Then, the convex portion is formed at a portion of the second wiring pattern that is connected to the wiring pattern further laminated thereon, and an insulator is attached except for the convex portion forming portion, and the convex portion is formed. The above-described anisotropic conductor is attached and pressurized, and these operations are repeated to form a multilayer substrate.

【００１１】[0011]

【発明の実施の形態】以下この発明の実施の形態につい
て、図面に基づいて説明する。図１はこの発明の第１実
施形態の多層基板を示すもので、この実施形態の第１の
基板１０には、銅箔により配線パターン１１が形成され
ている。その配線パターン１１の表面及びこの配線パタ
ーン１１以外の基板表面には、後に接続部を形成すべき
部分を除いたほぼ全面に、エポキシ系樹脂による絶縁性
樹脂１２が積層されている。後に接続部を形成すべき部
分の銅箔露出部１４の表面には、その露出部１４より狭
く点状または凸状に銅を含む導電体ペーストの凸部１５
が形成されている。この導電体ペーストの凸部１５は、
鉛や銀など他の材料でもよく、導電性を有するものであ
ればよい。この点状の導電体ペーストの印刷は、乾燥後
に周囲の絶縁性樹脂１２の高さより突出する形になるよ
う厚く印刷する。Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a multi-layer substrate according to a first embodiment of the present invention. A wiring pattern 11 is formed on a first substrate 10 of this embodiment by copper foil. On the surface of the wiring pattern 11 and on the surface of the substrate other than the wiring pattern 11, an insulating resin 12 of an epoxy resin is laminated on almost the entire surface except for a portion where a connection portion is to be formed later. On the surface of the copper foil exposed portion 14 where a connection portion is to be formed later, a convex portion 15 of a conductive paste containing copper in a dot or convex shape narrower than the exposed portion 14 is provided.
Are formed. The protrusion 15 of the conductor paste is
Other materials such as lead and silver may be used as long as they have conductivity. This dot-shaped conductor paste is printed thickly so as to protrude beyond the height of the surrounding insulating resin 12 after drying.

【００１２】また、第二の基板２０も銅箔による配線パ
ターン１１が形成され、その上に導電体ペーストによる
導電体部２１がスクリーン印刷により設けられている。
この導電体部２１と第一の基板１０の導電体ペーストの
凸部１５の間には、凸部１５より幾分か広い面積を持つ
異方性導電体２２が積層されている。異方性導電体２２
は、例えばＡｕコートされた樹脂粒子やＮｉ粒子を混入
された樹脂であり、熱硬化性樹脂及び熱可塑性樹脂の何
れでも良い。粒子径は３〜５μｍ程度であり、樹脂中の
密度は、１６μｍの厚さで１００００〜４００００個／
ｍｍ2である。熱硬化性樹脂としては、例えばエポキシ
樹脂やポリイミド樹脂があり、熱可塑性樹脂としては、
ポリエステル樹脂がある。その他、通常は絶縁性を有す
るとともに、厚さ方向に加圧すると導電性を得ることが
できる材料であれば良い。また、導電体２１は必要に応
じて形成すれば良く、なくても良い。A wiring pattern 11 made of copper foil is also formed on the second substrate 20, and a conductor portion 21 made of a conductor paste is provided thereon by screen printing.
An anisotropic conductor 22 having a somewhat larger area than the protrusion 15 is laminated between the conductor 21 and the protrusion 15 of the conductor paste of the first substrate 10. Anisotropic conductor 22
Is a resin mixed with, for example, Au-coated resin particles or Ni particles, and may be either a thermosetting resin or a thermoplastic resin. The particle diameter is about 3 to 5 μm, and the density in the resin is 10,000 to 40,000 particles /
mm 2 . Examples of the thermosetting resin include an epoxy resin and a polyimide resin, and examples of the thermoplastic resin include:
There is a polyester resin. In addition, any material may be used as long as it generally has an insulating property and can obtain conductivity when pressed in the thickness direction. In addition, the conductor 21 may be formed as needed, and may not be provided.

【００１３】この実施形態の多層基板の製造方法は、先
ず、第一の基板１０と第二の基板２０を形成する。第１
の基板１０は、表面の銅箔をエッチングして配線パター
ン１１を形成する。そして、その配線パターン１１の表
面及びこの配線パターン１１以外の基板表面には、後に
接続部を形成すべき部分を除いたほぼ全面に、エポキシ
系樹脂による絶縁性樹脂１２を印刷し硬化させる。ま
た、後に接続部を形成すべき部分の銅箔露出部１４の表
面には、その露出部１４より狭く導電体ペーストによる
凸部１５を周囲の絶縁性樹脂１２より高く形成する。In the method of manufacturing a multilayer substrate according to this embodiment, first, a first substrate 10 and a second substrate 20 are formed. First
The substrate 10 has a wiring pattern 11 formed by etching the surface copper foil. Then, an insulating resin 12 made of an epoxy resin is printed and hardened on almost the entire surface of the surface of the wiring pattern 11 and the surface of the substrate other than the wiring pattern 11 except for a portion where a connection portion is to be formed later. Further, on the surface of the copper foil exposed portion 14 where a connection portion is to be formed later, a convex portion 15 made of a conductive paste that is narrower than the exposed portion 14 and higher than the surrounding insulating resin 12 is formed.

【００１４】また、第二の基板２０も銅箔による配線パ
ターン１１をエッチングにより形成し、その上に導電体
ペーストにより導電体部２１を、スクリーン印刷により
形成する。そして、この導電体ペーストによる導電体部
２１と第一の基板１０の導電体ペーストによる凸部１５
の間で第二の配線基板２０側に、凸部１５よりわずかに
広い面積を持つように異方性導電体ペーストを印刷す
る。The wiring pattern 11 of copper foil is also formed on the second substrate 20 by etching, and a conductor portion 21 is formed thereon by a conductor paste by screen printing. Then, the conductor portion 21 made of the conductor paste and the projection 15 made of the conductor paste of the first substrate 10 are formed.
Then, an anisotropic conductive paste is printed on the second wiring board 20 side so as to have a slightly larger area than the convex portion 15.

【００１５】次に、第一の基板１０の凸部１５と、第二
の基板２０の異方性導電体２２が互いにに対面するよう
にして、両基板１０，２０を合わせて真空プレス機にセ
ットし、加圧するとともに加熱し硬化させる。これによ
り異方性導電体ペーストはその厚み方向にのみ導電性を
付与される。ここでは導電体ペーストを印刷に切形成し
たが、ポイントの数が少なければ、ディスペンサーを用
いて個々に塗布してもよい。また、加圧方法としては、
バキュームプレス方を用いた。これは層間に空気を挟み
込まないようにして、後のハンダ等の際に加熱により層
間の空気による膨れ等が生じないようにする効果があ
る。Next, the two substrates 10 and 20 are put together in a vacuum press so that the projection 15 of the first substrate 10 and the anisotropic conductor 22 of the second substrate 20 face each other. Set, pressurize, heat and cure. Thereby, the anisotropic conductor paste is given conductivity only in the thickness direction. Here, the conductive paste is cut and formed by printing, but if the number of points is small, the conductive paste may be individually applied using a dispenser. Also, as the pressing method,
The vacuum press method was used. This has the effect of preventing air from being caught between the layers and preventing swelling or the like due to air between the layers due to heating during subsequent soldering or the like.

【００１６】また、第一の配線基板１０に導電体ペース
トを付着し凸部１５が硬化した後に、異方性導電ペース
トをその頭部に重ねて付着しても、同じ構造が得られ
る。さらに、基板１０，２０はそれぞれ多層、または両
面の基板でもよく、上述の方法を重ねて多層化してもよ
い。Further, the same structure can be obtained by applying an anisotropic conductive paste on the first wiring board 10 after the conductive paste is applied to the first wiring board 10 and the projections 15 are hardened. Further, each of the substrates 10 and 20 may be a multi-layered or double-sided substrate, or may be multi-layered by repeating the above-described method.

【００１７】この実施形態の多層基板によれば、印刷工
程、または塗布工程の繰り返しで、多層基板の回路間の
接続が可能であり、さらに、異方性導電体２２を用いて
いるので導電率が上がり、更に、ドリルなどで孔を作ら
なくても接続ポイントに、導電体の突起を設けるだけで
よい。According to the multi-layer substrate of this embodiment, it is possible to connect the circuits of the multi-layer substrate by repeating the printing process or the coating process. Further, since the anisotropic conductor 22 is used, the electric conductivity is reduced. In addition, it is only necessary to provide a projection of the conductor at the connection point without making a hole with a drill or the like.

【００１８】次にこの発明の第二実施形態の多層基板と
その製造方法について、図３を基にして説明する。ここ
で、上記実施形態と同様の構成は同一符号を付して説明
を省略する。この実施形態の回路基板は、第一の基板１
０の第一の配線パターン１１に導電体ペーストの凸部１
５を形成し、さらに、異方性導電体２２のペーストを所
定個所に印刷後、上記第二の配線基板に代わり、第一の
配線パターン１１が形成された面に全面的に、銅箔等の
導電体を設ける。そして、加圧及び加熱し、接着した
後、上記導電体をエッチングして第二の配線パターン１
１を形成する。さらに、これを再び第一の基板１０とし
て、絶縁性樹脂１２と、この絶縁性樹脂１２よりわずか
に突出した凸部１５を形成し、その上に異方性導電体２
２を繰り返して積層する。以降必要な層数の配線パター
ンを形成し、回路基板を多層化する。Next, a multilayer substrate according to a second embodiment of the present invention and a method for manufacturing the same will be described with reference to FIG. Here, the same components as those in the above-described embodiment are denoted by the same reference numerals, and description thereof is omitted. The circuit board according to this embodiment includes a first board 1
0 of the conductive paste on the first wiring pattern 11
5 and further, after printing the paste of the anisotropic conductor 22 at a predetermined location, the entire surface on which the first wiring pattern 11 is formed is replaced with a copper foil or the like instead of the second wiring substrate. Is provided. Then, after applying pressure and heat and bonding, the conductor is etched to form the second wiring pattern 1.
Form one. Further, using this as the first substrate 10 again, the insulating resin 12 and the convex portion 15 slightly projecting from the insulating resin 12 are formed, and the anisotropic conductor 2 is formed thereon.
2 is repeated and laminated. Thereafter, wiring patterns of a required number of layers are formed, and the circuit board is multilayered.

【００１９】この実施形態の多層基板によれば、任意の
層の多層基板を効率よく形成することができ、しかも電
気的接続も確実である。According to the multi-layer substrate of this embodiment, a multi-layer substrate of an arbitrary layer can be efficiently formed, and the electrical connection is reliable.

【００２０】ここで、各層のパターンニングは、光学的
に位置合わせることができる。これにより、ピン等によ
る機械的位置合わせと比べて、熱膨張等の機械的誤差を
なくし、位置精度を向上させることができる。Here, the patterning of each layer can be optically aligned. This eliminates mechanical errors such as thermal expansion as compared with mechanical alignment using a pin or the like, and improves positional accuracy.

【００２１】次にこの発明の第三実施形態の多層基板と
その製造方法について、図４を基にして説明する。ここ
で、上記実施形態と同様の構成は同一符号を付して説明
を省略する。この実施形態の回路基板は、異方性導電体
２２は、必要なポイントのみに付着するのではなく全面
にシート状に挟み込むことより、導電体ペーストによる
凸部１５が当接している部分の異方性導電体２２のみが
加圧されて、その厚み方向に導電性が付与され、加圧の
ない部分は絶縁物として用いることが可能となる。Next, a multilayer substrate according to a third embodiment of the present invention and a method of manufacturing the same will be described with reference to FIG. Here, the same components as those in the above-described embodiment are denoted by the same reference numerals, and description thereof is omitted. In the circuit board of this embodiment, the anisotropic conductor 22 is not attached only to the necessary points, but is sandwiched in a sheet shape over the entire surface, so that the difference in the portion where the projection 15 made of the conductor paste is in contact is obtained. Only the isotropic conductor 22 is pressurized to provide conductivity in the thickness direction, and a portion without pressure can be used as an insulator.

【００２２】なお、この実施形態の場合、導通させる導
電体ペーストによる凸部以外の個所は絶縁物を介装させ
た方が好ましい。これは、加圧により、導通個所以外も
厚み方向に導電性を有することとなる場合があるからで
ある。しかし、この恐れがない場合は、異方性導電体が
絶縁層として作用するので、全面に異方性導電体を設け
ても良く、凸部以外の部分は絶縁層として機能させるこ
とができる。In the case of this embodiment, it is preferable that an insulating material is interposed at portions other than the protrusions made of the conductive paste to be conducted. This is because the pressure may cause conductivity in the thickness direction other than the conductive portion in some cases. However, when there is no fear of this, the anisotropic conductor acts as an insulating layer, so that the anisotropic conductor may be provided over the entire surface, and portions other than the convex portions can function as the insulating layer.

【００２３】[0023]

【発明の効果】この発明の多層基板は、従来の配線パタ
ーンと同様の製造工程で製造可能であり、一般的な設備
や技術で対応でき、コスト面でもきわめて安価に提供可
能であえる。また、異方性材料を導電体に用いているの
で配線パターンとの電気的接続の信頼性も極めて高いも
のにすることが出来る。更に、接続ポイントに導電体の
凸部を設けたので、ドリル穴加工やスルーホールメッキ
といった、複雑でかつ工数のかかる工程を省くことがで
き、効率的である。The multilayer board of the present invention can be manufactured by the same manufacturing process as that of the conventional wiring pattern, can be handled by general equipment and technology, and can be provided at a very low cost. Further, since the anisotropic material is used for the conductor, the reliability of electrical connection with the wiring pattern can be made extremely high. In addition, since the projections of the conductor are provided at the connection points, complicated and time-consuming steps such as drilling and through-hole plating can be omitted, which is efficient.

【図面の簡単な説明】[Brief description of the drawings]

【図１】この発明の第一実施形態の多層基板の製造時の
様子を示す図である。FIG. 1 is a diagram showing a state of a multi-layer substrate according to a first embodiment of the present invention during manufacture.

【図２】この発明の第一実施形態の多層基板の縦断面図
である。FIG. 2 is a longitudinal sectional view of the multilayer substrate according to the first embodiment of the present invention.

【図３】この発明の第二実施形態の多層基板の製造時の
様子を示す図である。FIG. 3 is a view showing a state at the time of manufacturing a multilayer substrate according to a second embodiment of the present invention.

【図４】この発明の第三実施形態の多層基板の縦断面図
である。FIG. 4 is a longitudinal sectional view of a multilayer substrate according to a third embodiment of the present invention.

【符号の説明】[Explanation of symbols]

１０ 第一の基板 １１ 配線パターン １２ 絶縁体 １５ 凸部 ２０ 第二の基板 ２１ 導電体 ２２ 異方性導電体 DESCRIPTION OF SYMBOLS 10 First substrate 11 Wiring pattern 12 Insulator 15 Convex part 20 Second substrate 21 Conductor 22 Anisotropic conductor

Claims (9)

【特許請求の範囲】[Claims] 【請求項１】 導電体による第一の配線パターンを有
する第一の配線基板と、この第一の配線基板と電気的導
通を行うべき第二の配線パターンを有する第二の配線基
板を設け、上記第二の配線パターンと電気的導通を行う
べき上記第一の配線パターンの部分の所定の個所の少な
くとも一部に、導電体ペーストにより凸部を設け、上記
第二の配線基板上で上記凸部に対応する部分に、厚さ方
向のみに導電性を有する異方性導電体を付着し、両者の
上記対応部分を合わせて上記第一の配線パターンと第二
の配線パターンを電気的に導通させた多層基板。1. A first wiring board having a first wiring pattern made of a conductor, and a second wiring board having a second wiring pattern to be electrically connected to the first wiring board, At least a part of a predetermined portion of a portion of the first wiring pattern to be electrically connected to the second wiring pattern is provided with a convex portion with a conductive paste, and the convex portion is formed on the second wiring substrate. An anisotropic conductor having conductivity only in the thickness direction is attached to the portion corresponding to the portion, and the first and second wiring patterns are electrically connected to each other by combining the corresponding portions. Multilayer substrate. 【請求項２】 上記凸部が接触すべき部分及び上記凸
部を形成すべき部分を除く、少なくとも上記配線パター
ン上に絶縁体を付着した請求項１記載の多層基板。2. The multi-layer substrate according to claim 1, wherein an insulator is attached to at least the wiring pattern except for a portion where the projection contacts and a portion where the projection forms. 【請求項３】 上記第一の配線基板と第二の配線基板
とが、さらに複数組積層され、上記各組間も上記異方性
導電体により導通されている請求項１または２記載の多
層基板。3. The multilayer according to claim 1, wherein a plurality of sets of the first wiring board and the second wiring board are further laminated, and the respective sets are electrically connected by the anisotropic conductor. substrate. 【請求項４】 第一の配線パターンを有する第一の配
線基板と、この第一の配線基板と電気的導通を行うべき
第二の配線パターンを有する第二の配線基板を備え、上
記第二の配線パターンと電気的導通を行うべき上記第一
の配線パターンに導電体ペーストにより凸部を設け、上
記第二の配線基板上で上記凸部に対応する部分に、厚さ
方向のみに導電性を有する異方性導電体を付着し、両者
の上記対応部分を合わせた状態で加圧し、上記第一の配
線パターンと第二の配線パターンを電気的に導通させる
多層基板の製造方法。4. A semiconductor device comprising: a first wiring board having a first wiring pattern; and a second wiring board having a second wiring pattern to be electrically connected to the first wiring board. The first wiring pattern to be electrically connected to the first wiring pattern is provided with a convex portion with a conductive paste, and the portion corresponding to the convex portion on the second wiring substrate is electrically conductive only in the thickness direction. A method of manufacturing a multilayer substrate, wherein an anisotropic conductor having the following characteristics is adhered, and pressure is applied in a state where the corresponding portions of the two are combined to electrically connect the first wiring pattern and the second wiring pattern. 【請求項５】 第一の配線パターンを有する第一の配
線基板と、この第一の配線基板と電気的導通を行うべき
第二の配線パターンを有する第二の配線基板を備え、上
記第二の配線パターンと電気的導通を行うべき上記第一
の配線パターンに導電体ペーストにより凸部を設け、こ
の凸部を形成した後、更に上記凸部の少なくとも頂部を
覆うように異方性導電体を付着し、この異方性導電体を
上記第二の配線基板の配線パターンに対面させて加圧し
て接続する多層基板の製造方法。5. A semiconductor device comprising: a first wiring board having a first wiring pattern; and a second wiring board having a second wiring pattern to be electrically connected to the first wiring board. The first wiring pattern to be electrically connected to the first wiring pattern is provided with a convex portion with a conductive paste, and after forming the convex portion, the anisotropic conductor is further covered so as to cover at least the top of the convex portion. And bonding the anisotropic conductor to the wiring pattern of the second wiring substrate by applying pressure and pressure. 【請求項６】 第一の配線パターンを有する第一の配
線基板と、この第一の配線基板と電気的導通を行うべき
第二の配線パターンを有する第二の配線基板を備え、上
記第一の配線パターンと上記第二の配線パターンとの少
なくとも一方にこの両者の間で電気的導通を行うべき部
分に導電体ペーストにより凸部を設け、その後、上記第
一の配線パターンと上記第二の配線パターンの間に異方
性導電体を介在させて加圧し、上記第一の配線パターン
と上記第二の配線パターンとを接続する多層基板の製造
方法。6. A semiconductor device comprising: a first wiring board having a first wiring pattern; and a second wiring board having a second wiring pattern to be electrically connected to the first wiring board. At least one of the wiring pattern and the second wiring pattern is provided with a convex portion by a conductive paste at a portion where electrical conduction is to be performed between the two, and thereafter, the first wiring pattern and the second wiring pattern are provided. A method for manufacturing a multilayer board, wherein an anisotropic conductor is interposed between wiring patterns and pressurized to connect the first wiring pattern and the second wiring pattern. 【請求項７】 上記凸部が接触すべき部分及び上記凸
部を形成すべき部分を除く、少なくとも上記配線パター
ン上に接着性を有する絶縁体を付着し、上記第一の配線
基板と第二の配線基板とを接合する請求項４，５または
６記載の多層基板の製造方法。7. An adhesive having an adhesive property is adhered on at least the wiring pattern except for a portion where the protrusion contacts and a portion where the protrusion is to be formed. 7. The method for manufacturing a multilayer board according to claim 4, wherein the wiring board is bonded to the wiring board. 【請求項８】 第一の配線パターンを有する第一の配
線基板を備え、第二の配線パターンと電気的導通を行う
べき上記第一の配線パターンに導電体ペーストによる凸
部を設け、上記第一の配線パターン面に厚さ方向のみに
導電性を有する異方性導電体を付着し、さらにその上に
導電体を設けて加圧し、上記導電体をエッチングして上
記第二の配線パターンを形成し、上記第一の配線パター
ンと上記第二の配線パターンを電気的に導通させる多層
基板の製造方法。8. A first wiring board having a first wiring pattern, wherein the first wiring pattern to be electrically connected to the second wiring pattern is provided with a projection made of a conductive paste, An anisotropic conductor having conductivity only in the thickness direction is attached to one wiring pattern surface, a conductor is further provided thereon and pressurized, and the conductor is etched to form the second wiring pattern. A method of manufacturing a multilayer substrate, which is formed and electrically connects the first wiring pattern and the second wiring pattern. 【請求項９】 上記第二の配線パターンのうちさらに
その上に積層される配線パターンと接続する部分に上記
凸部を形成し、この凸部形成部部を除いて絶縁体を付着
し、上記凸部に上記異方性導電体を付着して加圧加熱
し、これらの動作を繰り返して多層基板を形成する請求
項８記載の多層基板の製造方法。9. The convex portion is formed at a portion of the second wiring pattern that is connected to a wiring pattern laminated thereon, and an insulator is attached except for the convex portion forming portion. 9. The method for manufacturing a multilayer substrate according to claim 8, wherein the anisotropic conductor is attached to the projections, heated under pressure, and these operations are repeated to form a multilayer substrate.
JP28434097A 1997-09-30 1997-09-30 Multilayered substrate and its manufacture Pending JPH11112150A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP28434097A JPH11112150A (en) 1997-09-30 1997-09-30 Multilayered substrate and its manufacture

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP28434097A JPH11112150A (en) 1997-09-30 1997-09-30 Multilayered substrate and its manufacture

Publications (1)

Publication Number Publication Date
JPH11112150A true JPH11112150A (en) 1999-04-23

Family

ID=17677315

Family Applications (1)

Application Number Title Priority Date Filing Date
JP28434097A Pending JPH11112150A (en) 1997-09-30 1997-09-30 Multilayered substrate and its manufacture

Country Status (1)

Country Link
JP (1) JPH11112150A (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001007472A (en) * 1999-06-17 2001-01-12 Sony Corp Electronic circuit device and its manufacture
WO2001015228A1 (en) * 1999-08-19 2001-03-01 Seiko Epson Corporation Wiring board, method of manufacturing wiring board, electronic device, method of manufacturing electronic device, circuit board and electronic apparatus
WO2001095343A1 (en) * 2000-06-02 2001-12-13 Fujiprint Industrial Co. Ltd. Conductive composition, method for manufacturing electrode or printed board comprising the same, method for connecting electrode comprising the same, and electrode or printed board using the same
JP2007242872A (en) * 2006-03-08 2007-09-20 Sumitomo Electric Printed Circuit Inc Multilayer printed wiring board, and manufacturing method thereof
JP2008034484A (en) * 2006-07-26 2008-02-14 Toshiba Tec Corp Connection method and connection structure for inter-substrate-wiring pattern
JP2010206233A (en) * 2010-06-23 2010-09-16 Sumitomo Electric Printed Circuit Inc Multilayer printed wiring board and manufacturing method of the same
US8486758B2 (en) 2010-12-20 2013-07-16 Tessera, Inc. Simultaneous wafer bonding and interconnect joining

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001007472A (en) * 1999-06-17 2001-01-12 Sony Corp Electronic circuit device and its manufacture
WO2001015228A1 (en) * 1999-08-19 2001-03-01 Seiko Epson Corporation Wiring board, method of manufacturing wiring board, electronic device, method of manufacturing electronic device, circuit board and electronic apparatus
US6977441B2 (en) 1999-08-19 2005-12-20 Seiko Epson Corporation Interconnect substrate and method of manufacture thereof, electronic component and method of manufacturing thereof, circuit board and electronic instrument
WO2001095343A1 (en) * 2000-06-02 2001-12-13 Fujiprint Industrial Co. Ltd. Conductive composition, method for manufacturing electrode or printed board comprising the same, method for connecting electrode comprising the same, and electrode or printed board using the same
JP2007242872A (en) * 2006-03-08 2007-09-20 Sumitomo Electric Printed Circuit Inc Multilayer printed wiring board, and manufacturing method thereof
JP2008034484A (en) * 2006-07-26 2008-02-14 Toshiba Tec Corp Connection method and connection structure for inter-substrate-wiring pattern
JP2010206233A (en) * 2010-06-23 2010-09-16 Sumitomo Electric Printed Circuit Inc Multilayer printed wiring board and manufacturing method of the same
US8486758B2 (en) 2010-12-20 2013-07-16 Tessera, Inc. Simultaneous wafer bonding and interconnect joining
US8709913B2 (en) 2010-12-20 2014-04-29 Tessera, Inc. Simultaneous wafer bonding and interconnect joining

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