JP2954559B2 - Wiring board electrode structure - Google Patents

Wiring board electrode structure

Info

Publication number
JP2954559B2
JP2954559B2 JP9369556A JP36955697A JP2954559B2 JP 2954559 B2 JP2954559 B2 JP 2954559B2 JP 9369556 A JP9369556 A JP 9369556A JP 36955697 A JP36955697 A JP 36955697A JP 2954559 B2 JP2954559 B2 JP 2954559B2
Authority
JP
Japan
Prior art keywords
insulating sheet
electrode
wiring board
conductive
electrode structure
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP9369556A
Other languages
Japanese (ja)
Other versions
JPH11195673A (en
Inventor
悦四 鈴木
秀久 山崎
克成 小寺
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Yamaichi Electronics Co Ltd
Original Assignee
Yamaichi Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Yamaichi Electronics Co Ltd filed Critical Yamaichi Electronics Co Ltd
Priority to JP9369556A priority Critical patent/JP2954559B2/en
Publication of JPH11195673A publication Critical patent/JPH11195673A/en
Application granted granted Critical
Publication of JP2954559B2 publication Critical patent/JP2954559B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/1012—Auxiliary members for bump connectors, e.g. spacers
    • H01L2224/10122—Auxiliary members for bump connectors, e.g. spacers being formed on the semiconductor or solid-state body to be connected
    • H01L2224/10125—Reinforcing structures
    • H01L2224/10126—Bump collar
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
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    • H01L2924/01005—Boron [B]
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    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15182—Fan-in arrangement of the internal vias
    • H01L2924/15183—Fan-in arrangement of the internal vias in a single layer of the multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明はＩＣに貼り合せてＩ
Ｃの外部接点を形成するインターポーザ基板等として好
適な配線基板の電極構造に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention
The present invention relates to an electrode structure of a wiring board suitable as an interposer board or the like forming external contacts of C.

【０００２】[0002]

【従来の技術】従来よりＩＣの接点を配線回路基板やＩ
Ｃソケットとの接続に適したピッチ、又は形態に変換す
る手段としてインターポーザ基板が用いられている。2. Description of the Related Art Conventionally, a contact of an IC is connected to a printed circuit board or an IC.
An interposer substrate is used as a means for converting into a pitch or form suitable for connection with a C socket.

【０００３】例えば従来は図１０に示すように、ポリイ
ミド樹脂シートから成るインターポーザ基板２をＩＣ１
の表面に接着剤３を介して貼り合せ、該インターポーザ
基板２の内表面（貼り合せ面側の表面）に形成された導
電路４の端部とＩＣ１の接点６間をワイヤボンディング
法により微細配線７を介して接続し、ＩＣ１及び配線７
を密封材８で埋め保護している。For example, conventionally, as shown in FIG. 10, an interposer substrate 2 made of a polyimide resin sheet is
The surface of the interposer substrate 2 is bonded via an adhesive 3, and a fine wiring is formed by wire bonding between the end of the conductive path 4 formed on the inner surface (the surface on the bonding surface side) of the interposer substrate 2 and the contact 6 of the IC 1. 7 and the IC 1 and the wiring 7
Is protected by filling with a sealing material 8.

【０００４】次にインターポーザ基板２に予じめ穿けら
れた多数の貫通孔９内に半田を充填してそのインターポ
ーザ基板内表面側の内端部１０ｂ′を上記基板内表面上
に存する上記配線パターン４に融着しＩＣ１との接続を
図ると共に、インターポーザ基板外表面において上記半
田１０ａ′を盛り上げて配線回路基板と接続する半田ボ
ール１０ｃ′を形成している。Next, solder is filled in a large number of through holes 9 previously drilled in the interposer substrate 2 and the inner end 10b 'on the inner surface side of the interposer substrate is filled with the wiring pattern existing on the inner surface of the substrate. In addition, the solder 10a 'is fused to the IC 1 so as to be connected to the IC 1, and the solder 10a' is raised on the outer surface of the interposer substrate to form a solder ball 10c 'connected to the printed circuit board.

【０００５】即ち、上記従来例は上記インターポーザ基
板２の貫通孔９内に半田１０ａ′を充填することにより
同基板２の母材内に多点配置された導電子１０ａを形成
し、該各導電子１０ａの上記インターポーザ基板内表面
側の内端部１０ｂ′に上記ＩＣ１と接続する内部接点部
１０ｂを形成し、各導電子１０ａの上記インターポーザ
基板外表面側の外端部に配線回路基板と接続する外部接
点部１０ｃを形成している。That is, in the prior art, the solder 10a 'is filled in the through hole 9 of the interposer substrate 2 to form the conductors 10a arranged at multiple points in the base material of the substrate 2, and the conductors 10a' are formed. An internal contact portion 10b for connecting to the IC 1 is formed at an inner end 10b 'on the inner surface side of the interposer substrate of the electronic device 10a, and connected to a printed circuit board at an outer end of each conductor 10a on the outer surface side of the interposer substrate. The external contact portion 10c is formed.

【０００６】[0006]

【発明が解決しようとする課題】而して上記従来の接点
変換構造においてはインターポーザ基板を形成するポリ
イミド樹脂シートにレーザ加工、エッチング加工等によ
り無数の孔穿け加工を行なわねばならないため、非常に
コスト高となる。又高度の孔穿け技術と工程及び設備増
を招く問題を有している。However, in the above-mentioned conventional contact conversion structure, the polyimide resin sheet for forming the interposer substrate has to be subjected to an infinite number of holes by laser processing, etching or the like, which is very costly. Will be high. In addition, there is a problem that a high level of drilling technology and an increase in the number of processes and equipment are caused.

【０００７】又貫通孔間のピッチ縮小には限界があり、
これが導電路の微小ピッチ化を妨げ、従ってＩＣの接点
の微小ピッチ化に対応し難い問題を有している。Also, there is a limit in reducing the pitch between through holes,
This hinders the miniaturization of the pitch of the conductive path, and thus has a problem that it is difficult to cope with the miniaturization of the contact of the IC.

【０００８】[0008]

【課題を解決するための手段】本発明は上記問題を適切
に解決する。その手段として、液晶ポリマーに代表され
る絶縁シートの一方表面に延在せる導電路の局部を絶縁
シートの他方表面へ向け曲げ込んで突曲部を形成し、該
突曲部の頂部に絶縁シートの他方表面に配される電極を
形成した配線基板の電極構造を提供する。The present invention appropriately solves the above problems. As a means, a local portion of a conductive path extending on one surface of an insulating sheet typified by a liquid crystal polymer is bent toward the other surface of the insulating sheet to form a bent portion, and an insulating sheet is formed on the top of the bent portion. To provide an electrode structure of a wiring board on which an electrode arranged on the other surface is formed.

【０００９】上記配線基板においては導電路を同シート
の一方表面側から他方表面側に単に曲げ込んで、その頂
部に電極を形成する極めて簡単な方法で電極形成が可能
であり、導電路の微小ピッチ化を容易にして、ＩＣの接
点の微小ピッチ化に有効に対処でき、又逆に電極のラン
ド径を充分に確保できる。In the above-mentioned wiring board, it is possible to form an electrode by an extremely simple method of simply bending a conductive path from one surface side to the other surface side of the sheet and forming an electrode on the top. The pitch can be easily made, and it is possible to effectively cope with the minute pitch of the contacts of the IC, and conversely, the land diameter of the electrode can be sufficiently secured.

【００１０】上記突曲部の頂部の電極は下記に例示の構
成を有する。The electrode at the top of the bent portion has the following configuration.

【００１１】上記突曲部の頂部を絶縁シートの他方表
面に露出させて平坦なランド面を形成し、この平坦なラ
ンド面で上記電極を形成する。The top of the bent portion is exposed to the other surface of the insulating sheet to form a flat land surface, and the flat land surface forms the electrode.

【００１２】上記絶縁シートの他方表面に上記突曲部
と対応して導電ペーストを点状に埋め込み、該導電ペー
ストはこの埋め込み部において突曲部の頂部に接合さ
れ、加えて該導電ペーストは上記絶縁シートの他方表面
において平坦なランド面を形成し、該平坦ランド面で上
記電極を組成する。A conductive paste is buried in the other surface of the insulating sheet in a manner corresponding to the bent portion, and the conductive paste is bonded to the top of the bent portion at the buried portion. A flat land surface is formed on the other surface of the insulating sheet, and the electrode is formed on the flat land surface.

【００１３】上記導電ペーストの平坦ランド面又は突
曲部の頂面の平坦ランド面にメッキ層を施して又は半田
ボールを付設して上記電極を組成する。 上記各例示に
おいて、上記突曲部の曲げ込み側に形成された凹所内に
は絶縁材又は導電金属材から成るバックアップ材を充填
する。The above-mentioned electrode is formed by applying a plating layer to a flat land surface of the conductive paste or a flat land surface on the top surface of the protruding portion or by attaching a solder ball. In each of the above examples, the recess formed on the bent side of the protruding portion is filled with a backup material made of an insulating material or a conductive metal material.

【００１４】上記電極構造によればマザーボード等の電
子部品と接続するための平坦なランド面の面積を充分に
確保し、メッキ層形成面積やボール形成面積を確保す
る。又逆に突曲部の曲げ込み側においては突曲部の曲げ
込み径の選択の自由度が高く、例えば０．１ミリや０．
２ミリ程度の曲げ込み径にすることも可能であり、よっ
て導電路の高密度・微細化、ＩＣの接点の極小ピッチ化
に有効に応えることができる。According to the above-mentioned electrode structure, a sufficient area of a flat land surface for connecting to an electronic component such as a motherboard is ensured, and an area for forming a plating layer and an area for forming a ball are ensured. Conversely, on the bending side of the protruding portion, the degree of freedom in selecting the bending diameter of the protruding portion is high, for example, 0.1 mm or 0.1 mm.
It is also possible to make the bent diameter of about 2 mm, so that it is possible to effectively respond to the densification and fineness of the conductive path and the extremely small pitch of the contact points of the IC.

【００１５】上記凹所内に充填されたバックアップ材は
上記比較的剛性に欠ける突曲部を補強して健全なる電極
を形成し、ＩＣの外部端子との接続の信頼性を高める。The back-up material filled in the recess reinforces the relatively inflexible protruding portion to form a sound electrode and enhances the reliability of connection with the external terminals of the IC.

【００１６】又このバックアップ材を導電金属材にする
ことにより、ＩＣの外部端子との電極の通電性を向上す
る。By making the backup material a conductive metal material, the conductivity of the electrodes with the external terminals of the IC is improved.

【００１７】[0017]

【発明の実施の形態】図１Ａに示すように絶縁シート１
の一方表面に銅箔に代表される導電箔２を貼り合せ、同
他方表面に導電ペースト３を点状に多数埋め込み、該導
電ペースト３を絶縁シート１の他方表面に露出させたシ
ートを用意する。該導電ペースト３の露出面は絶縁シー
ト１の表面と同一レベルにする。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS As shown in FIG.
A conductive foil 2 typified by a copper foil is adhered to one surface of the insulating sheet 1, and a large number of conductive pastes 3 are buried in the other surface in the form of dots to prepare a sheet in which the conductive paste 3 is exposed on the other surface of the insulating sheet 1. . The exposed surface of the conductive paste 3 is at the same level as the surface of the insulating sheet 1.

【００１８】次に図１Ｂに示すように、上記絶縁シート
１の一方表面に貼り合せられた導電箔２の局部を上記導
電ペースト３と対応する多点において、プレスにより同
シート１の他方表面側へ曲げ込み突曲部４を形成する。Next, as shown in FIG. 1B, a local portion of the conductive foil 2 bonded to one surface of the insulating sheet 1 is pressed at multiple points corresponding to the conductive paste 3 on the other surface side of the sheet 1 by pressing. A bent portion 4 is formed.

【００１９】上記絶縁シート１を台盤上に置き、上方か
ら多数の突起１９を有する熱加圧盤１８によって絶縁シ
ート１を加熱軟化しつつ上記導電箔２を突起によりプレ
スすることにより、上記突曲部４を容易に形成できる。
又突起１９の選択により突曲部４の曲げ込み径を微小化
できる。The insulating sheet 1 is placed on a base plate, and the conductive foil 2 is pressed by the projections while the insulating sheet 1 is heated and softened by a hot pressing plate 18 having a large number of projections 19 from above, thereby forming the above-mentioned bending. The part 4 can be easily formed.
Further, by selecting the projection 19, the bent diameter of the protruding portion 4 can be reduced.

【００２０】上記絶縁シート１は上記プレス時に熱によ
って軟化するシートを用い、この絶縁シート１の適性材
として液晶ポリマーを用いる。液晶ポリマーは熱により
極めて容易に軟化し、上記突曲部のプレス加工を容易に
する。The insulating sheet 1 is a sheet which is softened by heat at the time of pressing, and a liquid crystal polymer is used as a suitable material for the insulating sheet 1. The liquid crystal polymer is very easily softened by heat, and facilitates the press working of the bent portion.

【００２１】即ち、上記プレス加工による突曲部の絶縁
シート１内への突入を著しく容易にする。又液晶ポリマ
ーは環境温度に対する収縮及び吸湿性が極端に少なく、
上記電極ピッチの維持や電気的特性の向上において適材
である。That is, it is possible to remarkably facilitate the protrusion into the insulating sheet 1 by the press working. In addition, liquid crystal polymers have extremely low shrinkage and hygroscopicity with respect to environmental temperature,
It is suitable for maintaining the electrode pitch and improving electrical characteristics.

【００２２】上記熱プレスにより形成された突曲部４
は、図３Ａに示すように絶縁シート１を塑性変形させつ
つ、絶縁シート１の一方の表面側から他方表面へ深く突
入され、その頂部４ａを上記導電ペースト３内へ突入し
て同頂部４ａに導電ペースト３を接合する。The protruding portion 4 formed by the hot press
3A, while plastically deforming the insulating sheet 1 as shown in FIG. 3A, the insulating sheet 1 is protruded deeply from one surface side to the other surface, and the top 4a is protruded into the conductive paste 3 to be inserted into the top 4a. The conductive paste 3 is joined.

【００２３】好ましくは上記導電ペースト３としては上
記絶縁シート１の軟化点より高い軟化点を有する金属粉
と合成樹脂ペーストの混練物を用い、適例としてニッケ
ル粉を合成樹脂ペーストで混練したもの、又は銀粉を合
成樹脂ペーストで混練したもの等を用いる。Preferably, as the conductive paste 3, a kneaded product of a metal powder having a softening point higher than the softening point of the insulating sheet 1 and a synthetic resin paste is used. As a suitable example, nickel powder is kneaded with a synthetic resin paste. Alternatively, a material obtained by kneading silver powder with a synthetic resin paste is used.

【００２４】図３Ｂは上記組成の導電ペースト３と導電
箔２のメカニカルな接続構造を模視的に示している。同
図に示すように、上記突曲部４が導電ペースト３中に強
力に突入することにより導電ペースト３中の金属粉の粒
子３ａが導電箔２の表面（頂部４ａの表面）に喰い込み
健全なる電気的接続を果す。FIG. 3B schematically shows a mechanical connection structure between the conductive paste 3 and the conductive foil 2 having the above composition. As shown in the figure, the protrusions 4 strongly penetrate into the conductive paste 3 so that the metal powder particles 3a in the conductive paste 3 bite into the surface of the conductive foil 2 (the surface of the top 4a). Make an electrical connection.

【００２５】他方上記導電ペースト３は図３Ａに示すよ
うに、絶縁シート１の他方表面において、該表面と略同
一レベルの平坦で且つ略円形のランド面５を形成する。
この平坦ランド面５のランド径Ｒは導電ペースト３の埋
め込み量によって自由に設定でき、この平坦ランド面５
を電極組成面として供する。On the other hand, as shown in FIG. 3A, the conductive paste 3 forms a flat and substantially circular land surface 5 on the other surface of the insulating sheet 1 at substantially the same level as the surface.
The land diameter R of the flat land surface 5 can be freely set according to the amount of the conductive paste 3 to be embedded.
As an electrode composition surface.

【００２６】例えばこの平坦ランド面５そのものを電極
面とするか、又はこの平坦ランド面５にメッキ層や、半
田ボールを付設して電極を組成する。For example, the flat land surface 5 itself is used as an electrode surface, or a plating layer or a solder ball is attached to the flat land surface 5 to form an electrode.

【００２７】図２は図１Ｂによって形成された導電ペー
スト３の平坦ランド面５に導電メッキ層６を施して電極
を組成している。FIG. 2 shows a configuration in which a conductive plating layer 6 is applied to the flat land surface 5 of the conductive paste 3 formed according to FIG. 1B to form an electrode.

【００２８】上記メッキ層６によって形成されたランド
径は上記導電ペースト３によって形成されたランド径Ｒ
と略同一である。The land diameter formed by the plating layer 6 is equal to the land diameter R formed by the conductive paste 3.
Is substantially the same as

【００２９】図４に示すように上記導電箔２にエッチン
グ等によるパターンニング処理を施して導電路２′を形
成し、この配線基板をＩＣ１２に貼り合せて接点変換を
行なうインターポーザ基板として用いる。As shown in FIG. 4, the conductive foil 2 is patterned by etching or the like to form a conductive path 2 ', and this wiring board is bonded to the IC 12 to be used as an interposer board for converting contacts.

【００３０】即ち、図４は上記電極構造を持つ配線基板
を用いたＩＣ１２の接点変換構造と、該接点変換構造を
持つＩＣパッケージを示している。FIG. 4 shows a contact conversion structure of the IC 12 using a wiring board having the above-mentioned electrode structure, and an IC package having the contact conversion structure.

【００３１】インターポーザ基板１３はフレキシブルな
絶縁シート１から成り、ＩＣ１２との貼り合せ面となる
該基板内表面に密着された、ＩＣ１２との接続に供され
る上記導電路２′即ち配線パターンを有する。よって上
記インターポーザ基板１３は絶縁シート１の内表面にの
み導電路２′を有する片面配線基板である。The interposer substrate 13 is made of a flexible insulating sheet 1 and has the above-described conductive path 2 ′, that is, a wiring pattern, which is in close contact with the inner surface of the substrate and serves as a bonding surface with the IC 12, and is provided for connection with the IC 12. . Therefore, the interposer substrate 13 is a single-sided wiring substrate having a conductive path 2 ′ only on the inner surface of the insulating sheet 1.

【００３２】上記インターポーザ基板１３を上記導電路
２を施した側の表面を以ってＩＣ１２の一方の表面、例
えば接点１２ａを配した側の表面と反対側の表面に接着
剤１５を介し貼り合せる。このインターポーザ基板１３
とＩＣ１２の貼り合せ面を内表面と称し、貼り合せ面と
反対側の表面を外表面と称する。The interposer substrate 13 is bonded to one surface of the IC 12, for example, the surface opposite to the surface on which the contacts 12 a are provided, with an adhesive 15 therebetween, with the surface on which the conductive path 2 is provided. . This interposer substrate 13
The bonding surface of the IC 12 and the IC 12 is called an inner surface, and the surface opposite to the bonding surface is called an outer surface.

【００３３】導電路２′をカバーコート１６で覆う場
合、インターポーザ基板１３は該カバーコート１６を施
した内表面を以ってＩＣ１２の内表面に貼り合せる。When covering the conductive path 2 ′ with the cover coat 16, the interposer substrate 13 is bonded to the inner surface of the IC 12 with the inner surface provided with the cover coat 16.

【００３４】インターポーザ基板１３はその端縁部をＩ
Ｃ１２の端縁部より張り出し、この張り出し部の内表面
において導電路２′の端部をカバーコート１６から露出
させ、接続用パッド２″を形成する。この接続用パッド
２″は上記張り出し部の内表面に沿って多数列配置され
ている。同様にＩＣ１２の接点１２ａはＩＣ１２の端縁
部外表面に沿って多数列配置されている。The edge of the interposer substrate 13 is I
C12 protrudes from the edge, and on the inner surface of the protruding portion, the end of the conductive path 2 'is exposed from the cover coat 16 to form a connecting pad 2 ". The connecting pad 2" is formed of the protruding portion. Many rows are arranged along the inner surface. Similarly, a large number of contacts 12a of the IC 12 are arranged along the outer surface of the edge of the IC 12.

【００３５】該ＩＣ１２の接点１２ａと接続用パッド
２″間をワイヤーボンディング法を用い微細配線１７に
より接続する。斯くしてＩＣ１２とインターポーザ基板
１３とは微細配線１７と導電路２′を介して接続され
る。The contact 12a of the IC 12 and the connection pad 2 "are connected by the fine wiring 17 using a wire bonding method. Thus, the IC 12 and the interposer substrate 13 are connected to the fine wiring 17 via the conductive path 2 '. Is done.

【００３６】そして上記インターポーザ基板１３を形成
するフレキシブル絶縁シート１の母材内に前記構造の多
数の突曲部４を多点配置する。そして突曲部４の頂面に
前記各種構造の電極を組成する。例えばこの電極のラン
ド面５にはメッキ層６又は半田ボール２０等が付設さ
れ、ＩＣパッケージが形成される。尚上記ＩＣは密封材
２１により密封する。Then, a large number of the bent portions 4 having the above structure are arranged at multiple points in the base material of the flexible insulating sheet 1 forming the interposer substrate 13. Then, the electrodes having the above-described various structures are formed on the top surface of the bent portion 4. For example, a plating layer 6 or a solder ball 20 is provided on the land surface 5 of the electrode to form an IC package. The IC is sealed with a sealing material 21.

【００３７】上記ＩＣパッケージにおいては突曲部４に
よって形成された電極がＩＣ１２の外部接点を形成し、
この外部接点によってＩＣ１２の接点１２ａのピッチや
形態を変換する。In the above IC package, the electrodes formed by the bent portions 4 form external contacts of the IC 12,
The pitch and form of the contact 12a of the IC 12 are converted by the external contact.

【００３８】図１乃至図３における導電箔２は導電路
２′と読み換えて説明できる。導電箔２はエッチング等
によりパターンニングして導電路２′が形成され、この
導電路２′に上記図１に示す突曲部４を形成することが
できる。The conductive foil 2 in FIG. 1 to FIG. 3 can be described in the form of a conductive path 2 ′. The conductive foil 2 is patterned by etching or the like to form a conductive path 2 ', and the bent portion 4 shown in FIG. 1 can be formed in the conductive path 2'.

【００３９】次に、図５、図６は上記電極構造に関する
他例を示している。図５に示すように、絶縁シート１の
一方表面に導電路２′が延在され、この導電路２′の局
部を液晶ポリマー等から成る絶縁シート１の他方表面へ
向け曲げ込んで突曲部４を形成し、この突曲部４の頂部
４ａを絶縁シート１を貫いて同シート１の他方表面に露
出させ、この露出面を使用して電極を組成する。Next, FIGS. 5 and 6 show other examples of the above electrode structure. As shown in FIG. 5, a conductive path 2 'extends on one surface of the insulating sheet 1, and a local portion of the conductive path 2' is bent toward the other surface of the insulating sheet 1 made of a liquid crystal polymer or the like to form a bent portion. 4 is formed, the top 4a of the bent portion 4 is exposed through the insulating sheet 1 to the other surface of the sheet 1, and the exposed surface is used to form an electrode.

【００４０】又図５は突曲部４の頂部４ａが絶縁シート
１の他表面より充分に突出するように露出させた例をも
示す。この場合、頂部４ａがマザーボード等の外部配線
基板或いは電子部品に接続された時、その熱膨張差によ
る熱ストレスを突曲部４の変形で容易に緩和できる利点
がある。FIG. 5 also shows an example in which the top 4a of the protruding portion 4 is exposed so as to sufficiently protrude from the other surface of the insulating sheet 1. In this case, when the top 4a is connected to an external wiring board such as a motherboard or an electronic component, there is an advantage that thermal stress due to a difference in thermal expansion can be easily relieved by deformation of the bent portion 4.

【００４１】例えば図６に示すように、上記突曲部４の
頂面に導電金属によるメッキ層６を形成して電極を組成
し、この電極、即ちメッキ層６の表面を図４における接
点変換されたＩＣパッケージの外部接点とする。勿論上
記メッキ層６を施さず、突曲部４の頂面をそのままラン
ド面とする場合を排除するものではない。For example, as shown in FIG. 6, a plating layer 6 made of a conductive metal is formed on the top surface of the bent portion 4 to form an electrode, and this electrode, that is, the surface of the plating layer 6 is contact-converted in FIG. External contact of the IC package. Of course, this does not exclude the case where the plating layer 6 is not applied and the top surface of the protruding portion 4 is used as the land surface as it is.

【００４２】上記電極のランド径を確保するために、図
５Ａ、Ｂに示すように突曲部４の頂部４ａの頂面を絶縁
シート１の表面において、略平坦に露出させ、この平坦
頂面を電極組成面として供する。In order to secure the land diameter of the electrode, the top surface of the top portion 4a of the protruding portion 4 is exposed substantially flat on the surface of the insulating sheet 1 as shown in FIGS. As an electrode composition surface.

【００４３】上記のような平坦頂面を有する平坦頂部４
ａは、導電箔２又は導電路２′を塑性変形させる加圧盤
の突起の形状によって容易に付形できる。Flat top 4 having a flat top as described above
“a” can be easily formed by the shape of the protrusion of the pressure plate that plastically deforms the conductive foil 2 or the conductive path 2 ′.

【００４４】例えば、図５Ｂに示すように導電路２′を
その短手巾方向においてその全巾を曲げ加工することに
よって上記平坦頂部４ａを形成する。For example, as shown in FIG. 5B, the flat top 4a is formed by bending the entire length of the conductive path 2 'in the short width direction.

【００４５】次に好ましくは図７に示すように、上記図
１乃至図６の突曲部４の曲げ込み側に形成された凹所９
内にバックアップ材１０を充填する。Next, preferably, as shown in FIG. 7, a recess 9 formed on the bent side of the protruding portion 4 shown in FIGS.
Is filled with a backup material 10.

【００４６】このバックアップ材１０は合成樹脂等の絶
縁材を用いるか、導電金属材を用いる。絶縁シート１の
表面に形成される導電路２′は比較的薄く剛性に欠け、
従ってこれを曲げ込んで形成された突曲部４も剛性に欠
ける場合が多い。The backup material 10 uses an insulating material such as a synthetic resin or a conductive metal material. The conductive path 2 'formed on the surface of the insulating sheet 1 is relatively thin and lacks rigidity.
Accordingly, the bent portion 4 formed by bending the bent portion also often lacks rigidity.

【００４７】図７の例示は上記突曲部４の曲げ込み側に
形成された凹所９内にバックアップ材１０を充填するこ
とにより、突曲部４及びその頂部４ａに組成される電極
の強度を高め、電極をマザーボード等に健全に接続する
ことができる。又上記バックアップ材１０を導電金属と
することより、突曲部４により組成される電極の電気的
性能を著しく高める。FIG. 7 shows the strength of the electrode formed on the bent portion 4 and its top 4a by filling the backing material 10 into the recess 9 formed on the bent side of the bent portion 4. And the electrodes can be connected to the motherboard or the like in a sound manner. Further, by using the backup material 10 as a conductive metal, the electrical performance of the electrode composed of the bent portions 4 is significantly improved.

【００４８】図８は上記突曲部４の曲げ込み側に形成さ
れた凹所９に導電金属から成るバックアップ材１０を充
填する方法を示している。FIG. 8 shows a method of filling the concave portion 9 formed on the bent side of the protruding portion 4 with the backup material 10 made of a conductive metal.

【００４９】図示のように、図１Ａに示す絶縁シート１
の一方表面側に存する導電箔２又は導電路２′の外表面
に導電ペースト１０′を点状に盛り上げ、この導電ペー
スト１０′に加圧盤１８によりプレスを与えることによ
り、導電ペースト１０′は導電箔２の局部又は導電路
２′の局部を絶縁シート１内へ曲げ込みつつ同シート１
内へ押し込まれる。As shown, the insulating sheet 1 shown in FIG.
The conductive paste 10 ′ is raised on the outer surface of the conductive foil 2 or the conductive path 2 ′ on one surface of the conductive paste 2 in a dot-like manner, and the conductive paste 10 ′ is pressed by a pressing plate 18 so that the conductive paste 10 ′ becomes conductive. While bending a local portion of the foil 2 or a local portion of the conductive path 2 ′ into the insulating sheet 1,
It is pushed inside.

【００５０】この結果、図７、図８に示すように、突曲
部４の曲げ込み側に形成された凹所９内に導電ペースト
１０′から成るバックアップ材１０が緊密に充填され
る。この時図８Ａに示すように、絶縁シート１に図１Ａ
に示す導電ペースト３を埋め込んでおけば、突曲部４の
頂部４ａは導電ペースト１０′と一緒に導電ペースト３
内へ突入され、図３Ａ、Ｂに示す頂部４ａと導電ペース
ト３との健全な接続が果せ、且つ充分なランド径Ｒを持
ったランド面５を有する電極を適正に確保できる。これ
は図８Ａ、Ｂに示す方法で、図５に示す形状の突曲部４
を形成してランド面５を形成する場合も同様である。As a result, as shown in FIGS. 7 and 8, the backup material 10 made of the conductive paste 10 'is tightly filled in the recess 9 formed on the bent side of the protruding portion 4. At this time, as shown in FIG.
When the conductive paste 3 shown in FIG. 3 is embedded, the top 4a of the bent portion 4 is formed together with the conductive paste 10 '.
3A and 3B, a sound connection between the top portion 4a and the conductive paste 3 can be achieved, and an electrode having a land surface 5 having a sufficient land diameter R can be properly secured. This is a method shown in FIGS.
The same applies to the case where the land surface 5 is formed by forming

【００５１】次に図９は上記配線基板を複層配線基板で
形成した例を示している。予じめ絶縁シート１ｂを用い
図８Ｂに示すような片面配線板を作製し、その導電路２
ｂ′側に絶縁シート１ａ及び導電箔２ａを配して貼り合
せた後、導電箔２ａに上述と同様な方法で突曲部４′を
形成する。そして導電箔２ａをエッチング等により導電
路２ａ′を形成する。突曲部４″に充填された導電ペー
スト１０′が上層の突曲部４′との接続に有効に働き複
層配線板を容易に形成できる。Next, FIG. 9 shows an example in which the wiring board is formed of a multilayer wiring board. Using the insulating sheet 1b, a single-sided wiring board as shown in FIG.
After arranging and bonding the insulating sheet 1a and the conductive foil 2a on the b 'side, a bent portion 4' is formed on the conductive foil 2a in the same manner as described above. Then, a conductive path 2a 'is formed in the conductive foil 2a by etching or the like. The conductive paste 10 'filled in the bent portion 4 "effectively works for connection with the upper bent portion 4', so that a multilayer wiring board can be easily formed.

【００５２】或いは一方表面に導電路２ａ′，２ｂ′を
有する絶縁シート１ａ，１ｂを複層に重ね、この絶縁シ
ート１ａ，１ｂの重ね合せ体を加熱しながら、プレスを
与えて上層の導電路２ａ′を同上層の絶縁シート１ａ内
へ曲げ込んで突曲部４′を形成し、同時にこの上層の突
曲部４′によって下層の導電路２ｂ′を同下層の絶縁シ
ート１ｂ内へ曲げ込んで突曲部４″を形成する。Alternatively, insulating sheets 1a and 1b having conductive paths 2a 'and 2b' on one surface are laminated in a plurality of layers, and the laminated conductive sheets 1a and 1b are pressed while being heated to give an upper conductive path. 2a 'is bent into the upper insulating sheet 1a to form a bent portion 4', and at the same time, the lower conductive path 2b 'is bent into the lower insulating sheet 1b by the upper bent portion 4'. To form a projection 4 ".

【００５３】この時下層の導電路２ｂ′の外表面に図８
に示す如き導電ペースト１０′を盛り上げて置き、その
上で上記プレスを与えることにより、突曲部４″の凹所
内に該導電ペースト１０′が充填され、この導電ペース
ト１０′を介して突曲部４′，４″相互が接続される。At this time, the outer surface of the lower conductive path 2b '
The conductive paste 10 'as shown in (1) is raised and placed thereon, and the above-mentioned press is applied thereon, so that the recess of the bent portion 4 "is filled with the conductive paste 10', and the bent portion is formed via the conductive paste 10 '. The parts 4 ', 4 "are connected to each other.

【００５４】上記図５乃至図９で説明した電極構造を持
つ配線基板を図４に示すインターポーザ基板として用い
て前記接点変換構造を持つＩＣパッケージを形成するこ
とができることは前記の通りである。As described above, the IC package having the contact conversion structure can be formed by using the wiring substrate having the electrode structure described in FIGS. 5 to 9 as the interposer substrate shown in FIG.

【００５５】[0055]

【発明の効果】上記配線基板においては導電路を同配線
基板の一方表面側から他方表面側に単に曲げ込んで、そ
の頂部に電極を形成する極めて簡単な方法で電極形成が
可能であり、突出部を微小径に曲げ込むことが可能であ
るから、導電路の微小ピッチ化をも容易に達成でき、Ｉ
Ｃの接点の微小ピッチ化に有効に対処できる。又、コス
ト的に安価になる。According to the above-mentioned wiring board, it is possible to form an electrode by an extremely simple method of simply bending a conductive path from one surface side to the other surface side of the wiring board and forming an electrode on the top. Since the portion can be bent to a minute diameter, the pitch of the conductive path can be easily reduced to a small value.
It is possible to effectively cope with the minute pitch of the C contact. Further, the cost is reduced.

【００５６】又上記突曲部の頂部には突曲部の曲げ込み
時に所要の面積を持つ平坦な頂面を容易に与えることが
でき、これにより電極のランド径を充分に確保できる。Further, a flat top surface having a required area can be easily provided at the top of the bent portion when the bent portion is bent, whereby a sufficient land diameter of the electrode can be secured.

【００５７】又上記凹所内に充填されたバックアップ材
により上記比較的剛性に欠ける突曲部を補強して健全な
る電極を形成し、ＩＣの外部端子との接続の信頼性を向
上できる。よって本発明は図４に示した如き接点変換構
造を持つＩＣパッケージのインターポーザ基板として好
適に用いられる。Further, the backing material filled in the recesses reinforces the relatively inflexible projections to form a sound electrode, thereby improving the reliability of connection with the external terminals of the IC. Therefore, the present invention is suitably used as an interposer substrate of an IC package having a contact conversion structure as shown in FIG.

【００５８】又本発明により得られたフレキシブルな配
線板をリジット配線基板にその電極を介して接合すれば
容易にリジット・フレキシブル複合配線板を得ることが
できる。If the flexible wiring board obtained according to the present invention is bonded to a rigid wiring board via its electrodes, a rigid-flexible composite wiring board can be easily obtained.

【図面の簡単な説明】[Brief description of the drawings]

【図１】Ａ，Ｂは配線基板に突曲部を形成し、該突曲部
にて電極構造を組成する一例を製造工程を以って示す断
面図。FIGS. 1A and 1B are cross-sectional views illustrating an example of forming a bent portion on a wiring board and forming an electrode structure at the bent portion through a manufacturing process.

【図２】上記図１の配線基板において突曲部にメッキ層
を付設して電極を組成した例を示す断面図。FIG. 2 is a cross-sectional view showing an example in which a plating layer is attached to a protruding portion in the wiring board of FIG. 1 to form an electrode.

【図３】Ａは図１、図２における突曲部と導電ペースト
によって組成される電極のランド径を示す拡大断面図、
Ｂは図１、図２における突曲部と導電ペーストの接続構
造を模視的に示す拡大断面図。FIG. 3A is an enlarged sectional view showing a land diameter of an electrode composed of a protruding portion and a conductive paste in FIGS. 1 and 2,
FIG. 3B is an enlarged cross-sectional view schematically showing a connection structure between the bent portion and the conductive paste in FIGS. 1 and 2.

【図４】上記配線基板をインターポーザ基板として用
い、これをＩＣに貼り合せて形成した接点変換構造、並
びに該接点変換構造を持つＩＣパッケージの断面図。FIG. 4 is a cross-sectional view of a contact conversion structure formed by bonding the above wiring substrate as an interposer substrate to an IC and an IC package having the contact conversion structure.

【図５】Ａは上記突曲部によって形成される電極構造の
他例を示す配線基板の拡大断面図、Ｂは同拡大平面図。FIG. 5A is an enlarged sectional view of a wiring board showing another example of the electrode structure formed by the bent portions, and FIG. 5B is an enlarged plan view of the same.

【図６】図５の突曲部にメッキ層を付設して電極を組成
する例を示す拡大断面図。FIG. 6 is an enlarged sectional view showing an example in which a plating layer is attached to the protruding portion in FIG. 5 to form an electrode.

【図７】上記図１乃至図６に示す突曲部の凹所内にバッ
クアップ材を充填した例を示す拡大断面図。FIG. 7 is an enlarged sectional view showing an example in which the concave portion of the protruding portion shown in FIGS. 1 to 6 is filled with a backup material.

【図８】Ａ，Ｂは上記図７のバックアップ材により突曲
部を形成しつつ上記凹所内へ充填する例を工程順に示す
拡大断面図。8A and 8B are enlarged cross-sectional views showing an example in which the concave portion is filled into the recess while forming a protruding portion using the backup material of FIG.

【図９】上記配線基板を複層にして上記突曲部を形成す
る例を示す拡大断面図。FIG. 9 is an enlarged cross-sectional view showing an example in which the above-mentioned bent portion is formed by using the above-mentioned wiring board as a multilayer.

【図１０】従来のＩＣパッケージにおける接点変換構造
を示す断面図。FIG. 10 is a cross-sectional view showing a contact conversion structure in a conventional IC package.

【符号の説明】[Explanation of symbols]

１，１ａ，１ｂ 絶縁シート ２，２ａ，２ｂ 導電箔 ２′，２ａ′，２ｂ′ 導電路 ２″ 接続パッド ３，１０′ 導電ペースト ３ａ 金属粒子 ４，４′，４″ 突曲部 ４ａ 頂部 ５ 平坦ランド面 Ｒ ランド径 ６ メッキ層 ９ 凹所 １０ バックアップ材 １１ 半田ペースト １２ ＩＣ １２ａ ＩＣの接点 １３ インターポーザ基板 １５ 接着剤 １６ カバーコート １７ 微細配線 １８ 加圧盤 １９ 突起 ２０ 半田ボール ２１ 密封材 1, 1a, 1b Insulating sheet 2, 2a, 2b Conductive foil 2 ', 2a', 2b 'Conductive path 2 "Connection pad 3, 10' Conductive paste 3a Metal particle 4, 4 ', 4" Projection 4a Top 5 Flat land surface R Land diameter 6 Plating layer 9 Concave part 10 Backup material 11 Solder paste 12 IC 12a IC contact 13 Interposer substrate 15 Adhesive 16 Cover coat 17 Fine wiring 18 Pressing plate 19 Projection 20 Solder ball 21 Sealing material

Claims (7)

(57)【特許請求の範囲】(57) [Claims] 【請求項１】絶縁シートの一方表面に延在せる導電路の
局部を絶縁シートの他方表面へ向け曲げ込んで突曲部を
形成し、該突曲部の頂部に絶縁シートの他方表面に配さ
れる電極を形成したことを特徴とする配線基板の電極構
造。A bent portion is formed by bending a local portion of a conductive path extending on one surface of an insulating sheet toward the other surface of the insulating sheet, and disposed on the other surface of the insulating sheet at the top of the bent portion. An electrode structure of a wiring board, wherein an electrode to be formed is formed. 【請求項２】上記絶縁シートが液晶ポリマー材から成る
ことを特徴とする請求項１記載の配線基板の電極構造。2. The electrode structure for a wiring board according to claim 1, wherein said insulating sheet is made of a liquid crystal polymer material. 【請求項３】上記突曲部の頂部を絶縁シートの他方表面
に露出させて上記電極を形成したことを特徴とする請求
項１又は２記載の配線基板の電極構造。3. The electrode structure for a wiring board according to claim 1, wherein the electrode is formed by exposing a top portion of the protruding portion to the other surface of the insulating sheet. 【請求項４】上記絶縁シートの他方表面には上記突曲部
と対応する位置に導電ペーストが点状に埋め込まれてお
り、該導電ペーストは上記埋め込み部において突曲部の
頂部に接合され、加えて該導電ペーストは上記絶縁シー
トの他方表面において平坦なランド面を形成し、該平坦
ランド面が上記電極を組成していることを特徴とする請
求項１又は２記載の配線基板の電極構造。4. A conductive paste is buried in the other surface of the insulating sheet at a position corresponding to the bent portion, and the conductive paste is joined to a top of the bent portion at the buried portion. 3. The electrode structure according to claim 1, wherein the conductive paste forms a flat land surface on the other surface of the insulating sheet, and the flat land surface composes the electrode. . 【請求項５】上記導電ペーストの平坦ランド面にメッキ
層を施して上記電極を組成していることを特徴とする請
求項４記載の配線基板の電極構造。5. The electrode structure of a wiring board according to claim 4, wherein a plating layer is applied to a flat land surface of said conductive paste to form said electrode. 【請求項６】上記突曲部の曲げ込み側に形成された凹所
内にバックアップ材を充填したことを特徴とする請求項
１又は２又は３又は４又は５記載の配線基板の電極構
造。6. The electrode structure for a wiring board according to claim 1, wherein a backup material is filled in a recess formed on the bent side of the protruding portion. 【請求項７】上記バックアップ材が絶縁材又は導電金属
材から成ることを特徴とする請求項６記載の配線基板の
電極構造。7. The electrode structure of a wiring board according to claim 6, wherein said backup material is made of an insulating material or a conductive metal material.
JP9369556A 1997-12-27 1997-12-27 Wiring board electrode structure Expired - Fee Related JP2954559B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9369556A JP2954559B2 (en) 1997-12-27 1997-12-27 Wiring board electrode structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9369556A JP2954559B2 (en) 1997-12-27 1997-12-27 Wiring board electrode structure

Publications (2)

Publication Number Publication Date
JPH11195673A JPH11195673A (en) 1999-07-21
JP2954559B2 true JP2954559B2 (en) 1999-09-27

Family

ID=18494730

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9369556A Expired - Fee Related JP2954559B2 (en) 1997-12-27 1997-12-27 Wiring board electrode structure

Country Status (1)

Country Link
JP (1) JP2954559B2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100580329B1 (en) * 2004-06-25 2006-05-16 삼성전자주식회사 circuit film with bump, film package using the same, and related fabrication method
US8866296B2 (en) 2009-06-24 2014-10-21 Aoi Electronics Co., Ltd. Semiconductor device comprising thin-film terminal with deformed portion

Also Published As

Publication number Publication date
JPH11195673A (en) 1999-07-21

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