JPH1041693A - Mounting structure for semiconductor package - Google Patents
Mounting structure for semiconductor packageInfo
- Publication number
- JPH1041693A JPH1041693A JP19315596A JP19315596A JPH1041693A JP H1041693 A JPH1041693 A JP H1041693A JP 19315596 A JP19315596 A JP 19315596A JP 19315596 A JP19315596 A JP 19315596A JP H1041693 A JPH1041693 A JP H1041693A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor package
- printed wiring
- wiring board
- connection
- contact portion
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3421—Leaded components
- H05K3/3426—Leaded components characterised by the leads
Landscapes
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体パッケー
ジ、特に、ＱＦＰ（Ｑｕａｄ Ｆｌａｔ Ｐａｃｋａｇ
ｅ）の基板への実装構造に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package, and more particularly, to a QFP (Quad Flat Package).
e) relates to a mounting structure on a substrate.
【０００２】[0002]
【従来の技術】一般に、ＱＦＰをプリント配線板に搭載
する場合には、プリント配線板にＱＦＰリード接続用パ
ッドを設け、半田付けによる接続を行っている。2. Description of the Related Art Generally, when a QFP is mounted on a printed wiring board, a QFP lead connection pad is provided on the printed wiring board, and connection is performed by soldering.
【０００３】[0003]
【発明が解決しようとする課題】しかしながら、機器の
小型化、高密度実装化が進むにつれ、ＱＦＰのリードが
小さくなり、隣接するリードの間隔も狭くなってきてい
ることから、ＱＦＰリードと接続用パッドの半田付け接
続作業に高度な技術を必要とするという問題が生じてき
た。However, as the miniaturization and high-density mounting of devices have progressed, the QFP leads have become smaller and the distance between adjacent leads has also become smaller. A problem has arisen that a high technique is required for the soldering connection operation of the pad.
【０００４】また、リード幅、パッド幅の縮小化によ
り、接続強度、接続信頼性の低下も懸念される。本発明
は、上記問題点を除去し、リード幅、パッド幅の縮小化
にも十分に対応することができ、接続強度、接続信頼性
の向上を図り得る半導体パッケージの実装構造を提供す
ることを目的とする。[0004] In addition, there is a concern that the connection strength and the connection reliability may be reduced due to the reduction in the lead width and the pad width. An object of the present invention is to provide a semiconductor package mounting structure which can eliminate the above problems, can sufficiently cope with a reduction in lead width and pad width, and can improve connection strength and connection reliability. Aim.
【０００５】[0005]
【課題を解決するための手段】本発明は、上記目的を達
成するために、 （１）半導体パッケージの実装構造において、外側に折
曲される第１の接触部と内側に折曲される第２の接触部
を有するリードとを交互に配置してなる半導体パッケー
ジと、前記第１の接触部と前記第２の接触部に対応する
接続パッドが形成されるプリント配線板を備え、このプ
リント配線板の接続パッドに前記第１の接触部と第２の
接触部をそれぞれ接続し、搭載するようにしたものであ
る。According to the present invention, there is provided a semiconductor package mounting structure comprising: a first contact portion bent outward and a first contact portion bent inward; A semiconductor package in which leads having two contact portions are alternately arranged; and a printed wiring board on which connection pads corresponding to the first contact portion and the second contact portion are formed. The first contact portion and the second contact portion are respectively connected to connection pads of a plate and mounted.
【０００６】したがって、半導体パッケージの隣り合う
リード及び接続パッドが交互に内側、外側、内側、…と
配置されるので、外側同士、内側同士のパッド間隔を広
くすることができ、半導体パッケージをプリント配線板
に搭載するリードの半田接続時には、隣り合うパッド同
士が電気的短絡（ブリッジ）を起こし難くなる。Therefore, adjacent leads and connection pads of the semiconductor package are alternately arranged inside, outside, inside,..., So that the pad spacing between the outside and inside can be widened, and the semiconductor package can be printed wiring. When soldering leads mounted on a board, adjacent pads are less likely to cause an electrical short circuit (bridge).
【０００７】また、外側同士、内側同士のパッド間隔が
広いため、半田接続の作業性の容易化にもつながり、パ
ッド間の配線本数も増加させることができる。 （２）半導体パッケージの実装構造において、外側に折
曲される接触部を有するリードと、底面より突設される
リードピンとを交互に配置してなる半導体パッケージ
と、前記接触部に対応する接続パッドと、前記リードピ
ンに対応する内側スルーホールを備えたプリント配線板
とを設け、前記プリント配線板の接続パッドに前記接触
部を接続し、前記内側スルーホールに前記リードピンを
挿入して接続し、搭載するようにしたものである。Further, since the pad intervals between the outside and the inside are wide, the workability of the solder connection is facilitated, and the number of wirings between the pads can be increased. (2) In a semiconductor package mounting structure, a semiconductor package in which leads having contact portions bent outward and lead pins projecting from the bottom face are alternately arranged, and connection pads corresponding to the contact portions And a printed wiring board having an inner through hole corresponding to the lead pin, connecting the contact portion to a connection pad of the printed wiring board, inserting and connecting the lead pin to the inner through hole, and mounting. It is something to do.
【０００８】このように、半導体パッケージの外側リー
ドの他に内側リードピンを設けているので、多ピン化に
なり、内側リードピンをスルーホールに挿入して半田接
続を行うことにより、フロー時の半導体パッケージのズ
レがなくなり、接続作業の容易化につながり、また、接
続強度も高めることができる。As described above, since the inner lead pins are provided in addition to the outer leads of the semiconductor package, the number of pins is increased. By inserting the inner lead pins into the through holes and performing solder connection, the semiconductor package at the time of flow is manufactured. Is eliminated, which leads to simplification of connection work, and connection strength can be increased.
【０００９】[0009]
【発明の実施の形態】以下、本発明の実施の形態につい
て図面を参照して詳細に説明する。図１は本発明の第１
実施例を示すＱＦＰの実装構造を示す斜視図、図２はそ
の平面図、図３は図２のＡ−Ａ線断面図である。これら
の図において、１はプリント配線板であり、２はそのプ
リント配線板１上に搭載されるＱＦＰ本体、３はＱＦＰ
外側リード、３ＡはそのＱＦＰ外側リード３の外側に折
曲される第１の接触部、４はＱＦＰ内側リード、４Ａは
そのＱＦＰ内側リード４の内側に折曲される第２の接触
部、５はプリント配線板１の接続用外側パッド、６はプ
リント配線板１の接続用内側パッド、７は半田である。Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 shows the first embodiment of the present invention.
FIG. 2 is a perspective view showing a mounting structure of a QFP showing an embodiment, FIG. 2 is a plan view thereof, and FIG. 3 is a sectional view taken along line AA of FIG. In these figures, 1 is a printed wiring board, 2 is a QFP main body mounted on the printed wiring board 1, and 3 is a QFP
The outer lead 3A is a first contact portion bent outside the QFP outer lead 3, 4 is a QFP inner lead, and 4A is a second contact portion bent inside the QFP inner lead 4. Is a connection outer pad of the printed wiring board 1, 6 is a connection inner pad of the printed wiring board 1, and 7 is solder.
【００１０】図１から図３に示すように、ＱＦＰ外側リ
ード３はプリント配線板１の接続用外側パッド５に、Ｑ
ＦＰ内側リード４はプリント配線板１の接続用内側パッ
ド６に半田接続される。このように、ＱＦＰの隣り合う
リード及び接続パッドが交互に内側、外側、内側、…と
配置されているため、ＱＦＰをプリント配線板１に搭載
する半田接続時には、隣り合うパッド同士が電気的短絡
（ブリッジ）を起こし難くなる。As shown in FIGS. 1 to 3, the QFP outer lead 3 is connected to the outer connecting pad 5 of the printed wiring board 1 by the QFP.
The FP inner lead 4 is connected by soldering to the connection inner pad 6 of the printed wiring board 1. As described above, the adjacent leads and connection pads of the QFP are alternately arranged inside, outside, inside,. (Bridge) is less likely to occur.
【００１１】また、外側同士、内側同士のパッド間隔が
広いため、半田接続の作業性の容易化にもつながり、パ
ッド間の配線本数も増加させることができる。次に、本
発明の第２実施例について説明する。図４は本発明の第
２実施例を示すＱＦＰの実装構造を示す斜視図、図５は
その平面図、図６は図５のＡ−Ａ線断面図である。Further, since the pad spacing between the outside and the inside is wide, the workability of the solder connection is facilitated, and the number of wirings between the pads can be increased. Next, a second embodiment of the present invention will be described. FIG. 4 is a perspective view showing a mounting structure of a QFP according to a second embodiment of the present invention, FIG. 5 is a plan view thereof, and FIG. 6 is a sectional view taken along line AA of FIG.
【００１２】これらの図において、１０はプリント配線
板、１１はそのプリント配線板１０に搭載されるＱＦＰ
本体、１２はＱＦＰ外側リード、１２ＡはそのＱＦＰ外
側リード１２の外側に折曲される接触部、１３は内側リ
ードピン、１４はプリント配線板１０の接続用外側パッ
ド、１５は内側スルーホール、１６は半田である。図４
から図６に示すように、ＱＦＰ外側リード１２は、プリ
ント配線板１０の接続用外側パッド１４に、内側リード
ピン１３は、プリント配線板１０の内側スルーホール１
５に半田接続される。In these figures, reference numeral 10 denotes a printed wiring board, and 11 denotes a QFP mounted on the printed wiring board 10.
Main body, 12 is a QFP outer lead, 12A is a contact portion bent outside of the QFP outer lead 12, 13 is an inner lead pin, 14 is an outer pad for connection of the printed wiring board 10, 15 is an inner through hole, 16 is Solder. FIG.
As shown in FIG. 6, the QFP outer lead 12 is connected to the connection outer pad 14 of the printed wiring board 10, and the inner lead pin 13 is connected to the inner through hole 1 of the printed wiring board 10.
5 is soldered.
【００１３】このように、ＱＦＰ外側リード１２の他に
内側リードピン１３を設けているため、多ピン化にな
り、内側リードピン１３を内側スルーホール１５に挿入
して半田接続を行うことにより、フロー時のＱＦＰのズ
レがなくなり、接続作業の容易化につながり、また、接
続強度を高めることができる。なお、上記実施例では、
ＱＦＰについて述べたが、その他の外部リードを有する
半導体パッケージについても適用できることは言うまで
もない。As described above, since the inner lead pins 13 are provided in addition to the QFP outer leads 12, the number of pins is increased. By inserting the inner lead pins 13 into the inner through holes 15 and performing solder connection, the flow rate can be reduced. Of the QFP is eliminated, which leads to simplification of the connection work, and the connection strength can be increased. In the above embodiment,
Although the QFP has been described, it goes without saying that the present invention can be applied to other semiconductor packages having external leads.
【００１４】また、本発明は上記実施例に限定されるも
のではなく、本発明の趣旨に基づいて種々の変形が可能
であり、これらを本発明の範囲から排除するものではな
い。Further, the present invention is not limited to the above-described embodiment, and various modifications are possible based on the gist of the present invention, and these are not excluded from the scope of the present invention.
【００１５】[0015]
【発明の効果】以上、詳細に説明したように、本発明に
よれば、以下のような効果を奏することができる。 （１）請求項１記載の発明によれば、半導体パッケージ
の隣合うリード及び接続パッドが交互に内側、外側、内
側、…と配置されているため、外側同士、内側同士のパ
ッド間隔を広くすることができ、半導体パッケージをプ
リント配線板に搭載するリードの半田接続時には、隣り
合うパッド同士が電気的短絡（ブリッジ）を起こし難く
なる。As described above, according to the present invention, the following effects can be obtained. (1) According to the first aspect of the present invention, the adjacent leads and connection pads of the semiconductor package are alternately arranged inside, outside, inside,..., So that the pad spacing between outside and inside is widened. When soldering leads for mounting a semiconductor package on a printed wiring board, adjacent pads are less likely to cause an electrical short circuit (bridge).
【００１６】また、外側同士、内側同士のパッド間隔が
広いため、半田接続の作業性の容易化にもつながり、パ
ッド間の配線本数も増加させることができる。 （２）請求項２記載の発明によれば、半導体パッケージ
の外側リードの他に内側リードピンを設けているので、
多ピン化になり、内側リードピンをスルーホールに挿入
して半田接続を行うことにより、フロー時の半導体パッ
ケージのズレがなくなり、接続作業の容易化につなが
り、また、接続強度も高めることができる。Further, since the pad spacing between the outside and the inside is wide, the workability of the solder connection is facilitated, and the number of wirings between the pads can be increased. (2) According to the second aspect of the present invention, since the inner lead pins are provided in addition to the outer leads of the semiconductor package,
By increasing the number of pins and inserting the inner lead pins into the through-holes to perform solder connection, the semiconductor package is not displaced during the flow, which facilitates the connection work and increases the connection strength.
【図１】本発明の第１実施例を示すＱＦＰの実装構造を
示す斜視図である。FIG. 1 is a perspective view showing a mounting structure of a QFP according to a first embodiment of the present invention.
【図２】本発明の第１実施例を示すＱＦＰの実装構造を
示す平面図である。FIG. 2 is a plan view showing a mounting structure of the QFP according to the first embodiment of the present invention.
【図３】図２のＡ−Ａ線断面図である。FIG. 3 is a sectional view taken along line AA of FIG. 2;
【図４】本発明の第２実施例を示すＱＦＰの実装構造を
示す斜視図である。FIG. 4 is a perspective view showing a mounting structure of a QFP according to a second embodiment of the present invention.
【図５】本発明の第２実施例を示すＱＦＰの実装構造を
示す平面図である。FIG. 5 is a plan view showing a mounting structure of a QFP according to a second embodiment of the present invention.
【図６】図５のＡ−Ａ線断面図である。FIG. 6 is a sectional view taken along line AA of FIG. 5;
１，１０ プリント配線板 ２，１１ ＱＦＰ本体 ３，１２ ＱＦＰ外側リード ３Ａ 外側に折曲される第１の接触部 ４ ＱＦＰ内側リード ４Ａ 内側に折曲される第２の接触部 ５，１４ 接続用外側パッド ６ 接続用内側パッド ７，１６ 半田 １２Ａ 外側に折曲される接触部 １３ 内側リードピン １５ 内側スルーホール 1,10 Printed wiring board 2,11 QFP main body 3,12 QFP outer lead 3A First contact part bent outward 4 QFP inner lead 4A Second contact part bent inside, 5,14 For connection Outer pad 6 Inner pad for connection 7, 16 Solder 12A Contact portion bent outward 13 Inner lead pin 15 Inner through hole
Claims (2)
側に折曲される第２の接触部を有するリードとを交互に
配置してなる半導体パッケージと、（ｂ）前記第１の接
触部と前記第２の接触部に対応する接続パッドが形成さ
れるプリント配線板を備え、（ｃ）該プリント配線板の
接続パッドに前記第１の接触部と第２の接触部をそれぞ
れ接続し、搭載することを特徴とする半導体パッケージ
の実装構造。1. A semiconductor package in which (a) leads having first contact portions bent outward and lead having second contact portions bent inward are alternately arranged; A printed wiring board on which connection pads corresponding to the first contact part and the second contact part are formed, and (c) the first contact part and the second contact part are provided on connection pads of the printed wiring board. And mounting the semiconductor package.
ードと底面より突設されるリードピンとを交互に配置し
てなる半導体パッケージと、（ｂ）前記接触部に対応す
る接続パッドと前記リードピンに対応する内側スルーホ
ールを備えたプリント配線板とを設け、（ｃ）前記プリ
ント配線板の接続パッドに前記接触部を接続し、前記内
側スルーホールに前記リードピンを挿入して接続し、搭
載することを特徴とする半導体パッケージの実装構造。2. A semiconductor package in which (a) leads having contact portions bent outward and lead pins projecting from a bottom face are alternately arranged, and (b) connection pads corresponding to the contact portions. And a printed wiring board having an inner through-hole corresponding to the lead pin, (c) connecting the contact portion to a connection pad of the printed wiring board, inserting the lead pin into the inner through-hole and connecting. Mounting structure of a semiconductor package characterized by being mounted.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19315596A JPH1041693A (en) | 1996-07-23 | 1996-07-23 | Mounting structure for semiconductor package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19315596A JPH1041693A (en) | 1996-07-23 | 1996-07-23 | Mounting structure for semiconductor package |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH1041693A true JPH1041693A (en) | 1998-02-13 |
Family
ID=16303205
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19315596A Withdrawn JPH1041693A (en) | 1996-07-23 | 1996-07-23 | Mounting structure for semiconductor package |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH1041693A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2024024595A1 (en) * | 2022-07-29 | 2024-02-01 | 株式会社鷺宮製作所 | Signal converting device, and pressure sensor |
-
1996
- 1996-07-23 JP JP19315596A patent/JPH1041693A/en not_active Withdrawn
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2024024595A1 (en) * | 2022-07-29 | 2024-02-01 | 株式会社鷺宮製作所 | Signal converting device, and pressure sensor |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A300 | Withdrawal of application because of no request for examination |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 20031007 |