JPH1032334A - Gate electrode and its forming method - Google Patents
Gate electrode and its forming methodInfo
- Publication number
- JPH1032334A JPH1032334A JP8352537A JP35253796A JPH1032334A JP H1032334 A JPH1032334 A JP H1032334A JP 8352537 A JP8352537 A JP 8352537A JP 35253796 A JP35253796 A JP 35253796A JP H1032334 A JPH1032334 A JP H1032334A
- Authority
- JP
- Japan
- Prior art keywords
- amorphous silicon
- silicon layer
- gate electrode
- insulating film
- tungsten
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims description 14
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 claims abstract description 25
- 229910021342 tungsten silicide Inorganic materials 0.000 claims abstract description 25
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 24
- 239000004065 semiconductor Substances 0.000 claims abstract description 17
- 239000000758 substrate Substances 0.000 claims abstract description 15
- 125000001153 fluoro group Chemical group F* 0.000 claims abstract description 14
- PZPGRFITIJYNEJ-UHFFFAOYSA-N disilane Chemical compound [SiH3][SiH3] PZPGRFITIJYNEJ-UHFFFAOYSA-N 0.000 claims abstract description 8
- 230000035515 penetration Effects 0.000 claims abstract description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 25
- 229920005591 polysilicon Polymers 0.000 claims description 25
- 239000002245 particle Substances 0.000 claims description 9
- 239000000126 substance Substances 0.000 claims description 9
- 238000005229 chemical vapour deposition Methods 0.000 claims description 5
- 229910021332 silicide Inorganic materials 0.000 claims description 3
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 3
- 229910052721 tungsten Inorganic materials 0.000 claims description 2
- 239000010937 tungsten Substances 0.000 claims description 2
- 230000015572 biosynthetic process Effects 0.000 abstract description 2
- 238000009413 insulation Methods 0.000 abstract 4
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 abstract 1
- 230000015556 catabolic process Effects 0.000 abstract 1
- 238000006731 degradation reaction Methods 0.000 abstract 1
- 229910052731 fluorine Inorganic materials 0.000 abstract 1
- 239000011737 fluorine Substances 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 44
- 239000000470 constituent Substances 0.000 description 7
- 238000007740 vapor deposition Methods 0.000 description 3
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000000149 penetrating effect Effects 0.000 description 2
- 239000002344 surface layer Substances 0.000 description 2
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 239000012466 permeate Substances 0.000 description 1
- 238000005240 physical vapour deposition Methods 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
- H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
- H01L21/28052—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a silicide layer formed by the silicidation reaction of silicon with a metal layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
- H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
- H01L29/4933—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a silicide layer contacting the silicon layer, e.g. Polycide gate
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- Manufacturing & Machinery (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Crystallography & Structural Chemistry (AREA)
- Ceramic Engineering (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は半導体装置に使用さ
れるトランジスターのゲート電極に関し、特に、非晶質
シリコン層上にタングステン−シリサイドが積層された
構造を有するゲート電極に関する。The present invention relates to a gate electrode of a transistor used in a semiconductor device, and more particularly to a gate electrode having a structure in which tungsten-silicide is laminated on an amorphous silicon layer.
【０００２】[0002]
【従来の技術】一般に、ＭＯＳトランジスターにおける
ゲート電極はソース、ドレイン電極の形成に先だって、
ゲート絶縁膜が形成された半導体基板上に形成される。
前記ゲート電極はポリシリコンで形成されており、該特
性の向上のために非晶質のポリシリコンで代替される
か、ポリシリコン上にタングステン−シリサイド層が積
層された構造として形成される。2. Description of the Related Art Generally, a gate electrode of a MOS transistor is formed before forming a source electrode and a drain electrode.
The gate insulating film is formed on the semiconductor substrate.
The gate electrode is formed of polysilicon, and may be replaced with amorphous polysilicon to improve the characteristics, or may be formed as a structure in which a tungsten-silicide layer is stacked on polysilicon.
【０００３】図２は従来の実施例によるものであって、
ポリシリコン層上にタングステン−シリサイドが積層さ
れた構造を有する半導体素子の部分断面図である。図２
を参照すれば、従来のゲート構造は半導体基板１０の表
面にゲート酸化膜（ＳｉＯ2 ）１２が形成されており、
ゲート酸化膜の上部にはポリシリコン層１４及びタング
ステン−シリサイド層１６が順次積層されている。ポリ
シリコンは結晶性を有する物質であって、それは粒界等
によって分離される小さい単結晶性領域（粒度）等で構
成される。蒸着時、ポリシリコン膜等は非晶質や結晶質
であり得るが、蒸着後に高温を受けるようになると、次
後には結晶構造を示す。FIG. 2 shows a conventional embodiment.
FIG. 4 is a partial cross-sectional view of a semiconductor device having a structure in which tungsten-silicide is stacked on a polysilicon layer. FIG.
In the conventional gate structure, a gate oxide film (SiO 2 ) 12 is formed on the surface of a semiconductor substrate 10,
On the gate oxide film, a polysilicon layer 14 and a tungsten-silicide layer 16 are sequentially stacked. Polysilicon is a substance having crystallinity, and is composed of small single crystal regions (grain size) separated by grain boundaries and the like. At the time of vapor deposition, the polysilicon film or the like may be amorphous or crystalline, but when subjected to a high temperature after vapor deposition, it shows a crystalline structure thereafter.
【０００４】ポリシリコン層１４は化学気状蒸着(Chemi
cal Vapor Deposition )法によって主に形成される。こ
の場合、ポリシリコンに対するソースとしてはシラン
（ＳｉＨ4 ）ガスが用いられる。化学気状蒸着法の適用
結果、形成されるポリシリコンの粒度は０．２乃至０．
３μｍの大きさを有する。The polysilicon layer 14 is formed by chemical vapor deposition (Chemi).
cal Vapor Deposition). In this case, a silane (SiH 4 ) gas is used as a source for the polysilicon. As a result of applying the chemical vapor deposition method, the grain size of the formed polysilicon is 0.2 to 0.5.
It has a size of 3 μm.
【０００５】タングステン−シリサイド層１６は、化学
気状蒸着法や物理的蒸着法によって選択的に形成でき得
る。化学気状蒸着法が適用される場合、その上にタング
ステン−シリサイド形成のためのポリシリコン層１４の
対象層を有する半導体基板１０はＷＦ6 ガスを含有する
雰囲気に露出される。この場合、前記ＷＦ6 ガスに含ま
れた小量のフルオロ(fluorine)原子が前記ポリシリコン
層１４の表面層に浸透される。この結果、タングステン
−シリサイド１６には、小量のフルオロ原子が存在する
ようになる。The tungsten-silicide layer 16 can be selectively formed by a chemical vapor deposition method or a physical vapor deposition method. When the chemical vapor deposition method is applied, the semiconductor substrate 10 having the target layer of the polysilicon layer 14 for forming tungsten-silicide thereon is exposed to an atmosphere containing WF 6 gas. In this case, a small amount of fluorine atoms contained in the WF 6 gas permeates the surface layer of the polysilicon layer 14. As a result, the tungsten-silicide 16 has a small amount of fluoro atoms.
【０００６】[0006]
【発明が解決しようとする課題】前記タングステン−シ
リサイド層１６に含まれた前記フルオロ原子は大部分後
続熱処理工程の際、前記ポリシリコン層１４を経由して
前記ゲート酸化膜１２へ浸透するようになる。これは前
記ポリシリコン層１４を構成する構成粒度の大きさが非
常に小さいことによって、前記フルオロ原子の浸透経路
が多く存在することに基づく。その結果、前記ゲート酸
化膜１２の厚さが増加し、且つ前記ゲート酸化膜１２の
電気的特性が著しく低下する。Most of the fluoro atoms contained in the tungsten-silicide layer 16 penetrate into the gate oxide film 12 through the polysilicon layer 14 during a subsequent heat treatment process. Become. This is based on the fact that there is a large number of permeation paths of the fluoro atoms due to the extremely small size of the constituent particles constituting the polysilicon layer 14. As a result, the thickness of the gate oxide film 12 increases, and the electrical characteristics of the gate oxide film 12 significantly decrease.
【０００７】一方、非晶質シリコン上にタングステン−
シリサイドを形成する場合、形成された非晶質シリコン
の粒度はポリシリコンの場合に比べて大きいが、これま
た粒度の大きさが０．５μｍ程度に小さいためタングス
テン−シリサイドの形成時フルオロの浸透が依然として
生じる。On the other hand, tungsten-
When forming silicide, the grain size of the formed amorphous silicon is larger than that of polysilicon, but since the size of the grain size is as small as about 0.5 μm, the penetration of fluoro during the formation of tungsten-silicide is suppressed. Still occurs.
【０００８】従って、本発明の目的は、ゲート電極をポ
リシリコンとタングステン−シリサイドの積層構造を形
成する際、フルオロの浸透によるゲート酸化膜の電気的
特性の低下及び厚さの増加を防止できるゲート電極及び
その形成方法を提供することにある。Accordingly, an object of the present invention is to provide a gate electrode which can prevent a decrease in electrical characteristics and an increase in thickness of a gate oxide film due to permeation of fluoro when forming a laminated structure of polysilicon and tungsten-silicide. An object of the present invention is to provide an electrode and a method for forming the electrode.
【０００９】[0009]
【課題を解決するための手段】前記目的を達成するため
に、本発明は、半導体基板上部に形成されたゲート絶縁
膜と、前記ゲート絶縁膜の上部にジシランガスによって
形成された非晶質シリコン層と前記非晶質シリコン層の
上部に形成され、微量の異物質を含むタングステン−シ
リサイド層を備え、前記非晶質シリコン層は前記異物質
のゲート絶縁膜側への浸透が防止されるほどの粒度の大
きさがあることを特徴とするゲート電極を提供する。本
発明によれば、ゲート電極はゲート酸化膜の上部に非常
に大きい構成粒子を有する非晶質ポリシリコン層を持
つ。前記大きい構成粒子等を有するポリシリコン層は前
記ゲート酸化膜側へ浸透する異物質の経路を最小化す
る。In order to achieve the above object, the present invention provides a gate insulating film formed on a semiconductor substrate and an amorphous silicon layer formed on the gate insulating film by using disilane gas. And a tungsten-silicide layer formed on the amorphous silicon layer and containing a trace amount of a foreign substance, wherein the amorphous silicon layer has such an extent that the foreign substance is prevented from penetrating to the gate insulating film side. Provided is a gate electrode characterized by having a large grain size. According to the present invention, the gate electrode has an amorphous polysilicon layer having very large constituent particles on top of the gate oxide film. The polysilicon layer having the large constituent particles and the like minimizes a path of a foreign substance penetrating into the gate oxide film.
【００１０】[0010]
【発明の実施の形態】以下、本発明の望ましい実施例を
図１を参照して詳細に説明する。図１を参照すれば、半
導体基板２０の上部にゲート絶縁膜２２が形成され、前
記ゲート絶縁膜２２の上部には大きい構成粒子を有する
非晶質シリコン層２４及び微量のフルオロ原子が含まれ
たタングステン−シリサイド層２６が積層されている。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a preferred embodiment of the present invention will be described in detail with reference to FIG. Referring to FIG. 1, a gate insulating layer 22 is formed on a semiconductor substrate 20, and an amorphous silicon layer 24 having large constituent particles and a small amount of fluoro atoms are included on the gate insulating layer 22. A tungsten-silicide layer 26 is stacked.
【００１１】前記非晶質シリコン層２４はジシラン（Ｓ
ｉ2 Ｈ6 ）をソースにした化学気状蒸着法によって形成
されるが、該構成粒度は概ね２乃至３μｍの大きさとし
て、結晶質ポリシリコンが積層された従来の構造に比べ
１０倍程度の大きい粒度を有する。従って、前記非晶質
シリコン層２４は従来のゲート電極に使用されるポリシ
リコン層に比べて前記ゲート絶縁膜２２側への異物質の
浸透経路を少なくとも１／１０程度に減少させることが
できる。その結果、前記ゲート絶縁膜２２の厚さは増加
しないようになり、且つ前記ゲート絶縁膜２２の電気的
特性も大きく低下しない。本発明で適用されたタングス
テン−シリサイドはＷＳｉ2 であることが望ましい。The amorphous silicon layer 24 is made of disilane (S
Although i 2 H 6) is formed by a chemical gaseous deposition method was the source of the configuration granularity is approximately 2 to 3μm as size, the crystalline polysilicon of 10 times compared with the conventional structure that is laminated Has a large particle size. Accordingly, the amorphous silicon layer 24 can reduce the permeation path of the foreign substance to the gate insulating film 22 side at least about 1/10 as compared with the polysilicon layer used for the conventional gate electrode. As a result, the thickness of the gate insulating film 22 does not increase, and the electrical characteristics of the gate insulating film 22 do not significantly decrease. It applied tungsten in the present invention - it is desired silicide is WSi 2.
【００１２】以下、前記構造のゲート電極を形成するた
めの過程を説明する。前記ゲート絶縁膜２４は、前記半
導体基板２０をＯ2 ガスに露出させ酸化（ＳｉＯ2 ）が
前記半導体基板２０の表面から成長されるようにするこ
とによって形成される。Hereinafter, a process for forming the gate electrode having the above structure will be described. The gate insulating film 24 is formed by exposing the semiconductor substrate 20 to O 2 gas so that oxidation (SiO 2 ) is grown from the surface of the semiconductor substrate 20.
【００１３】そして、前記非晶質シリコン層２４は、４
５０乃至５８０℃の温度で前記ゲート絶縁膜２２が形成
された前記半導体基板２０を所定圧力のジシラン（Ｓｉ
2 Ｈ6 ）ガスに露出させることによって、２乃至３μｍ
の大きさの構成粒子を有するように形成される。前記ジ
シランガス反応時圧力は概ね０．１乃至数十Ｔｏｒｒ程
度に設定される。The amorphous silicon layer 24 is composed of 4
The semiconductor substrate 20 on which the gate insulating film 22 is formed is heated at a temperature of 50 to 580 ° C. with disilane (Si
2 to 3 μm by exposure to 2 H 6 ) gas
Is formed so as to have constituent particles of a size. The pressure during the reaction of the disilane gas is set to about 0.1 to several tens Torr.
【００１４】最後に、前記タングステン−シリサイド層
２６は、非晶質シリコン層２４が形成された半導体基板
２０をＷＦ6 ガスに露出させ前記ＷＦ6 ガスに含まれた
タングステン原子が前記液晶質シリコン層２４と反応す
ることによって形成される。前記タングステン−シリサ
イド層２６の形成時、前記ＷＦ6 ガスに含まれた小量の
フルオロ原子２８が前記非晶質シリコン層２４の表面層
に浸透される。この結果、前記タングステン−シリサイ
ド層２６には小量のフルオロ原子が存在するようにな
る。[0014] Finally, the tungsten - silicide layer 26, the tungsten atoms liquid crystalline silicon layer included in the WF 6 gas to expose the semiconductor substrate 20 on which an amorphous silicon layer 24 is formed on the WF 6 gas It is formed by reacting with 24. When the tungsten-silicide layer 26 is formed, a small amount of fluoro atoms 28 contained in the WF 6 gas penetrates into the surface layer of the amorphous silicon layer 24. As a result, the tungsten-silicide layer 26 has a small amount of fluoro atoms.
【００１５】前記タングステン−シリサイド２６に含ま
れた前記フルオロ原子２８は、後続熱処理時、前記非晶
質シリコン層２４を経由して前記ゲート絶縁膜２２側へ
浸透される量が著しく少なくなる。これは前記非晶質シ
リコン層２４を構成する構成粒子が非常に大きくて前記
ゲート絶縁膜２２側への浸透経路が減少したことに起因
する。The amount of the fluoro atoms 28 contained in the tungsten-silicide 26 permeating the gate insulating film 22 through the amorphous silicon layer 24 during the subsequent heat treatment is significantly reduced. This is because the constituent particles constituting the amorphous silicon layer 24 are very large, and the penetration path to the gate insulating film 22 is reduced.
【００１６】その結果、前記ゲート絶縁膜２２の厚さの
増加が最小化され且つ、前記ゲート絶縁膜２２の電気的
特性の低下が最小化される。前記ゲート絶縁膜２２の増
加は５乃至１０Å以下に抑制され従来のゲート電極に比
べて２００％程度改善される。そして前記ゲート絶縁膜
２２の電気的特性も一定な電流を印加した試験結果によ
れば、従来のゲート電極の場合に比べて２００％程度向
上させることができた。As a result, an increase in the thickness of the gate insulating film 22 is minimized, and a decrease in the electrical characteristics of the gate insulating film 22 is minimized. The increase in the gate insulating film 22 is suppressed to 5 to 10 ° or less, which is improved by about 200% as compared with the conventional gate electrode. According to a test result in which a constant current was applied to the electrical characteristics of the gate insulating film 22, the electrical characteristics could be improved by about 200% as compared with the conventional gate electrode.
【００１７】[0017]
【発明の効果】上述したように、本発明はゲート酸化膜
上に結晶質のポリシリコンとタングステン−シリサイド
層が順次積層されたポリサイド構造のゲート電極で、ジ
シランガスと用いて前記結晶質のポリシリコンを非晶質
のシリコンで代替し、その構成粒度のサイズを可能な限
り大きくすることによって、前記タングステン−シリサ
イド層に含まれたフルオロ原子が前記ゲート絶縁膜側へ
浸透することを最小化する。これによって、本発明は前
記ゲート絶縁膜の厚さの増加を最小化でき、また、前記
ゲート絶縁膜の電気的特性の低下を最小化でき得る長所
を提供する。As described above, the present invention relates to a gate electrode having a polycide structure in which crystalline polysilicon and a tungsten-silicide layer are sequentially laminated on a gate oxide film. Is replaced with amorphous silicon, and the size of the constituent grain size is made as large as possible to minimize the penetration of fluoro atoms contained in the tungsten-silicide layer into the gate insulating film side. Accordingly, the present invention provides advantages that an increase in the thickness of the gate insulating layer can be minimized and a decrease in electrical characteristics of the gate insulating layer can be minimized.
【００１８】ここでは、本発明の特定実施例に対して説
明し図示したが、当業者によって、これに対する修正と
変更ができる。従って、特許請求の範囲は本発明の真正
な思想と範囲に属する限り全ての修正と変更を含むもの
と理解できる。Although specific embodiments of the present invention have been described and illustrated herein, modifications and changes may be made by those skilled in the art. It is therefore understood that the appended claims will cover all such modifications and changes as fall within the true spirit and scope of the invention.
【図１】本発明の実施例によるものであって、ポリシリ
コン層上にタングステン−シリサイドが積層された構造
を有するゲート電極の断面図である。FIG. 1 is a cross-sectional view of a gate electrode having a structure in which tungsten-silicide is stacked on a polysilicon layer according to an embodiment of the present invention.
【図２】従来の実施例によるものであって、ポリシリコ
ン層上にタングステン−シリサイドが積層された構造を
有するゲート電極の断面図である。FIG. 2 is a cross-sectional view of a gate electrode having a structure in which tungsten-silicide is stacked on a polysilicon layer according to a conventional example.
１０，２０ 半導体基板 １４ ポリシリコン層 ２２ ゲート電極 ２４ 非晶質シリコン層 １６，２６ タングステン−シリサイド層 ２８ フルオロ原子 10, 20 semiconductor substrate 14 polysilicon layer 22 gate electrode 24 amorphous silicon layer 16, 26 tungsten-silicide layer 28 fluoro atom
Claims (7)
縁膜と、前記ゲート絶縁膜の上部にジシランガスによっ
て形成された非晶質シリコン層と前記非晶質シリコン層
の上部に形成され、微量の異物質を含むタングステン−
シリサイド層を備え、前記非晶質シリコン層は前記異物
質のゲート絶縁膜側への浸透が防止されるほどの粒度の
大きさがあることを特徴とするゲート電極。A gate insulating film formed on a semiconductor substrate; an amorphous silicon layer formed on the gate insulating film by a disilane gas; Tungsten containing substances
A gate electrode comprising a silicide layer, wherein the amorphous silicon layer has a particle size large enough to prevent penetration of the foreign substance into the gate insulating film side.
２乃至３μｍであることを特徴とする請求項１記載のゲ
ート電極。2. The gate electrode according to claim 1, wherein said amorphous silicon layer has a particle size of 2 to 3 μm.
特徴とする請求項１記載のゲート電極。3. The gate electrode according to claim 1, wherein said foreign substance is a fluoro element.
体基板を提供する工程と、 化学気状蒸着用反応器に装着された半導体基板をジシラ
ンガスの雰囲気で熱処理して前記ゲート絶縁膜上に非晶
質シリコン層を形成する工程と、 前記非晶質シリコン層上にタングステン−シリサイドを
形成する工程とを含むことを特徴とするゲート電極形成
方法。4. A process for providing a semiconductor substrate having a gate insulating film formed thereon, and heat treating the semiconductor substrate mounted in a chemical vapor deposition reactor in an atmosphere of disilane gas to form a semiconductor substrate on the gate insulating film. A method of forming a gate electrode, comprising: forming an amorphous silicon layer; and forming tungsten-silicide on the amorphous silicon layer.
のものを特徴とする請求項４記載のゲート電極形成方
法。5. The method of claim 1, wherein said tungsten-silicide is WSi 2.
5. The method for forming a gate electrode according to claim 4, wherein:
ｒｒであることを特徴とする請求項４記載のゲート電極
形成方法。6. The pressure of the reactor is 0.1 to several tens of To.
5. The method according to claim 4, wherein rr is rr.
ンガスが反応する反応器の温度は４５０乃至５８０℃で
あることを特徴とする請求項４記載のゲート電極形成方
法。7. The method according to claim 4, wherein a temperature of a reactor in which the disilane gas reacts to form polysilicon is 450 to 580 ° C.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1995P50441 | 1995-12-15 | ||
| KR1019950050441A KR100203896B1 (en) | 1995-12-15 | 1995-12-15 | Manufacturing method of the gate electrode |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH1032334A true JPH1032334A (en) | 1998-02-03 |
Family
ID=19440439
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8352537A Pending JPH1032334A (en) | 1995-12-15 | 1996-12-16 | Gate electrode and its forming method |
Country Status (5)
| Country | Link |
|---|---|
| JP (1) | JPH1032334A (en) |
| KR (1) | KR100203896B1 (en) |
| CN (1) | CN1172378C (en) |
| DE (1) | DE19652070C2 (en) |
| GB (1) | GB2308233B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100710645B1 (en) * | 2001-05-18 | 2007-04-24 | 매그나칩 반도체 유한회사 | Method for forming the metal line in semiconductor device |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB9802940D0 (en) * | 1998-02-11 | 1998-04-08 | Cbl Ceramics Ltd | Gas sensor |
| CN101572228B (en) * | 2008-04-28 | 2011-03-23 | 中芯国际集成电路制造(北京)有限公司 | Methods for forming polysilicon thin film and gate |
| CN112514031A (en) * | 2018-08-11 | 2021-03-16 | 应用材料公司 | Graphene diffusion barrier |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0459770B1 (en) * | 1990-05-31 | 1995-05-03 | Canon Kabushiki Kaisha | Method for producing a semiconductor device with gate structure |
| JP2901423B2 (en) * | 1992-08-04 | 1999-06-07 | 三菱電機株式会社 | Method for manufacturing field effect transistor |
| US5364803A (en) * | 1993-06-24 | 1994-11-15 | United Microelectronics Corporation | Method of preventing fluorine-induced gate oxide degradation in WSix polycide structure |
| JP2560993B2 (en) * | 1993-09-07 | 1996-12-04 | 日本電気株式会社 | Method for manufacturing compound semiconductor device |
| DE4440857C2 (en) * | 1993-11-16 | 2002-10-24 | Hyundai Electronics Ind | Method of manufacturing a gate electrode of a semiconductor device |
-
1995
- 1995-12-15 KR KR1019950050441A patent/KR100203896B1/en not_active IP Right Cessation
-
1996
- 1996-12-13 DE DE19652070A patent/DE19652070C2/en not_active Expired - Fee Related
- 1996-12-15 CN CNB961214740A patent/CN1172378C/en not_active Expired - Fee Related
- 1996-12-16 JP JP8352537A patent/JPH1032334A/en active Pending
- 1996-12-16 GB GB9626113A patent/GB2308233B/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100710645B1 (en) * | 2001-05-18 | 2007-04-24 | 매그나칩 반도체 유한회사 | Method for forming the metal line in semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| GB2308233B (en) | 2000-11-15 |
| DE19652070C2 (en) | 2003-02-20 |
| DE19652070A1 (en) | 1997-06-19 |
| GB9626113D0 (en) | 1997-02-05 |
| GB2308233A (en) | 1997-06-18 |
| CN1172378C (en) | 2004-10-20 |
| KR100203896B1 (en) | 1999-06-15 |
| KR970053905A (en) | 1997-07-31 |
| CN1155159A (en) | 1997-07-23 |
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