JPH10256300A - Semiconductor device - Google Patents

Semiconductor device

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Publication number
JPH10256300A
JPH10256300A JP9051633A JP5163397A JPH10256300A JP H10256300 A JPH10256300 A JP H10256300A JP 9051633 A JP9051633 A JP 9051633A JP 5163397 A JP5163397 A JP 5163397A JP H10256300 A JPH10256300 A JP H10256300A
Authority
JP
Japan
Prior art keywords
wire bonding
insulating film
bonding electrode
bonding
wire
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP9051633A
Other languages
Japanese (ja)
Other versions
JP2937927B2 (en
Inventor
Tomohiko Inoue
朋彦 井上
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Hiroshima Ltd
Original Assignee
Hiroshima Nippon Denki KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hiroshima Nippon Denki KK filed Critical Hiroshima Nippon Denki KK
Priority to JP9051633A priority Critical patent/JP2937927B2/en
Publication of JPH10256300A publication Critical patent/JPH10256300A/en
Application granted granted Critical
Publication of JP2937927B2 publication Critical patent/JP2937927B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
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    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
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    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
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    • H01L2224/05624—Aluminium [Al] as principal constituent
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4807—Shape of bonding interfaces, e.g. interlocking features
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4845—Details of ball bonds
    • H01L2224/48451—Shape
    • H01L2224/48453—Shape of the interface with the bonding area
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Wire Bonding (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device in which projecting and recessing parts can be formed on the surface of a wire-bonding electrode with a simple method and which has a wire-bonding electrode part which is resistant against a bonding shock by selectively forming element isolating insulating films at the lowermost part of the wire-bonding electrode. SOLUTION: An element isolating insulating films 2a are selectively formed at the lowermost part of a wire-bonding electrode 5. Thus, a semiconductor substrate 1 and an element isolating insulating films 2a, constituted of materials different form the semiconductor substrate 1, constitute the lowermost part. Thus, absorption force for absorbing the bonding shock added at the time of wire bonding becomes large, so that the semiconductor substrate 1 is prevented from being damaged or the occurrence of a crack in the semiconductor substrate 1. Consequently, the semiconductor device in which the projecting and recessing parts can be formed on the surface of the wire-bonding electrode with a simple method and having the wire-bonding electrode part which is resistant against the bonding shock can be provided.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は半導体装置に関し、
特に半導体チップのワイヤボンディング電極部の構造に
関する。The present invention relates to a semiconductor device,
In particular, it relates to the structure of a wire bonding electrode portion of a semiconductor chip.

【０００２】[0002]

【従来の技術】従来、半導体チップの周辺に形成され、
ボンディングワイヤに接続されることになるワイヤボン
ディング電極の表面を凹凸にすることはよく知られてい
る。以下、このような技術について図４を参照して説明
する。ここで、図４は特開平４−３４８０４７号公報に
記載されているところのワイヤボンディング電極部の断
面図である。2. Description of the Related Art Conventionally, a semiconductor chip is formed around a semiconductor chip.
It is well known that the surface of a wire bonding electrode to be connected to a bonding wire is made uneven. Hereinafter, such a technique will be described with reference to FIG. Here, FIG. 4 is a cross-sectional view of the wire bonding electrode portion described in JP-A-4-348047.

【０００３】図において、２１は半導体基板、２２はフ
ィールド酸化膜としての第１の絶縁膜、２３はゲート電
極配線、２４は第１のアルミ電極、２５は層間絶縁膜と
しての第２の絶縁膜、２６は第２のアルミ電極、２７は
パッシベーション膜、２８はボンディングボール、２９
はボンディングワイヤである。ここで、第２のアルミ配
線２６がワイヤボンディング電極となる。In the figure, 21 is a semiconductor substrate, 22 is a first insulating film as a field oxide film, 23 is a gate electrode wiring, 24 is a first aluminum electrode, and 25 is a second insulating film as an interlayer insulating film. , 26 are second aluminum electrodes, 27 is a passivation film, 28 is a bonding ball, 29
Is a bonding wire. Here, the second aluminum wiring 26 becomes a wire bonding electrode.

【０００４】つぎに、このような構造のワイヤボンデイ
ング電極部の形成方法について説明する。先ず、半導体
基板２１の熱酸化等で第１の絶縁膜２２を形成する。次
に、半導体素子である絶縁ゲート電界効果トランジスタ
（以下、ＭＯＳトランジスタと呼称する）のゲート電極
形成と同一の工程で、第１の絶縁膜２２上にゲート電極
配線２３を形成する。Next, a method of forming a wire bonding electrode portion having such a structure will be described. First, the first insulating film 22 is formed by thermal oxidation of the semiconductor substrate 21 or the like. Next, a gate electrode wiring 23 is formed on the first insulating film 22 in the same step as that for forming a gate electrode of an insulated gate field effect transistor (hereinafter, referred to as a MOS transistor) which is a semiconductor element.

【０００５】次に、半導体素子間を結線するためのアル
ミ配線形成工程で、第１のアルミ配線２４を上記ゲート
電極配線２３を被覆するように形成する。そして、配線
間の層間絶縁膜を形成する工程で、開口部を有する第２
の絶縁膜２５を形成する。Next, in an aluminum wiring forming step for connecting the semiconductor elements, a first aluminum wiring 24 is formed so as to cover the gate electrode wiring 23. Then, in the step of forming an interlayer insulating film between the wirings, the second
Is formed.

【０００６】次に、上記第１のアルミ電極２４を被覆す
るように第２のアルミ電極２６を形成する。ここで、上
記のゲート電極配線２３パターンの段差により、第１の
アルミ配線２４および第２のアルミ配線２６表面に凹凸
が形成されることになる。Next, a second aluminum electrode 26 is formed so as to cover the first aluminum electrode 24. Here, unevenness is formed on the surfaces of the first aluminum wiring 24 and the second aluminum wiring 26 due to the step of the pattern of the gate electrode wiring 23 described above.

【０００７】次に、パッシベーション膜２７を形成し、
ワイヤボンデイング電極部を開口する。そして、凹凸を
有する第２のアルミ配線２６にボンディングボール２８
で接続するようになるボンディングワイヤ２９を形成す
る。Next, a passivation film 27 is formed,
Open the wire bonding electrode. Then, a bonding ball 28 is attached to the second aluminum wiring 26 having unevenness.
A bonding wire 29 to be connected is formed.

【０００８】ここで、第２のアルミ配線２６の表面にボ
ンディングワイヤ２９をボンディングボール２８を通し
て接合させる場合、この接合部は従来に比べて広い接触
面積を有するようになる。このために、第２のアルミ配
線２６とボンディングボール２８との接着力は向上する
ようになる。Here, when the bonding wire 29 is bonded to the surface of the second aluminum wiring 26 through the bonding ball 28, the bonding portion has a wider contact area than the conventional one. For this reason, the adhesive force between the second aluminum wiring 26 and the bonding ball 28 is improved.

【０００９】同様にワイヤボンディング電極の表面に凹
凸を形成しボンディングボールとの接着力を向上させる
方法が、特開平４−７４４６号公報あるいは特開平４−
１５２６７８号公報に示されている。ここで、前者では
ワイヤボンディング電極下に形成された配線層の段差で
上記の凹凸が形成されるようになる。なお、この配線層
は平坦な絶縁膜上に形成されるものである。また、後者
では半導体基板表面に形成された凹凸上にワイヤボンデ
イング電極が形成され、その表面が凹凸形状にされよう
になる。Similarly, a method of forming irregularities on the surface of a wire bonding electrode to improve the adhesive force with a bonding ball is disclosed in Japanese Patent Application Laid-Open No. 4-7446 or Japanese Patent Application Laid-Open No.
No. 152678. Here, in the former case, the above-mentioned unevenness is formed at the step of the wiring layer formed below the wire bonding electrode. This wiring layer is formed on a flat insulating film. In the latter case, a wire bonding electrode is formed on the unevenness formed on the surface of the semiconductor substrate, and the surface is made uneven.

【００１０】[0010]

【発明が解決しようとする課題】通常、ワイヤボンデイ
ング電極にボンディングワイヤを圧着して接合させる場
合すなわちワイヤボンディング時には、大きな力がワイ
ヤボンデイング電極部の領域あるいは半導体基板に加わ
るようになる（以下、ボンディングショックと呼称す
る）。Generally, when a bonding wire is crimped and bonded to a wire bonding electrode, that is, at the time of wire bonding, a large force is applied to the region of the wire bonding electrode portion or the semiconductor substrate (hereinafter referred to as bonding). Shock).

【００１１】しかし、上記従来の技術のうち特開平４−
３４８０４７号公報および特開平４−７４４６号公報に
記載されている技術では、ワイヤボンデイング電極部に
おいて、最下層となる第１の絶縁膜表面が完全な平坦面
になっている。このために、上記公開公報に示されてい
る技術では、ワイヤボンディング時に加わるボンディン
グショックを吸収する吸収力が小さく、半導体基板が破
損したり半導体基板にクラックが生じるようになる。However, among the above-mentioned conventional techniques, Japanese Patent Laid-Open No.
In the technology described in Japanese Patent Application Laid-Open No. 348047 and Japanese Patent Application Laid-Open No. H4-7446, the surface of the first insulating film which is the lowermost layer in the wire bonding electrode portion is a completely flat surface. For this reason, in the technique disclosed in the above-mentioned publication, the absorbing power for absorbing the bonding shock applied at the time of wire bonding is small, and the semiconductor substrate is damaged or the semiconductor substrate is cracked.

【００１２】また、特開平４−１５２６７８号公報に記
載されている技術では、半導体基板表面を凹凸形状にす
るために、予め半導体基板をエッチングすることが必要
になる。このために、この従来の技術の場合では、半導
体装置の製造工程が増加しその製造コストが上昇するよ
うになる。In the technique described in Japanese Patent Application Laid-Open No. 4-152678, it is necessary to etch the semiconductor substrate in advance in order to make the surface of the semiconductor substrate uneven. For this reason, in the case of this conventional technique, the number of manufacturing steps of the semiconductor device increases, and the manufacturing cost increases.

【００１３】本発明の目的は、簡便な方法でワイヤボン
デイング電極の表面に凹凸を形成すると共に、ボンディ
ングショックに強いワイヤボンディング電極部を有する
半導体装置を提供することにある。SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor device having a wire bonding electrode portion which is not only capable of forming irregularities on the surface of a wire bonding electrode by a simple method but also resistant to bonding shock.

【００１４】[0014]

【課題を解決するための手段】このために、本発明の半
導体装置では、半導体基板上に形成された絶縁膜層と、
ゲート電極配線層と、前記絶縁膜層およびゲート電極配
線層を被覆する層間絶縁膜上に形成されたワイヤボンデ
ィング電極とを備えた半導体装置において、半導体基板
表面に選択的に形成された凸状の素子分離絶縁膜と前記
素子分離絶縁膜の凸状部に形成されたゲート電極配線層
とが前記ワイヤボンディング電極直下に配置される。For this purpose, in a semiconductor device according to the present invention, an insulating film layer formed on a semiconductor substrate;
In a semiconductor device including a gate electrode wiring layer and a wire bonding electrode formed on an interlayer insulating film covering the insulating film layer and the gate electrode wiring layer, a convex shape selectively formed on a surface of the semiconductor substrate. An element isolation insulating film and a gate electrode wiring layer formed on a convex portion of the element isolation insulating film are disposed immediately below the wire bonding electrode.

【００１５】ここで、前記ゲート電極配線層とワイヤボ
ンディング電極との間には、層間絶縁膜を介して互いに
絶縁されるアルミ配線層がパターニングされて形成され
ている。Here, between the gate electrode wiring layer and the wire bonding electrode, an aluminum wiring layer insulated from each other via an interlayer insulating film is formed by patterning.

【００１６】あるいは、前記層間絶縁膜とワイヤボンデ
ィング電極との間には、前記層間絶縁膜およびワイヤボ
ンディング電極との接着力の大きな金属材料が介在する
ように形成されている。Alternatively, a metal material having a large adhesive force with the interlayer insulating film and the wire bonding electrode is formed between the interlayer insulating film and the wire bonding electrode.

【００１７】ここで、前記ワイヤボンディング電極はア
ルミ配線層で構成されている。あるいは、前記金属材料
はタングステンシリサイドで構成されている。Here, the wire bonding electrode is formed of an aluminum wiring layer. Alternatively, the metal material is made of tungsten silicide.

【００１８】[0018]

【発明の実施の形態】次に、本発明の第１の実施の形態
を図１および図２に基づいて説明する。図１は本発明の
ワイヤボンディング電極部の平面図と断面図である。図
１（ｂ）は図１（ａ）に記したＡ−Ｂで切断した断面図
となっている。また、同様に図２は別のワイヤボンディ
ング電極部の断面図である。ここで、図１は半導体装置
の配線層が１層で形成される場合であり、図２は２層で
形成される場合を示す。DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, a first embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a plan view and a sectional view of a wire bonding electrode portion of the present invention. FIG. 1B is a cross-sectional view taken along a line AB shown in FIG. FIG. 2 is a sectional view of another wire bonding electrode portion. Here, FIG. 1 shows a case where the wiring layer of the semiconductor device is formed with one layer, and FIG. 2 shows a case where the wiring layer is formed with two layers.

【００１９】図１において、１は半導体基板、２および
２ａは素子分離絶縁膜、３はゲート電極配線、４は第１
の層間絶縁膜、５はワイヤボンディング電極、６はパッ
シベーション膜、７はボンディングボール、８はボンデ
ィングワイヤである。In FIG. 1, 1 is a semiconductor substrate, 2 and 2a are element isolation insulating films, 3 is a gate electrode wiring, and 4 is a first
5 is a wire bonding electrode, 6 is a passivation film, 7 is a bonding ball, and 8 is a bonding wire.

【００２０】ここで、図１（ａ）に示すように、素子分
離絶縁膜２ａは格子状に形成されるとともに、図１
（ｂ）に示しように、半導体基板１の表面から出っ張る
ように形成される。Here, as shown in FIG. 1A, the element isolation insulating film 2a is formed in a lattice shape, and
As shown in (b), the semiconductor device is formed so as to project from the surface of the semiconductor substrate 1.

【００２１】以下、このような構造のワイヤボンデイン
グ電極部の形成方法について説明する。Hereinafter, a method of forming the wire bonding electrode portion having such a structure will be described.

【００２２】先ず、半導体基板１の表面部に選択的に素
子分離絶縁膜２および２ａを形成する。ここで、この素
子分離絶縁膜２および２ａは、半導体基板１表面の選択
的な熱酸化で形成される。例えばＬＯＣＯＳ（Ｌｏｃａ
ｌ Ｏｘｉｄａｔｉｏｎ ｏｆ Ｓｉｌｉｃｏｎ）法で
形成される。このために素子分離絶縁膜２および２ａの
上部は半導体基板の１の表面から３００ｎｍ程度に出っ
張るように形成される。また、図１（ａ）に示すよう
に、この素子分離絶縁膜２ａのパターンの平面形状は格
子状になるように形成される。First, the element isolation insulating films 2 and 2a are selectively formed on the surface of the semiconductor substrate 1. Here, the element isolation insulating films 2 and 2a are formed by selective thermal oxidation of the surface of the semiconductor substrate 1. For example, LOCOS (Loca
1 Oxidation of Silicon) method. For this purpose, the upper portions of the element isolation insulating films 2 and 2a are formed so as to protrude from the surface of the semiconductor substrate 1 by about 300 nm. Further, as shown in FIG. 1A, the pattern of the element isolation insulating film 2a is formed so as to have a lattice shape in plan view.

【００２３】次に、従来の技術で説明したように、ＣＭ
ＯＳトランジスタのゲート電極形成と同一の工程で、こ
の素子分離絶縁膜２ａ上にゲート電極配線３を形成す
る。このゲート電極配線３も、素子分離絶縁膜２ａと同
様に格子状に形成されることになる。ここで、ゲート電
極配線３の膜厚は３００ｎｍ程度である。Next, as described in the background art, CM
In the same step as the formation of the gate electrode of the OS transistor, the gate electrode wiring 3 is formed on the element isolation insulating film 2a. The gate electrode wiring 3 is also formed in a lattice like the element isolation insulating film 2a. Here, the thickness of the gate electrode wiring 3 is about 300 nm.

【００２４】次に、全体を被覆するように、第１の層間
絶縁膜４が形成する。ここで、この第１の層間絶縁膜４
はステップカバレッジのよい化学気相成長（ＣＶＤ）法
で堆積される。そして、表面が凹凸形状となるワイヤボ
ンディング電極５をこの第１の層間絶縁膜４上に形成す
る。このワイヤボンディング電極５は、半導体素子間を
接続する第１のアルミ配線層の形成と同一工程で形成さ
れ、その膜厚は１μｍ程度である。Next, a first interlayer insulating film 4 is formed so as to cover the whole. Here, the first interlayer insulating film 4
Is deposited by a chemical vapor deposition (CVD) method with good step coverage. Then, a wire bonding electrode 5 having an uneven surface is formed on the first interlayer insulating film 4. This wire bonding electrode 5 is formed in the same step as the formation of the first aluminum wiring layer for connecting the semiconductor elements, and has a thickness of about 1 μm.

【００２５】次に、パッシベーション膜６をＳｉＯＮ膜
等で形成する。そして、ワイヤボンディング電極５上の
領域を開口する。最後に、このワイヤボンディング電極
５表面にボンディングワイヤ７をボンディングボール８
を通して接合させる。Next, a passivation film 6 is formed of a SiON film or the like. Then, an area on the wire bonding electrode 5 is opened. Finally, a bonding wire 7 is placed on the surface of the wire bonding electrode 5 with a bonding ball 8.
Through.

【００２６】この場合には、ワイヤボンディング電極５
の表面の凹凸は、素子分離絶縁膜２ａの出っ張りと、ゲ
ート電極配線３の段差で形成されるようになる。このた
めに特開平４−３４８０４７号公報および特開平４−７
４４６号公報の場合よりボンディングボール８の接合部
はさらに広い接触面積を有するようになる。そして、ワ
イヤボンディング電極５とボンディングボール８との接
着力は向上するようになる。In this case, the wire bonding electrode 5
Is formed by the protrusion of the element isolation insulating film 2 a and the step of the gate electrode wiring 3. For this purpose, Japanese Patent Application Laid-Open Nos.
The joint of the bonding ball 8 has a wider contact area than in the case of Japanese Patent No. 446. Then, the adhesive force between the wire bonding electrode 5 and the bonding ball 8 is improved.

【００２７】次に、半導体素子が２層のアルミ配線層で
結線される場合を説明する。図２において、１は半導体
基板、２および２ａは素子分離絶縁膜、３はゲート電極
配線、４は第１の層間絶縁膜、９は第１のアルミ配線
層、１０は第２の層間絶縁膜、５はワイヤボンディング
電極、６はパッシベーション膜、７はボンディングボー
ル、８はボンディングワイヤである。ここで、ワイヤボ
ンディング電極５は第２のアルミ配線層で構成される。Next, a case where the semiconductor element is connected by two aluminum wiring layers will be described. In FIG. 2, 1 is a semiconductor substrate, 2 and 2a are element isolation insulating films, 3 is a gate electrode wiring, 4 is a first interlayer insulating film, 9 is a first aluminum wiring layer, and 10 is a second interlayer insulating film. Reference numeral 5 denotes a wire bonding electrode, 6 denotes a passivation film, 7 denotes a bonding ball, and 8 denotes a bonding wire. Here, the wire bonding electrode 5 is formed of a second aluminum wiring layer.

【００２８】なお、図２の平面図は図１（ａ）と同一で
ある。すなわち、素子分離絶縁膜２ａおよびゲート電極
配線３は格子状に形成される。The plan view of FIG. 2 is the same as FIG. 1A. That is, the element isolation insulating film 2a and the gate electrode wiring 3 are formed in a lattice shape.

【００２９】このような構造のワイヤボンデイング電極
部の形成方法は、ほぼ図１で説明した方法と同じであ
る。この場合では、２層の配線層が形成される。すなわ
ち、第１の層間絶縁膜４上にパターニングされた第１の
アルミ配線層９が形成される。ここで、この第１のアル
ミ配線層９の膜厚は５００ｎｍ程度に設定される。そし
て、この第１のアルミ配線層９を被覆するように第２の
層間絶縁膜１０が形成される。さらに、この第２の層間
絶縁膜１０上にワイヤボンディング電極５が形成される
ことになる。ここで、ワイヤボンディング電極５は、半
導体素子を接続する第２のアルミ配線層の形成と同一工
程で形成されることになる。その他の形成工程は全く図
１で説明したのと同一である。The method of forming the wire bonding electrode portion having such a structure is substantially the same as the method described with reference to FIG. In this case, two wiring layers are formed. That is, the patterned first aluminum wiring layer 9 is formed on the first interlayer insulating film 4. Here, the thickness of the first aluminum wiring layer 9 is set to about 500 nm. Then, a second interlayer insulating film 10 is formed so as to cover the first aluminum wiring layer 9. Further, the wire bonding electrode 5 is formed on the second interlayer insulating film 10. Here, the wire bonding electrode 5 is formed in the same step as the formation of the second aluminum wiring layer connecting the semiconductor elements. The other forming steps are exactly the same as those described in FIG.

【００３０】この場合には、ワイヤボンディング電極５
の表面の凹凸は、素子分離絶縁膜２ａの出っ張りと、ゲ
ート電極配線３の段差と、第１のアルミ配線層９の段差
とで形成されるようになる。このために図１の場合より
ボンディングボール８の接合部はさらに広い接触面積を
有するようになる。そして、ワイヤボンディング電極５
とボンディングボール８との接着力はさらに向上するよ
うになる。In this case, the wire bonding electrode 5
Is formed by the protrusion of the element isolation insulating film 2 a, the step of the gate electrode wiring 3, and the step of the first aluminum wiring layer 9. Therefore, the bonding portion of the bonding ball 8 has a larger contact area than that in the case of FIG. Then, the wire bonding electrode 5
The bonding strength between the metal and the bonding ball 8 is further improved.

【００３１】上記のような実施の形態では、ワイヤボン
ディング電極５の最下部には素子分離絶縁膜２ａが選択
的に形成される。このようにして、半導体基板１と、半
導体基板１とは異種の材料で構成された素子分離絶縁膜
２ａと、が最下部を構成するようになる。このために、
ワイヤボンディング時に加わるボンディングショックを
吸収する吸収力が大きくなり、半導体基板が破損したり
半導体基板にクラックが生じるようなことは無くなる。In the embodiment described above, the element isolation insulating film 2a is selectively formed at the lowermost part of the wire bonding electrode 5. Thus, the semiconductor substrate 1 and the element isolation insulating film 2a made of a material different from the semiconductor substrate 1 constitute the lowermost portion. For this,
The absorbing power for absorbing the bonding shock applied at the time of wire bonding is increased, so that the semiconductor substrate is not damaged and the semiconductor substrate is not cracked.

【００３２】次に、本発明の第２の実施の形態を図３に
基づいて説明する。図３は、ワイヤボンディング電極部
の別の平面図とその断面図である。ここで、図３（ｂ）
は図３（ａ）に記したＣ−Ｄで切断した断面図となって
いる。なお、図１および図２と同一のものは同一の符号
で示されている。Next, a second embodiment of the present invention will be described with reference to FIG. FIG. 3 is another plan view of the wire bonding electrode portion and a cross-sectional view thereof. Here, FIG.
Is a cross-sectional view cut along CD shown in FIG. 1 and 2 are denoted by the same reference numerals.

【００３３】図３において、１は半導体基板、２および
２ａは素子分離絶縁膜、３はゲート電極配線、４は第１
の層間絶縁膜、１１はＷＳｉ配線層、１０ａは第２の層
間絶縁膜、５はワイヤボンディング電極、６はパッシベ
ーション膜、７はボンディングボール、８はボンディン
グワイヤである。ここで、ＷＳｉ配線層１１とワイヤボ
ンディング電極５とは接着して形成される。In FIG. 3, 1 is a semiconductor substrate, 2 and 2a are element isolation insulating films, 3 is a gate electrode wiring, and 4 is a first
Reference numeral 11 denotes a WSi wiring layer, 10a denotes a second interlayer insulating film, 5 denotes a wire bonding electrode, 6 denotes a passivation film, 7 denotes a bonding ball, and 8 denotes a bonding wire. Here, the WSi wiring layer 11 and the wire bonding electrode 5 are formed by bonding.

【００３４】図３（ａ）に示すように、第１の実施の形
態と同様、素子分離絶縁膜２ａは格子状に形成されると
ともに、図３（ｂ）に示しように、半導体基板１の表面
から出っ張るように形成される。なお、ワイヤボンディ
ング電極５は第１のアルミ配線層あるいは第２のアルミ
配線層で形成される。As shown in FIG. 3A, similarly to the first embodiment, the element isolation insulating films 2a are formed in a lattice shape, and as shown in FIG. It is formed to protrude from the surface. The wire bonding electrode 5 is formed of a first aluminum wiring layer or a second aluminum wiring layer.

【００３５】以下、このような構造のワイヤボンデイン
グ電極部の形成方法について説明する。ここで、図１と
同一のところは簡略される。Hereinafter, a method of forming the wire bonding electrode portion having such a structure will be described. Here, the same parts as those in FIG. 1 are simplified.

【００３６】半導体基板１の表面部に選択的に素子分離
絶縁膜２および２ａを形成する。ここで、素子分離絶縁
膜２および２ａの上部は半導体基板の１の表面から２０
０ｎｍ程度に出っ張るように形成される。また、図３
（ａ）に示すように、この素子分離絶縁膜２ａのパター
ンの平面形状は格子状になるように形成される。Element isolation insulating films 2 and 2a are selectively formed on the surface of semiconductor substrate 1. Here, the upper portions of the element isolation insulating films 2 and 2a are 20 meters away from the surface of the semiconductor substrate 1.
It is formed so as to protrude to about 0 nm. FIG.
As shown in FIG. 2A, the planar shape of the pattern of the element isolation insulating film 2a is formed in a lattice shape.

【００３７】次に、ＣＭＯＳトランジスタのゲート電極
形成と同一の工程で、この素子分離絶縁膜２ａ上にゲー
ト電極配線３を形成する。このゲート電極配線３も、素
子分離絶縁膜２ａと同様に格子状に形成されることにな
る。ここで、ゲート電極配線３の膜厚は４００ｎｍ程度
である。Next, the gate electrode wiring 3 is formed on the element isolation insulating film 2a in the same step as the formation of the gate electrode of the CMOS transistor. The gate electrode wiring 3 is also formed in a lattice like the element isolation insulating film 2a. Here, the thickness of the gate electrode wiring 3 is about 400 nm.

【００３８】次に、全体を被覆するように、第１の層間
絶縁膜４が形成する。そして、表面が凹凸形状となるＷ
Ｓｉ配線層１１をこの第１の層間絶縁膜４上に形成す
る。このＷＳｉ配線層１１は、例えば半導体メモリのビ
ット線の形成と同一工程で形成され、その膜厚は４００
ｎｍ程度である。Next, a first interlayer insulating film 4 is formed so as to cover the whole. Then, W, whose surface has an uneven shape,
An Si wiring layer 11 is formed on the first interlayer insulating film 4. The WSi wiring layer 11 is formed, for example, in the same step as the formation of the bit line of the semiconductor memory,
nm.

【００３９】次に、このＷＳｉ配線層１１に接着するよ
うにワイヤボンディング電極５を形成する。このワイヤ
ボンディング電極５は、半導体素子を接続する第１のア
ルミ配線層あるいは第２のアルミ配線層等で形成され
る。Next, a wire bonding electrode 5 is formed so as to adhere to the WSi wiring layer 11. This wire bonding electrode 5 is formed of a first aluminum wiring layer or a second aluminum wiring layer for connecting a semiconductor element.

【００４０】次に、パッシベーション膜６を形成し、ワ
イヤボンディング電極５上の領域を開口する。そして、
このワイヤボンディング電極５表面にボンディングワイ
ヤ７をボンディングボール８を通して接合させる。Next, a passivation film 6 is formed, and a region on the wire bonding electrode 5 is opened. And
A bonding wire 7 is bonded to the surface of the wire bonding electrode 5 through a bonding ball 8.

【００４１】この場合には、アルミ配線層で構成される
ワイヤボンディング電極５はＷＳｉ配線層１１と接着し
て形成される。このＷＳｉ配線層１１とワイヤボンディ
ング電極５との接着性およびＷＳｉ配線層１１と第１の
層間絶縁膜との接着性は共に非常に高い。このために、
層間絶縁膜上にアルミ配線層を形成する場合より、ワイ
ヤボンディング電極５の接着強度が大幅に向上するよう
になる。In this case, the wire bonding electrode 5 composed of an aluminum wiring layer is formed by bonding to the WSi wiring layer 11. The adhesiveness between the WSi wiring layer 11 and the wire bonding electrode 5 and the adhesiveness between the WSi wiring layer 11 and the first interlayer insulating film are both very high. For this,
The bonding strength of the wire bonding electrode 5 is greatly improved as compared with the case where an aluminum wiring layer is formed on the interlayer insulating film.

【００４２】このために、第２の実施の形態では、ワイ
ヤボンディング時に加わるボンディングショックを吸収
する吸収力がさらに大きくなり、半導体基板が破損した
り半導体基板にクラックが生じるようなことは皆無にな
る。For this reason, in the second embodiment, the absorbing power for absorbing the bonding shock applied at the time of wire bonding is further increased, and the semiconductor substrate is not damaged or the semiconductor substrate is not cracked. .

【００４３】[0043]

【発明の効果】以上に説明したように、本発明の半導体
装置では、ワイヤボンディング電極の最下部に、素子分
離絶縁膜が選択的に形成される。このようにして、半導
体基板と、半導体基板とは異種の材料で構成された素子
分離絶縁膜と、が最下部を構成するようになる。As described above, in the semiconductor device of the present invention, the element isolation insulating film is selectively formed at the lowermost part of the wire bonding electrode. Thus, the semiconductor substrate and the element isolation insulating film made of a material different from the semiconductor substrate constitute the lowermost portion.

【００４４】このために、先述したようにワイヤボンデ
ィング時に加わるボンディングショックを吸収する吸収
力が大きくなり、半導体基板が破損したり半導体基板に
クラックが生じるようなことは無くなる。For this reason, as described above, the absorbing power for absorbing the bonding shock applied at the time of the wire bonding is increased, and the semiconductor substrate is not damaged and the semiconductor substrate is not cracked.

【００４５】また、本発明では、ワイヤボンディング電
極の表面の凹凸は、素子分離絶縁膜出っ張りと、ゲート
電極配線３の段差と、第１のアルミ配線層９の段差等で
形成されるようになる。In the present invention, the irregularities on the surface of the wire bonding electrode are formed by the protrusion of the element isolation insulating film, the step of the gate electrode wiring 3, the step of the first aluminum wiring layer 9, and the like. .

【００４６】このために、ワイヤボンディング電極とボ
ンディングボール接合部の接触面積がより広くなるよう
に形成できる。そして、ワイヤボンディング電極とボン
ディングボールとの接着力がさらに向上するようにな
る。Therefore, the contact area between the wire bonding electrode and the bonding portion of the bonding ball can be increased. Then, the adhesive force between the wire bonding electrode and the bonding ball is further improved.

【００４７】また、ワイヤボンディング電極が接着性の
高い他の配線層と接着して形成される。ここで、他の配
線層は層間絶縁膜との接着性が高い材料が選ばれる。The wire bonding electrode is formed by bonding with another wiring layer having high adhesiveness. Here, a material having high adhesion to the interlayer insulating film is selected for the other wiring layers.

【００４８】このために、層間絶縁膜上にアルミ配線層
を形成する場合より、ワイヤボンディング電極５の接着
強度が大幅に向上するようになる。また、この場合に
は、ワイヤボンディング時に加わるボンディングショッ
クを吸収する吸収力が大きくなり、半導体基板が破損し
たり半導体基板にクラックが生じるようなことは皆無に
なる。For this reason, the bonding strength of the wire bonding electrode 5 is greatly improved as compared with the case where the aluminum wiring layer is formed on the interlayer insulating film. Further, in this case, the absorbing power for absorbing the bonding shock applied at the time of wire bonding is increased, and the semiconductor substrate is not damaged or the semiconductor substrate is not cracked.

【００４９】以上のようにして、簡便な方法でワイヤボ
ンデイング電極の表面に凹凸が形成され、接着力および
ボンディングショックに強いワイヤボンディング電極部
を有する半導体装置が容易に形成できるようになる。As described above, irregularities are formed on the surface of the wire bonding electrode by a simple method, and a semiconductor device having a wire bonding electrode portion resistant to adhesive force and bonding shock can be easily formed.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明の第１の実施の形態を説明するためのワ
イヤボンディング電極部の平面図と断面図である。FIGS. 1A and 1B are a plan view and a cross-sectional view of a wire bonding electrode unit for explaining a first embodiment of the present invention.

【図２】上記実施の形態での別のワイヤボンディング電
極部の断面図である。FIG. 2 is a cross-sectional view of another wire bonding electrode portion in the embodiment.

【図３】本発明の第２の実施の形態を説明するためのワ
イヤボンディング電極部の平面図と断面図である。FIG. 3 is a plan view and a cross-sectional view of a wire bonding electrode unit for explaining a second embodiment of the present invention.

【図４】従来の技術を説明するためのワイヤボンディン
グ電極部の断面図である。FIG. 4 is a cross-sectional view of a wire bonding electrode section for explaining a conventional technique.

【符号の説明】[Explanation of symbols]

１，２１ 半導体基板 ２，２ａ 素子分離絶縁膜 ３，２３ ゲート電極配線 ４ 第１の層間絶縁膜 ５ ワイヤボンディング電極 ６，２７ パッシベーション膜 ７，２９ ボンディングワイヤ ８，２８ ボンディングボール １０，１０ａ 第２の層間絶縁膜 １１ ＷＳｉ配線層 ２２ 第１の絶縁膜 ２４ 第１のアルミ電極 ２５ 第２の絶縁膜 ２６ 第２のアルミ電極 1, 21 semiconductor substrate 2, 2a element isolation insulating film 3, 23 gate electrode wiring 4 first interlayer insulating film 5 wire bonding electrode 6, 27 passivation film 7, 29 bonding wire 8, 28 bonding ball 10, 10a second Interlayer insulating film 11 WSi wiring layer 22 First insulating film 24 First aluminum electrode 25 Second insulating film 26 Second aluminum electrode

Claims (5)

【特許請求の範囲】[Claims] 【請求項１】 半導体基板上に形成された絶縁膜層と、
ゲート電極配線層と、前記絶縁膜層およびゲート電極配
線層を被覆する層間絶縁膜上に形成されたワイヤボンデ
ィング電極とを備えた半導体装置において、前記半導体
基板表面に選択的に形成された凸状の素子分離絶縁膜と
前記素子分離絶縁膜の凸状部に形成されたゲート電極配
線層とが前記ワイヤボンディング電極直下に配置されて
いることを特徴とする半導体装置。An insulating film layer formed on a semiconductor substrate;
In a semiconductor device comprising a gate electrode wiring layer, and a wire bonding electrode formed on an interlayer insulating film covering the insulating film layer and the gate electrode wiring layer, a convex shape selectively formed on a surface of the semiconductor substrate. And a gate electrode wiring layer formed on a convex portion of the element isolation insulating film is disposed immediately below the wire bonding electrode. 【請求項２】 前記ゲート電極配線層とワイヤボンディ
ング電極との間に、層間絶縁膜を介して互いに絶縁され
るアルミ配線層がパターニングされて形成されているこ
とを特徴とする請求項１記載の半導体装置。2. The method according to claim 1, wherein an aluminum wiring layer insulated from each other through an interlayer insulating film is formed between the gate electrode wiring layer and the wire bonding electrode by patterning. Semiconductor device. 【請求項３】 前記層間絶縁膜とワイヤボンディング電
極との間に、前記層間絶縁膜およびワイヤボンディング
電極との接着力の大きな金属材料が介在していることを
特徴とする請求項１または請求項２記載の半導体装置。3. The semiconductor device according to claim 1, wherein a metal material having a large adhesive force with the interlayer insulating film and the wire bonding electrode is interposed between the interlayer insulating film and the wire bonding electrode. 3. The semiconductor device according to 2. 【請求項４】 前記ワイヤボンディング電極がアルミ配
線層で構成されていることを特徴とする請求項１、請求
項２または請求項３記載の半導体装置。4. The semiconductor device according to claim 1, wherein said wire bonding electrode is formed of an aluminum wiring layer. 【請求項５】 前記金属材料がタングステンシリサイド
であることを特徴とする請求項１、請求項２、請求項３
または請求項４記載の半導体装置。5. The method according to claim 1, wherein said metal material is tungsten silicide.
Alternatively, the semiconductor device according to claim 4.
JP9051633A 1997-03-06 1997-03-06 Semiconductor device Expired - Fee Related JP2937927B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9051633A JP2937927B2 (en) 1997-03-06 1997-03-06 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9051633A JP2937927B2 (en) 1997-03-06 1997-03-06 Semiconductor device

Publications (2)

Publication Number Publication Date
JPH10256300A true JPH10256300A (en) 1998-09-25
JP2937927B2 JP2937927B2 (en) 1999-08-23

Family

ID=12892256

Family Applications (1)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2019159189A (en) * 2018-03-15 2019-09-19 住友大阪セメント株式会社 Optical modulator and optical transmission device
JPWO2019049572A1 (en) * 2017-09-05 2019-12-26 富士電機株式会社 Silicon carbide semiconductor device and method of manufacturing silicon carbide semiconductor device

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55163877A (en) * 1979-06-06 1980-12-20 Toshiba Corp Semiconductor integrated circuit device
JPH0476927A (en) * 1990-07-19 1992-03-11 Nec Corp Semiconductor integrated circuit
JPH1022322A (en) * 1996-06-28 1998-01-23 Denso Corp Semiconductor device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55163877A (en) * 1979-06-06 1980-12-20 Toshiba Corp Semiconductor integrated circuit device
JPH0476927A (en) * 1990-07-19 1992-03-11 Nec Corp Semiconductor integrated circuit
JPH1022322A (en) * 1996-06-28 1998-01-23 Denso Corp Semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPWO2019049572A1 (en) * 2017-09-05 2019-12-26 富士電機株式会社 Silicon carbide semiconductor device and method of manufacturing silicon carbide semiconductor device
JP2019159189A (en) * 2018-03-15 2019-09-19 住友大阪セメント株式会社 Optical modulator and optical transmission device

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