JP2964999B2 - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof

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Publication number
JP2964999B2
JP2964999B2 JP9156985A JP15698597A JP2964999B2 JP 2964999 B2 JP2964999 B2 JP 2964999B2 JP 9156985 A JP9156985 A JP 9156985A JP 15698597 A JP15698597 A JP 15698597A JP 2964999 B2 JP2964999 B2 JP 2964999B2
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JP
Japan
Prior art keywords
pad electrode
insulating film
interlayer insulating
metal layer
opening
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP9156985A
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Japanese (ja)
Other versions
JPH118264A (en
Inventor
明 吉開
弘文 堀田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
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Nippon Electric Co Ltd
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Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP9156985A priority Critical patent/JP2964999B2/en
Publication of JPH118264A publication Critical patent/JPH118264A/en
Application granted granted Critical
Publication of JP2964999B2 publication Critical patent/JP2964999B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は、半導体装置に関
し、特に外部との接続に用いるパッド電極の構造及び製
造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a structure and a manufacturing method of a pad electrode used for connection with the outside.

【０００２】[0002]

【従来の技術】従来、この種の半導体装置は図４ａ、ｂ
に示すように、半導体基板１上にＳｉＯ2等の絶縁膜２
が形成され、かつその絶縁膜上にＡｌ等で形成されたパ
ッド電極３が形成されており、さらにそのパッド電極３
の一部を覆うように半導体素子の保護のためのパッシベ
ーション膜４が形成されていた。Conventionally, this type of semiconductor device FIG. 4 a, b
As shown in FIG. 1, an insulating film 2 such as SiO 2 is formed on a semiconductor substrate 1.
Is formed, and a pad electrode 3 made of Al or the like is formed on the insulating film.
A passivation film 4 for protecting a semiconductor element is formed so as to cover a portion of the semiconductor device.

【０００３】また、配線層が多く、かつ各配線層の膜厚
が薄い場合、パッド電極の厚みを確保するため図５のよ
うに最上層の配線層のみでなくその下層の配線層でパッ
ド電極３ａを形成した後、配線層間の絶縁膜２のパッド
電極３ａ上に開口を設け、さらにパッド電極３ｂを形成
後パッシベーション膜４を形成する場合もある。[0003] The wiring layer is large, and when the film thickness of each wiring layer is thin, the pad electrode wiring layer thereunder not only the uppermost wiring layer as in FIG. 5 for ensuring the thickness of the pad electrode After the formation of the passivation film 4a, an opening may be provided on the pad electrode 3a of the insulating film 2 between the wiring layers, and the passivation film 4 may be formed after the formation of the pad electrode 3b.

【０００４】これら従来の半導体装置の製造方法は次の
ようなものである。[0004] The method of manufacturing these conventional semiconductor devices is as follows.

【０００５】まず、回路素子を形成した半導体基板上の
絶縁膜２上にＡｌ等をスパッタ法などにより全面に形成
し、その後フォトリソグラフィー及びエッチング法を用
いて所望の形状の配線層及び電気接続を行うためのパッ
ド電極３を選択的に形成する（図６ａ）。First, Al or the like is formed on the entire surface of an insulating film 2 on a semiconductor substrate on which circuit elements have been formed by a sputtering method or the like, and thereafter, a wiring layer having a desired shape and an electrical connection are formed by photolithography and etching. the pad electrode 3 for performing selectively formed (FIG. 6 a).

【０００６】次いでパッド電極を含む半導体基板上の全
面にシリコンの酸化物または窒化物等のパッシベーショ
ン膜を形成し、さらにパッド電極上のみをパッド電極同
様に選択的にエッチングし開口を設け（図６ｂ）る事に
より形成していた。Next, a passivation film such as silicon oxide or nitride is formed on the entire surface of the semiconductor substrate including the pad electrode, and only the pad electrode is selectively etched similarly to the pad electrode to form an opening (FIG. 6 ). b) formed by

【０００７】また、配線層数が多い場合は上記パッシベ
ーション膜の代わりにＳｉＯ2等の層間絶縁膜２を形成
し、さらにその上部の配線を形成すると同時にパッド電
極３ｂを形成した後（図６ｃ）、さらにパッシベーショ
ン膜を形成する事により形成していた（図６ｄ）。Further, if the number of wiring layers is large to form an interlayer insulating film 2 of SiO 2 or the like instead of the passivation film, after further formed simultaneously pad electrode 3b to form a wiring of the upper (Fig. 6 c ), it was formed by forming a further passivation film (FIG. 6 d).

【０００８】[0008]

【発明が解決しようとする課題】これら半導体装置は、
その後金線等のワイヤを用いたワイヤボンディング法や
フィルムキャリアを用いたＴＡＢボンディング法等によ
り外部と接続される。These semiconductor devices are :
Thereafter, it is connected to the outside by a wire bonding method using a wire such as a gold wire or a TAB bonding method using a film carrier.

【０００９】この各種ボンディングは多くが超音波を併
用した熱圧着法である。Most of these bonding methods are thermocompression bonding methods using ultrasonic waves.

【００１０】例として図７に金線を用いたワイヤボンデ
ィングでの状態を示す。As an example, FIG. 7 shows a state of wire bonding using a gold wire.

【００１１】ワイヤボンディングは管状のキャピラリ５
に金線６ａが通されており、この金線を放電により溶解
させて金ボール６ｂを形成し、加熱及び加圧をしながら
半導体装置上のパッド電極３に圧着を行うが、その際、
キャピラリに超音波振動７を与える事によりパッド電極
３と金ボール６ｂの接合をより安定的に行っている。The wire bonding is performed by using a tubular capillary 5.
Gold wire 6a has passed, the gold wire was dissolved by the discharge to form a gold ball 6b, performs the crimping to the pad electrode 3 on the semiconductor device while heat and pressure, in which the,
By applying the ultrasonic vibration 7 to the capillary, the bonding between the pad electrode 3 and the gold ball 6b is performed more stably.

【００１２】しかし、従来の半導体装置はパッドとボー
ルの接合は行われるものの、図７のように、パッド電極
３とその下層の絶縁膜２との界面が平滑な面であるた
め、ボンディングの際に印加される超音波振動７によっ
て界面で滑りが起こり、パッド電極３と絶縁層２の界面
の密着強度を弱くしてしまい、その界面でのはがれが発
生しやすくなり、初期的にはがれて接続部が電気的にオ
ープンとなるため歩留が低下したり、使用中の温度変化
などによる応力によりはがれが発生し、信頼性を低下さ
せる原因となる。[0012] However, although the conventional semiconductor device bonding pad and the ball takes place, as shown in FIG. 7, for the interface between the pad electrode 3 and the insulating film 2 thereunder is smooth surface, during bonding to the ultrasonic vibration 7 to be marked pressure occurs slippage at the interface, leads to weak adhesion strength at the interface of the pad electrode 3 and the insulating layer 2, becomes peeling tends to occur at the interface, and initially peeling connecting portion or electrically reduced yield for the open, peeling occurs due to stress caused by temperature changes during use, it causes a reduction in the reliability.

【００１３】特に近年の微細加工技術の進歩により配線
幅が狭くまた配線の厚みが薄くなる中で多層配線のため
の層間の絶縁膜の平坦化技術が進んでいるため、ボンデ
ィングの際に印加される超音波振動がパッド電極と絶縁
膜２の界面の密着力を低下させる事が大きな問題となっ
てきている。[0013] In particular, since the wiring width Recent advances in microfabrication technology has progressed planarizing technique of an interlayer insulating film for narrow also multilayer wiring in the thickness of the wiring is reduced, marks pressurized during bonding It is becoming a serious problem that the ultrasonic vibration to be caused lowers the adhesion force at the interface between the pad electrode and the insulating film 2.

【００１４】本発明は上記問題に鑑みてなされたもので
あり、ボンディングの際の超音波振動が印加されてもパ
ッドと絶縁膜の密着力が低下することのないパッド電極
を持つ半導体装置及びその製造方法を提供することを目
的とする。[0014] The present invention has been made in view of the above problems, a semiconductor device and an ultrasonic vibration when the bonding with no pad electrodes be adhesion pads and the insulating film be marked pressure drops It is an object of the present invention to provide a manufacturing method thereof.

【００１５】[0015]

【課題を解決するための手段】前記の目的は以下の手段
によって達成される。The above object is achieved by the following means.

【００１６】すなわち、本発明は、半導体回路素子が形
成されている半導体基板上に外部との接続のためのパッ
ド電極が設けられている半導体装置において、、半導体
素子を形成した半導体基板上に第１のパッド電極が形成
され、該第１のパッド電極を含む半導体基板全面に層間
絶縁膜が形成され、前記第１のパッド電極上部の層間絶
縁膜には選択的に前記第１のパッド電極に達する複数の
開口が形成されており、該開口内に金属層が、該金属層
の上端が開口部上端面より低くなる段差を形成するよう
に埋め込まれ、該金属層及び層間絶縁膜上に第２のパッ
ド電極が形成されていることを特徴とする半導体装置で
あり、前記層間絶縁膜に選択的に形成された複数の開口
の総面積が、前記第２のパッド電極面積の１０％以上で
あり、前記金属層上端と開口部上端面とで形成される段
差が０．０３〜０．３μｍであることを特徴とする半導
体装置を提案するものである。また本発明は、半導体素
子を形成した半導体基板上に第１のパッド電極を形成す
る工程、該第１のパッド電極を含む半導体基板全面に層
間絶縁膜を形成する工程、前記第１のパッド電極上部の
層間絶縁膜に選択的に第１のパッド電極に達する複数の
開口を形成する工程、該開口内に金属層を形成し、金属
層をエッチバックして該金属層の上端が開口部上端面よ
り低くなる段差を形成するように金属層を埋め込む工
程、該金属層及び層間絶縁膜上に第２のパッド電極を形
成する工程とを有することを特徴とする半導体装置の製
造方法を提案するものであり、更に本発明は、上記の半
導体装置の第２のパッド電極上へボンディングを超音波
振動を併用した熱圧着により行うボンディング方法であ
って、印加する超音波振動の方向が、層間絶縁膜の開口
部以外の上面と第２のパッド電極との界面の面方向と一
致していることを特徴とす るボンディング方法を提供す
るものである。 [0016] Namely, the present invention is ,, semiconductor in a semiconductor device where the pad electrode is provided for connection to an external on a semiconductor substrate having a semiconductor circuit element is formed
A first pad electrode is formed on a semiconductor substrate on which an element has been formed.
And an interlayer on the entire surface of the semiconductor substrate including the first pad electrode.
An insulating film is formed, and an interlayer insulation on the first pad electrode is formed.
A plurality of the edge films selectively reach the first pad electrode.
An opening is formed, and a metal layer is formed in the opening.
So that the upper end of the opening is lower than the upper end surface of the opening.
And a second package is formed on the metal layer and the interlayer insulating film.
A semiconductor device, wherein a cathode electrode is formed, selectively formed a plurality of openings in the interlayer insulating film
Is not less than 10% of the area of the second pad electrode.
And a step formed by the upper end surface of the metal layer and the upper end surface of the opening.
Difference Ru der proposes a semiconductor device which is a 0.03 to 0.3 [mu] m. The present invention also relates to a semiconductor device.
Forming a first pad electrode on a semiconductor substrate on which a chip is formed;
Forming a layer on the entire surface of the semiconductor substrate including the first pad electrode.
Forming an inter-insulation film;
A plurality of layers selectively reaching the first pad electrode on the interlayer insulating film
Forming an opening; forming a metal layer in the opening;
Etch back the layer so that the upper end of the metal layer is
Embedding the metal layer to form a lower step
Forming a second pad electrode on the metal layer and the interlayer insulating film.
Manufacturing a semiconductor device, comprising the steps of:
The present invention also proposes a manufacturing method
Ultrasonic bonding on the second pad electrode of the conductor device
This bonding method is performed by thermocompression bonding with vibration.
Therefore, the direction of the ultrasonic vibration to be applied depends on the opening of the interlayer insulating film.
With the surface direction of the interface between the upper surface other than the portion and the second pad electrode.
To provide a bonding method shall be the features that you have match
Things.

【００１７】[0017]

【発明の実施の形態】次に本発明の実施の形態について
図面を参照して説明する。Embodiments of the present invention will now be described with reference to the drawings.

【００１８】図１は本発明の一例を示す平面図及び断面
図である。FIG. 1 is a plan view and a sectional view showing an example of the present invention.

【００１９】本実施例では層間絶縁膜２上に第１のパッ
ド電極３ａが形成され、その第１のパッド電極３ａ上に
形成された層間絶縁膜２にマトリックス状に開口８が形
成されており、かつその開口の内部に金属層９が層間絶
縁膜２よりも低い高さで形成されている。[0019] In this embodiment the first pad <br/> cathode electrode 3a is formed on the interlayer insulating film 2, an opening 8 in a matrix in the interlayer insulating film 2 formed on the first pad electrode 3a Is formed, and the metal layer 9 is separated from the inside of the opening by interlayer insulation.
It is formed at a lower height than the edge membrane 2.

【００２０】この層間絶縁膜２表面と開口８内に形成さ
れている金属層９とにより凹凸が形成され、その凹凸の
さらに上部に第２のパッド電極３ｂ及びパッシベーショ
ン膜４が形成されている。Irregularities are formed by the surface of the interlayer insulating film 2 and the metal layer 9 formed in the opening 8, and a second pad electrode 3b and a passivation film 4 are formed further on the irregularities.

【００２１】図３は上記実施例の半導体装置のワイヤボ
ンディング時における形態を示す断面図である。FIG. 3 is a sectional view showing an embodiment of the semiconductor device of the above embodiment at the time of wire bonding.

【００２２】キャピラリに印加された超音波振動７は、
金ボール６ｂと第２のパッド電極３ｂとの間で両者の変
形に寄与すると共に、さらにその下層の第２のパッド電
極３ｂと層間絶縁膜２の間にも伝達されるが、その界面
が凹凸により一平面上にないため滑りを起こすことがな
い。[0022] The ultrasonic vibration 7, which is marked addition to the capillary,
Together they contribute to deformation of both with the gold ball 6b and the second pad electrode 3b, but further also transmitted during the second underlying pad electrodes 3b and the interlayer insulating film 2, the interface irregularities Because it is not on one plane, it does not slip.

【００２３】従って、このパッド電極３ｂと層間絶縁膜
の間の密着強度を低下させることなくボンディングを行
うことができる。[0023] Accordingly, it is possible to perform the bonding without reducing the adhesion strength between the pad electrode 3b and the interlayer insulating film.

【００２４】本発明の半導体装置は、従来の半導体装置
のパッド電極と層間絶縁膜２との界面が一平面上に存在
し、かつその方向とボンディングの際に印加される超音
波振動の方向とが一致することにより密着性が低下する
ことに着目し、パッド電極と層間絶縁膜の界面が凹凸を
設けることにより一平面ではなくなり、パッド電極と層
間絶縁膜の界面で滑りが起こることを防止するため、パ
ッド電極と層間絶縁膜間の密着力の低下が発生しなくな
り、歩留及び信頼性の高い半導体装置を提供することが
できる。The semiconductor device of the present invention, present at the interface are on one plane of the pad electrode and the interlayer insulating film 2 of a conventional semiconductor device, and the direction of the ultrasonic vibration indicia pressurized during its direction and bonding And that the interface between the pad electrode and the interlayer insulating film has irregularities.
It is no longer a single plane by providing, for preventing the slippage occurs at the interface between the pad electrode and the interlayer insulating film, such reduction in the adhesion between the pad electrode and the interlayer insulating film occurs kuna
Thus , a semiconductor device with high yield and high reliability can be provided.

【００２５】[0025]

【実施例】本発明を実施例により、さらに具体的に説明
する。EXAMPLES The present invention will be described more specifically with reference to examples.

【００２６】実施例１ 図１は本発明の第１の実施例を示す。Embodiment 1 FIG. 1 shows a first embodiment of the present invention.

【００２７】第１の実施例では層間絶縁膜にＳｉＯ2を
使用し、また、開口の大きさは径０．５μｍのものを１
ミクロン間隔で形成して金属層にタングステンを使用し
た。In the first embodiment, SiO 2 is used for the interlayer insulating film, and the size of the opening is 0.5 μm in diameter.
Tungsten was used for the metal layer formed at micron intervals.

【００２８】タングステンと層間絶縁膜との段差は約
０．１μｍに形成し、その上部にさらにパッド電極を形
成している。The step between tungsten and the interlayer insulating film is formed to be about 0.1 μm, and a pad electrode is further formed thereon.

【００２９】その製造方法について図２を参照して説明
する。[0029] will be described with reference to FIG. 2 for the production process.

【００３０】半導体素子形成後の半導体基板にＡｌを全
面に形成しフォトリソグラフィーにより選択的に第１の
パッド電極を形成する（図２ａ）。[0030] to form an Al on a semiconductor substrate after a semiconductor element formed on the entire surface to form a selective first <br/> pad electrodes by photolithography (Fig. 2 a).

【００３１】次に第１のパッド電極を含む半導体基板全
面に層間絶縁膜であるＳｉＯ2をプラズマＣＶＤ法によ
り形成する（図２ｂ）。[0031] Next, SiO 2, which is an interlayer insulating film on the entire surface of the semiconductor substrate is formed by a plasma CVD method comprising a first pad electrode (Fig. 2 b).

【００３２】その後さらにフォトリソグラフィーにより
選択的にパッド上部に開口を設け、さらに開口を含む半
導体基板全面にＣＶＤ法によりタングステン層を形成す
る（図２ｃ）。[0032] After that further selectively opening provided in pad upper by photolithography, further forming a tungsten layer by CVD on the semiconductor substrate over the entire surface including the opening (Fig. 2 c).

【００３３】次いでタングステン層をエッチバックする
事により層間絶縁膜の開口内にタングステンを残す。こ
のときタングステン層が層間絶縁膜上に残らないように
するため、エッチバックをややオーバーさせることで層
間絶縁膜とタングステンの間に約０．１μｍ程度の段
差、即ち、凹凸が形成される（図２ｄ）。Next, the tungsten layer is etched back to leave tungsten in the opening of the interlayer insulating film. At this time so that the tungsten layer does not remain on the interlayer insulating film, the order of about 0.1μm between layers <br/> insulating film and the tungsten thereby somewhat over-etch back step, i.e., uneven is formed (Fig. 2 d).

【００３４】その後さらに第２のパッド電極を下層の第
１のパッド電極と同様の方法にて形成し（図２ｅ）た
後、パッド電極を含む半導体基板全面にＳｉＮ等のパッ
シベーション膜を形成し、第２のパッド電極上部を選択
的にエッチング除去して完成する（図２ｆ）。Thereafter, the second pad electrode is further connected to the lower first layer .
After was formed at the first pad electrode and the same method (Fig. 2 e), a passivation film such as SiN is formed on the entire surface of the semiconductor substrate including the pad electrode, selectively removed by etching the second pad electrode upper to complete Te (Figure 2 f).

【００３５】前述の実施例では金属層と開口の段差を
０．１μｍとしたが０．０３μｍ以上の深さで形成して
も問題はない。ただし、深くするためには層間絶縁膜を
厚くすることになるため０．３μｍ程度までが現実的で
ある。In the above-described embodiment, the step between the metal layer and the opening is 0.1 μm, but there is no problem if the step is formed to a depth of 0.03 μm or more. However, to increase the depth, the thickness of the interlayer insulating film must be increased to about 0.3 μm.

【００３６】また、開口寸法についても径０．５μｍの
円形状としたが、矩形等の形状でもよく、またその数に
ついても開口部の総面積がパッドの面積の１０％以上で
あれば効果が得られる。The size of the opening is 0.5 μm in diameter .
Although a circular shape is used , a rectangular shape or the like may be used, and an effect can be obtained with respect to the number thereof as long as the total area of the openings is 10% or more of the pad area.

【００３７】さらに本実施例では金線を用いたワイヤボ
ンディング法を用いて説明したが、Ａｌ線やＴＡＢを用
いたボンディングであっても、超音波振動を印加するボ
ンディング法であれば同様の効果が得られることはいう
までもない。Furthermore in the present embodiment it has been described with reference to a wire bonding method using a gold wire, but a bonding using Al wire or TAB, similar if bonding method for indicia pressurized ultrasonic vibrations Needless to say, an effect can be obtained.

【００３８】また、前述の実施例では開口を層間絶縁膜
に対し垂直に形成したが、開口の断面形状はテーパー状
であっても効果が得られる。Although the opening is formed perpendicular to the interlayer insulating film in the above-described embodiment, the effect can be obtained even if the cross-sectional shape of the opening is tapered.

【００３９】ただし、この場合開口の深さとテーパーの
角度により効果の大きさに差が生じるため可能な限り角
度は大きくする方がよい。However, in this case, the degree of the effect varies depending on the depth of the opening and the angle of the taper, so that the angle should be as large as possible.

【００４０】[0040]

【発明の効果】第１の効果はボンディングの際に強度の
低下による初期的なボンディング不良が発生しないこと
である。The first effect is that no initial bonding failure occurs due to a decrease in strength during bonding.

【００４１】第２の効果はパッド電極と層間絶縁膜間の
密着強度の低下がないため長期的な使用にも耐えうる信
頼性を確保できることである。The second effect is that since there is no decrease in the adhesion strength between the pad electrode and the interlayer insulating film, it is possible to ensure reliability that can withstand long-term use.

【００４２】その理由はパッド電極と層間絶縁膜の界面
が一平面で構成されず、凹凸を有している構造となって
いるため、ボンディングの際に印加される超音波振動が
パッド電極と層間絶縁膜の界面で滑りを発生させること
がないからである。The reason is that the interface between the pad electrode and the interlayer insulating film
There are not constituted by a plane, because that is the structure which has irregularities, there is no necessity to ultrasonic vibration indicia pressure during bonding to generate slip in the interface of the pad electrode and the interlayer insulating film It is.

【図面の簡単な説明】[Brief description of the drawings]

【図１】図１（ａ）は、本発明の半導体装置の平面図で
あり、図１（ｂ）は図１（ａ）の断面図である。FIG. 1A is a plan view of a semiconductor device of the present invention, and FIG. 1B is a cross-sectional view of FIG. 1A.

【図２】（ａ）〜（ｆ）は本発明の製造工程を示す断面
図である。FIGS. 2A to 2F are cross-sectional views illustrating a manufacturing process of the present invention.

【図３】本発明の半導体装置の形態を示す断面図であ
る。FIG. 3 is a cross-sectional view illustrating an embodiment of a semiconductor device of the present invention.

【図４】（ａ）は、従来の半導体装置の平面図であり、
（ｂ）は（ａ）の断面図である。FIG. 4A is a plan view of a conventional semiconductor device,
(B) is a sectional view of (a).

【図５】（ａ）は、従来の半導体装置の別の例を示す平
面図であり、（ｂ）は（ａ）の断面図である。5A is a plan view showing another example of the conventional semiconductor device, and FIG. 5B is a cross-sectional view of FIG.

【図６】（ａ）〜（ｄ）は従来の製造工程を示す断面図
である。FIGS. 6A to 6D are cross-sectional views showing a conventional manufacturing process.

【図７】従来の半導体装置の問題点を示す断面図であ
る。FIG. 7 is a cross-sectional view showing a problem of a conventional semiconductor device.

【符号の説明】[Explanation of symbols]

１ 半導体基板 ２ 層間絶縁膜 ３ａ 第１のパッド電極 ３ｂ 第２のパッド電極 ４ パッシベーション膜 ５ キャピラリ ６ａ 金線 ６ｂ 金ボール ７ 超音波振動 ８ 開口 ９ 金属層Reference Signs List 1 semiconductor substrate 2 interlayer insulating film 3a first pad electrode 3b second pad electrode 4 passivation film 5 capillary 6a gold wire 6b gold ball 7 ultrasonic vibration 8 opening 9 metal layer

Claims (5)

(57)【特許請求の範囲】(57) [Claims] 【請求項１】 半導体回路素子が形成されている半導体
基板上に外部との接続のためのパッド電極が設けられて
いる半導体装置において、半導体素子を形成した半導体
基板上に第１のパッド電極が形成され、該第１のパッド
電極を含む半導体基板全面に層間絶縁膜が形成され、前
記第１のパッド電極上部の層間絶縁膜には選択的に前記
第１のパッド電極に達する複数の開口が形成されてお
り、該開口内に金属層が、該金属層の上端が開口部上端
面より低くなる段差を形成するように埋め込まれ、該金
属層及び層間絶縁膜上に第２のパッド電極が形成されて
いることを特徴とする半導体装置。1. A semiconductor device where the pad electrode is provided for the connection of an external and on a semiconductor substrate having a semiconductor circuit element is formed, the semiconductor forming the semiconductor element
A first pad electrode is formed on a substrate, and the first pad electrode is formed on the substrate.
An interlayer insulating film is formed on the entire surface of the semiconductor substrate including the electrodes.
The interlayer insulating film above the first pad electrode is selectively
A plurality of openings reaching the first pad electrode are formed.
A metal layer in the opening, and an upper end of the metal layer is an upper end of the opening.
The gold is embedded so as to form a step lower than the surface.
A second pad electrode is formed on the metal layer and the interlayer insulating film;
Wherein a it is. 【請求項２】 前記層間絶縁膜に選択的に形成された複
数の開口の総面積が、前記第２のパッド電極面積の１０
％以上であり、前記金属層上端と開口部上端面とで形成
される段差が０．０３〜０．３μｍであることを特徴と
する請求項１に記載の半導体装置。2. A multi-layer structure selectively formed on the interlayer insulating film.
The total area of the openings is 10% of the area of the second pad electrode.
% Or more, formed by the upper end of the metal layer and the upper end of the opening.
Characterized in that the step is 0.03 to 0.3 μm.
The semiconductor device according to claim 1. 【請求項３】 半導体素子を形成した半導体基板上に第
１のパッド電極を形成する工程、該第１のパッド電極を
含む半導体基板全面に層間絶縁膜を形成する工程、前記
第１のパッド電極上部の層間絶縁膜に選択的に第１のパ
ッド電極に達する複数の開口を形成する工程、該開口内
に金属層を形成し、金属層をエッチバックして該金属層
の上端が開口部上端面より低くなる段差を形成するよう
に金属層を埋め込む工程、該金属層及び層間絶縁膜上に
第２のパッド電極を形成する工程とを有することを特徴
とする半導体装置の製造方法。3. A semiconductor device having a semiconductor element formed thereon, wherein a semiconductor element is formed on the semiconductor substrate.
Forming one pad electrode, and forming the first pad electrode
Forming an interlayer insulating film over the entire surface of the semiconductor substrate, including:
The first pad is selectively formed on the interlayer insulating film above the first pad electrode.
Forming a plurality of openings reaching the pad electrode;
A metal layer is formed on the metal layer, and the metal layer is etched back.
So that the upper end of the opening is lower than the upper end surface of the opening.
Embedding a metal layer on the metal layer and the interlayer insulating film
Forming a second pad electrode.
Manufacturing method of a semiconductor device . 【請求項４】 前記層間絶縁膜に選択的に形成する複数
の開口の総面積が、前記第２のパッド電極面積の１０％
以上であり、前記金属層上端と開口部上端面とで形成さ
れる段差が０．０３〜０．３μｍであることを特徴とす
る請求項３に記載の半導体装置の製造方法。4. A plurality of layers selectively formed on said interlayer insulating film.
Is 10% of the area of the second pad electrode.
And the upper end surface of the metal layer and the upper end surface of the opening.
Characterized in that the step difference is 0.03 to 0.3 μm.
A method for manufacturing a semiconductor device according to claim 3 . 【請求項５】 請求項１又は２に記載の半導体装置の第
２のパッド電極上へボンディングを超音波振動を併用し
た熱圧着により行うボンディング方法であって、印加す
る超音波振動の方向が、層間絶縁膜の開口部以外の上面
と第２のパッド電極との界面の面方向と一致しているこ
とを特徴とするボンディング方法。5. The semiconductor device according to claim 1, wherein
Bonding on the pad electrode of 2 using ultrasonic vibration
Bonding method by thermocompression bonding.
The direction of the ultrasonic vibration is higher than the opening of the interlayer insulating film.
And the plane direction of the interface between the second pad electrode and
And a bonding method .
JP9156985A 1997-06-13 1997-06-13 Semiconductor device and manufacturing method thereof Expired - Fee Related JP2964999B2 (en)

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Application Number Priority Date Filing Date Title
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