JPH0456237A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0456237A JPH0456237A JP2167149A JP16714990A JPH0456237A JP H0456237 A JPH0456237 A JP H0456237A JP 2167149 A JP2167149 A JP 2167149A JP 16714990 A JP16714990 A JP 16714990A JP H0456237 A JPH0456237 A JP H0456237A
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- insulating film
- interlayer insulating
- metallic
- metal wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 41
- 239000011229 interlayer Substances 0.000 claims abstract description 35
- 229910052751 metal Inorganic materials 0.000 claims description 84
- 239000002184 metal Substances 0.000 claims description 84
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 18
- 229920005591 polysilicon Polymers 0.000 claims description 18
- 239000010410 layer Substances 0.000 abstract description 13
- 238000000034 method Methods 0.000 abstract description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 8
- 229910052814 silicon oxide Inorganic materials 0.000 description 8
- 238000005229 chemical vapour deposition Methods 0.000 description 7
- 238000001312 dry etching Methods 0.000 description 7
- 239000000853 adhesive Substances 0.000 description 5
- 230000001070 adhesive effect Effects 0.000 description 5
- 238000004544 sputter deposition Methods 0.000 description 5
- 239000000758 substrate Substances 0.000 description 5
- 238000001459 lithography Methods 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- 230000001681 protective effect Effects 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000002994 raw material Substances 0.000 description 2
- 229910021332 silicide Inorganic materials 0.000 description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 2
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 2
- 229910021342 tungsten silicide Inorganic materials 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
- H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
- H01L2224/02165—Reinforcing structures
- H01L2224/02166—Collar structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05073—Single internal layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05556—Shape in side view
- H01L2224/05558—Shape in side view conformal layer on a patterned surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4807—Shape of bonding interfaces, e.g. interlocking features
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4845—Details of ball bonds
- H01L2224/48451—Shape
- H01L2224/48453—Shape of the interface with the bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は半導体装置、特に半導体装置における入力回路
部のワイヤー・ボンディング・パッド部に関するもので
ある。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a semiconductor device, and more particularly to a wire bonding pad section of an input circuit section in a semiconductor device.
従来の技術
半導体装置は、外部からの入力信号あるいは、半導体装
置からの出力信号を半導体装置内の金属配線パッド部と
、半導体装置外部につながる配線の間を金属のワイヤー
で接続することにより信号の入出力を行なっている。Conventional technology A semiconductor device receives an input signal from the outside or an output signal from the semiconductor device by connecting a metal wire between a metal wiring pad inside the semiconductor device and a wiring connected to the outside of the semiconductor device. Performing input/output.
以下従来の半導体装置の金属配線パッド部について図面
を用いて説明する。A metal wiring pad portion of a conventional semiconductor device will be described below with reference to the drawings.
第３図は、従来の半導体装置の金属配線パッド部の要部
断面図である。FIG. 3 is a sectional view of a main part of a metal wiring pad portion of a conventional semiconductor device.
半導体基板１の上部に層間絶縁膜２を形成し、その上部
に所定の形状の金属配線３を形成する。An interlayer insulating film 2 is formed on the top of a semiconductor substrate 1, and a metal wiring 3 having a predetermined shape is formed on top of the interlayer insulating film 2.
そして表面保護膜４形成後、金属ワイヤー５を接続する
。After the surface protective film 4 is formed, the metal wire 5 is connected.
層間絶縁膜２は半導体基板１の上部に化学的気相成長法
により、酸化シリコンを主成分とする約０．３μｍから
１μｍの厚みで形成する。層間絶縁膜２の上部に、スパ
ッタリングにより金属配線膜を約１μｍ成膜する。金属
配線３はリソグラフィおよびドライエツチングにより所
定のパターンに形成する。半導体外部からの異物（水分
、イオンなど）から半導体装置を保護するために、酸化
シリコンや窒化シリコンを主成分にする表面保護膜４を
形成し、金属ワイヤー５を接続する箇所には、約１００
μｍ角の窓をあけて金属配線３を表面に露出させ、金属
ワイヤーと接続する。金属ワイヤー５は、直径的３０μ
ｍから５０μｍで超音波振動と熱により金属配線３と接
続されて０る。The interlayer insulating film 2 is formed on the semiconductor substrate 1 by chemical vapor deposition to have a thickness of about 0.3 μm to 1 μm and mainly contains silicon oxide. A metal wiring film having a thickness of about 1 μm is formed on the interlayer insulating film 2 by sputtering. The metal wiring 3 is formed into a predetermined pattern by lithography and dry etching. In order to protect the semiconductor device from foreign substances (moisture, ions, etc.) from outside the semiconductor, a surface protective film 4 mainly composed of silicon oxide or silicon nitride is formed, and approximately 10
A μm square window is opened to expose the metal wiring 3 on the surface and connect it to a metal wire. The metal wire 5 has a diameter of 30μ
It is connected to the metal wiring 3 by ultrasonic vibration and heat at 50 μm from m.
金属ワイヤー５の先端は、金属配線３との接続部で約６
０μｍから１００μｍの直径になる。すなわち、金属ワ
イヤーが２〜３倍に広がる。The tip of the metal wire 5 has a diameter of about 6 mm at the connection point with the metal wiring 3.
The diameter ranges from 0 μm to 100 μm. That is, the metal wire expands two to three times.
このように製作された半導体装置において、半導体外部
との信号の入出力か可能となる。In the semiconductor device manufactured in this manner, it is possible to input and output signals to and from the outside of the semiconductor.
発明が解決しようとする課題
しかしながら、上記従来の構造では、金属配線３と金属
ワイヤー５との接着面積は約６０μｍから１００μｍで
あり、金属配線３と金属ワイヤー５の接続時や、半導体
装置の組立時に、外部からの機械的応力が生じる。この
ため金属配線３と金属ワイヤー５との界面あるいは金属
配線３と層間絶縁膜２との界面で剥離が発生しやすい。Problems to be Solved by the Invention However, in the conventional structure described above, the bonding area between the metal wiring 3 and the metal wire 5 is about 60 μm to 100 μm, which makes it difficult to connect the metal wiring 3 and the metal wire 5 or when assembling a semiconductor device. Sometimes external mechanical stresses arise. Therefore, peeling is likely to occur at the interface between the metal wiring 3 and the metal wire 5 or at the interface between the metal wiring 3 and the interlayer insulating film 2.
金属配線３．金属ワイヤー５と層間絶縁膜２との接着強
度を向上するには接着部分の面積を拡大する必要が、あ
る。すなわち、金属ワイヤー５の直径を太くし金属配線
３との接着面積を拡大し、なおかつ金属配線３の面積を
大きくする必要がある。金属ワイヤー５の直径を太くす
るには半導体装置組立装置の大幅な改造が必要であり金
属配線３の面積を広げるためには、レイアウト面積が増
加する不都合が生じる。Metal wiring 3. In order to improve the bonding strength between the metal wire 5 and the interlayer insulating film 2, it is necessary to increase the area of the bonded portion. That is, it is necessary to increase the diameter of the metal wire 5 to increase the bonding area with the metal wiring 3, and also to increase the area of the metal wiring 3. Increasing the diameter of the metal wire 5 requires significant modification of the semiconductor device assembly equipment, and increasing the area of the metal wiring 3 causes the disadvantage of increasing the layout area.
本発明は上記従来例の問題点を解決するもので、入力回
路パッド部と金属ワイヤーとの接着強度を向上させるこ
とか可能な半導体装置を提供することを目的とする。The present invention solves the problems of the prior art described above, and aims to provide a semiconductor device in which the adhesive strength between an input circuit pad portion and a metal wire can be improved.
課題を解決するための手段
この目的を達成するために、本発明の半導体装置は、入
力回路部の金属配線パッド部の下部に導電層と金属配線
と導電層とを接続するコンタクト窓を有する。Means for Solving the Problems To achieve this object, a semiconductor device of the present invention has a contact window for connecting a conductive layer, a metal wire, and a conductive layer under a metal wiring pad portion of an input circuit portion.
作用
この構造によって、金属配線の形状がコンタクト窓部に
おいて凹凸を持ち、金属ワイヤーと金属配線との接着面
積および金属配線と層間絶縁膜との接着面積を拡大する
ことができ、接着強度を向上することができる。また、
従来品と同等の接着強度ならばレイアウト面積を縮小す
ることができる。Effect: Due to this structure, the shape of the metal wiring has irregularities in the contact window portion, and the adhesion area between the metal wire and the metal wiring and the adhesion area between the metal wiring and the interlayer insulating film can be expanded, thereby improving the adhesive strength. be able to. Also,
If the adhesive strength is equivalent to that of conventional products, the layout area can be reduced.
実施例
以下、本発明の一実施例について、図面を参照しながら
説明する。EXAMPLE Hereinafter, an example of the present invention will be described with reference to the drawings.
第１図は、本発明の第１の実施例における、半導体装置
の入力回路部の金属配線パッド部の要部断面図を示すも
のである。FIG. 1 is a sectional view of a main part of a metal wiring pad section of an input circuit section of a semiconductor device in a first embodiment of the present invention.
半導体装置は、ワイヤー・ボンディング・パッドを構成
する金属層３が、層間絶縁膜７を介して、下層のポリサ
イド（シリサイド＋ポリシリコン）配線６上に積層され
、かつ金属層３が層間絶縁膜７に形成された２個以上の
スルーホールによりポリサイド配線６に接続される構造
を有するものである。In the semiconductor device, a metal layer 3 constituting a wire bonding pad is laminated on a lower polycide (silicide + polysilicon) wiring 6 via an interlayer insulating film 7, and the metal layer 3 is stacked on an interlayer insulating film 7. It has a structure in which it is connected to the polycide wiring 6 through two or more through holes formed in the polycide wiring 6.
層間絶縁膜２は半導体基板１の上部に化学的気相成長法
により、酸化シリコンを主成分として約０．３μｍから
１μｍの厚みで形成する。ポリサイド（シリサイド＋ポ
リシリコン、以下ポリサイドと称す）配線６は層間絶縁
膜２の上部に、化学的気相成長法により、モノシランを
原料ガスとしてポリシリコン膜を約０．３μｍから１μ
ｍ、 高融点金属とシリコンとの化合物（例えばタング
ステンシリサイドＷＳｉ、など）を約０．３μｍから０
．５μｍ成膜しリングラフィおよびドライエツチングに
より形成する。ポリサイド配線６の上部に化学的気相成
長法により、酸化シリコンを主成分とする層間絶縁膜７
を約０．３μｍから１μｍ形成する。スパッタリングに
より金属配線膜を約１μｍ成膜する。リングラフィおよ
びドライエツチングによりコンタクト窓８を層間絶縁膜
に形成する。コンタクト窓の大きさと間隔は、それぞれ
約１μｍにして、コンタクト窓を形成する。そしてスパ
ッタリングにより金属配線膜（例えばアルミニウム）を
約１μｍ成膜する。リソグラフィおよびドライエツチン
グにより所定のパターンに金属配線を形成する。入力回
路パッド部の金属配線３とポリサイド配線６の大きさは
約１００μｍ飛程度である。層間絶縁膜７に形成したコ
ンタクト窓８により、金属配線３は、ポリサイド配線６
と接続し層間絶縁膜の形状に沿って凹凸形状となり表面
積が増加する。金属配線３の上部には、半導体外部から
の異物（水分、イオンなど）から半導体装置を保護する
ために、酸化シリコンや窒化シリコンを主成分にする表
面保護膜４を形成しである。金属ワイヤー５を接続する
箇所には、約１００μｍ角の窓をあけ金属配線３を表面
に露出し、金属ワイヤーと接続する。ポリサイド配線６
とコンタクト窓８は集積回路半導体装置に用いられる多
層配線のレイアウト・パターンの一部を変更するだけで
形成することができる。The interlayer insulating film 2 is formed on the semiconductor substrate 1 by chemical vapor deposition to have a thickness of about 0.3 μm to 1 μm and mainly contains silicon oxide. A polycide (silicide + polysilicon, hereinafter referred to as polycide) wiring 6 is formed by depositing a polysilicon film of about 0.3 μm to 1 μm on the top of the interlayer insulating film 2 using monosilane as a raw material gas by chemical vapor deposition.
m, a compound of high melting point metal and silicon (for example, tungsten silicide WSi, etc.) from about 0.3 μm to 0.
．． A 5 μm thick film is formed by phosphorography and dry etching. An interlayer insulating film 7 mainly composed of silicon oxide is formed on the polycide wiring 6 by chemical vapor deposition.
A thickness of about 0.3 μm to 1 μm is formed. A metal wiring film with a thickness of about 1 μm is formed by sputtering. A contact window 8 is formed in the interlayer insulating film by phosphorography and dry etching. The size and interval of the contact windows are each about 1 μm to form the contact windows. Then, a metal wiring film (for example, aluminum) is formed to a thickness of about 1 μm by sputtering. Metal wiring is formed in a predetermined pattern by lithography and dry etching. The size of the metal wiring 3 and polycide wiring 6 in the input circuit pad portion is approximately 100 μm apart. The contact window 8 formed in the interlayer insulating film 7 allows the metal wiring 3 to connect to the polycide wiring 6.
The surface area becomes uneven and the surface area increases along the shape of the interlayer insulating film. A surface protection film 4 mainly composed of silicon oxide or silicon nitride is formed on the metal wiring 3 in order to protect the semiconductor device from foreign substances (moisture, ions, etc.) from outside the semiconductor. At the location where the metal wire 5 is to be connected, a window of about 100 μm square is opened to expose the metal wiring 3 to the surface and connected to the metal wire. Polycide wiring 6
The contact window 8 can be formed by simply changing a part of the layout pattern of the multilayer wiring used in the integrated circuit semiconductor device.
入力回路部の金属配線パッド部３の下部に、ポリサイド
配線６と金属配線３と前記ポリサイド配線６を接続する
コンタクト窓８を設ける。下層の層間絶縁膜に形成され
たコンタクト窓８により金属配線３の形状が凹凸となり
金属配線３の上部と下部の表面積が増加し、金属配線３
と金属ワイヤー５および金属配線３と下地の層間絶縁膜
７との接着強度を向上させることができる。A contact window 8 for connecting the polycide wiring 6, the metal wiring 3, and the polycide wiring 6 is provided below the metal wiring pad part 3 of the input circuit part. The contact window 8 formed in the lower interlayer insulating film makes the shape of the metal wiring 3 uneven, increasing the surface area of the upper and lower parts of the metal wiring 3, and increasing the surface area of the metal wiring 3.
The adhesion strength between the metal wire 5 and the metal wiring 3 and the underlying interlayer insulating film 7 can be improved.
以下、本発明の第２の実施例について、図面を参照しな
から説明する。A second embodiment of the present invention will be described below with reference to the drawings.
第２図は、半導体装置の入力回路部の金属配線パッド部
の要部断面図である。FIG. 2 is a sectional view of a main part of a metal wiring pad section of an input circuit section of a semiconductor device.
この実施例の半導体装置は、ワイヤー・ボンディング・
パッドを構成する金属層３が、層間絶縁膜７を介して、
下層のポリシリコン配線９上に積層され、かつ金属層３
が層間絶縁膜７に形成された２個以上のスルーホールに
よりポリシリコン配線９に接続される構造を有するもの
である。The semiconductor device of this example uses wire bonding,
The metal layer 3 constituting the pad is interposed via the interlayer insulating film 7,
Laminated on the lower layer polysilicon wiring 9 and metal layer 3
is connected to polysilicon wiring 9 through two or more through holes formed in interlayer insulating film 7.
層間絶縁膜２は半導体基板１の上部に化学的気相成長法
により、酸化シリコンを主成分として約０．３μｍから
１μｍの厚みで形成する。ポリシリコン配線９は層間絶
縁膜２の上部に、化学的気相成長法により、モノシラン
を原料ガスとして用いてポリシリコン膜を約０．３μｍ
から１μｍ成膜する。ポリシリコン膜の加工はりソグラ
フィおよびドライエツチングにより行う。ポリシリコン
配線６の上部に化学的気相成長法により、酸化シリコン
を主成分とする層間絶縁膜７を約０．３μｍから１μｍ
形成する。スパッタリングにより金属配線膜を約１μｍ
成膜する。リングラフィおよびドライエツチングにより
コンタクト窓８を層間絶縁膜に形成する。コンタクト窓
の大きさと間隔は、それぞれ約１μｍにして、コンタク
ト窓を形成する。そしてスパッタリングにより金属配線
膜（例えばアルミニウム）を約１μｍ成膜する。リソグ
ラフィおよびドライエツチングにより所定のパターンに
金属配線を形成する。入力回路パッド部の金属配線３と
ポリシリコン配線９の大きさは約１００μｍ飛程度であ
る。層間絶縁膜７に形成したコンタクト窓８により、金
属配線３は、ポリシリコン配線９と接続し層間絶縁膜の
形状に沿って凹凸形状となり表面積が増加する。金属配
線３の上部には、半導体外部からの異物（水分、イオン
など）から半導体装置を保護するために、酸化シリコン
や窒化シリコンを主成分にする表面保護膜４を形成し、
金属ワイヤー５を接続する箇所には、約１００μｍ角の
窓をあけて金属配線３を表面に露出して、金属ワイヤー
と接続する。ポリシリコン配線９とコンタクト窓８は集
積回路半導体装置に用いられる多層配線のレイアウト・
パターンの一部を変更するだけで形成することができる
。The interlayer insulating film 2 is formed on the semiconductor substrate 1 by chemical vapor deposition to have a thickness of about 0.3 μm to 1 μm and mainly contains silicon oxide. The polysilicon wiring 9 is formed by depositing a polysilicon film with a thickness of approximately 0.3 μm on the interlayer insulating film 2 by chemical vapor deposition using monosilane as a raw material gas.
A film with a thickness of 1 μm is formed. Processing of the polysilicon film is performed by lithography and dry etching. An interlayer insulating film 7 mainly composed of silicon oxide is formed on the polysilicon wiring 6 to a thickness of about 0.3 μm to 1 μm by chemical vapor deposition.
Form. The metal wiring film is approximately 1 μm thick by sputtering.
Form a film. A contact window 8 is formed in the interlayer insulating film by phosphorography and dry etching. The size and interval of the contact windows are each about 1 μm to form the contact windows. Then, a metal wiring film (for example, aluminum) is formed to a thickness of about 1 μm by sputtering. Metal wiring is formed in a predetermined pattern by lithography and dry etching. The size of the metal wiring 3 and polysilicon wiring 9 in the input circuit pad portion is approximately 100 μm apart. Through the contact window 8 formed in the interlayer insulating film 7, the metal wiring 3 is connected to the polysilicon wiring 9 and has an uneven shape along the shape of the interlayer insulating film, increasing the surface area. A surface protection film 4 mainly composed of silicon oxide or silicon nitride is formed on the metal wiring 3 in order to protect the semiconductor device from foreign substances (moisture, ions, etc.) from outside the semiconductor.
At the location where the metal wire 5 is to be connected, a window of about 100 μm square is opened to expose the metal wiring 3 to the surface and connected to the metal wire. The polysilicon wiring 9 and the contact window 8 are used in the layout and layout of multilayer wiring used in integrated circuit semiconductor devices.
It can be formed by simply changing part of the pattern.
入力回路部の金属配線パッド部３の下部に、ポリシリコ
ン配線９と金属配線３と前記ポリシリコン配線９を接続
するコンタクト窓８を設ける。下層の層間絶縁膜に形成
されたコンタクト窓８により、金属配線３の形状が凹凸
となり金属配線３の上部と下部の表面積が増加し、金属
配線３と金属ワイヤー５および金属配線３と下地の層間
絶縁膜７との接着強度を向上させることができる。A contact window 8 connecting the polysilicon wiring 9, the metal wiring 3, and the polysilicon wiring 9 is provided below the metal wiring pad part 3 of the input circuit part. Due to the contact window 8 formed in the lower interlayer insulating film, the shape of the metal wiring 3 becomes uneven, increasing the surface area of the upper and lower parts of the metal wiring 3, and the interlayer between the metal wiring 3 and the metal wire 5 and between the metal wiring 3 and the underlying layer. The adhesive strength with the insulating film 7 can be improved.
また第１の発明でポリサイド配線を用いているが、導電
層が２層構造でありプロセス上の難易度が高くまた、ポ
リサイドとタングステンシリサイドとの熱膨張係数の差
による剥がれが発生し易く第２の発明である導電層がポ
リシリコン配線層の方が製造し易く、組立時の信頼性も
著しく高くなる。Further, although polycide wiring is used in the first invention, the conductive layer has a two-layer structure, which is highly difficult to process, and peeling is likely to occur due to the difference in thermal expansion coefficient between polycide and tungsten silicide. According to the invention of the present invention, a polysilicon wiring layer is easier to manufacture as a conductive layer and has significantly higher reliability during assembly.
発明の効果
本発明の半導体装置は金属配線と金属ワイヤーの接続時
や半導体装置の組立時の外部からの機械的応力により金
属配線と金属ワイヤーとの界面あるいは金属配線と層間
絶縁膜との界面で剥離が発生するのを大幅に改善する。Effects of the Invention The semiconductor device of the present invention can be damaged at the interface between the metal wiring and the metal wire or at the interface between the metal wiring and the interlayer insulating film due to external mechanical stress when connecting the metal wiring and the semiconductor device or when assembling the semiconductor device. Significantly reduces the occurrence of peeling.
また、従来品と同等の接着強度であるならばレイアウト
面積を縮小することができる。Furthermore, if the adhesive strength is equivalent to that of conventional products, the layout area can be reduced.
第１図は本発明の第１の実施例における半導体装置の要
部断面図、第２図は本発明の第２の実施例における半導
体装置の要部断面図、第３図は従来の半導体装置の要部
断面図である。
１・・・・・・半導体基板、２・・・・・・層間絶縁膜
、３・・・・・・金属配線、４・・・・・・表面保護膜
、５・・・・・・金属ワイヤー ６・・・・・・ポリシ
リコン配線、７・・・・・・層間絶縁膜、８・・・・・
・コンタクト窓、９・・・・・・ポリシリコン配線。FIG. 1 is a cross-sectional view of a main part of a semiconductor device according to a first embodiment of the present invention, FIG. 2 is a cross-sectional view of a main part of a semiconductor device according to a second embodiment of the present invention, and FIG. 3 is a conventional semiconductor device. FIG. DESCRIPTION OF SYMBOLS 1...Semiconductor substrate, 2...Interlayer insulating film, 3...Metal wiring, 4...Surface protective film, 5...Metal Wire 6...Polysilicon wiring, 7...Interlayer insulating film, 8...
・Contact window, 9...Polysilicon wiring.
Claims (2)
ング・パッドと、前記ポリサイド配線と金属配線が層間
絶縁膜に設けられた複数個のコンタクト窓を通して接続
され、前記金属配線上に接続された金属ワイヤーを備え
たことを特徴とする半導体装置。(1) A wire bonding pad formed of polycide wiring, the polycide wiring and metal wiring are connected through a plurality of contact windows provided in an interlayer insulating film, and the metal wire connected on the metal wiring is A semiconductor device characterized by:
特徴とする請求項１記載の半導体装置。(2) The semiconductor device according to claim 1, wherein the polycide wiring is a polysilicon wiring.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2167149A JPH0456237A (en) | 1990-06-25 | 1990-06-25 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2167149A JPH0456237A (en) | 1990-06-25 | 1990-06-25 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0456237A true JPH0456237A (en) | 1992-02-24 |
Family
ID=15844331
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2167149A Pending JPH0456237A (en) | 1990-06-25 | 1990-06-25 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0456237A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5409861A (en) * | 1993-09-15 | 1995-04-25 | Hyundai Electronics Industries Co., Ltd. | Method of forming a via plug in a semiconductor device |
| USRE36475E (en) * | 1993-09-15 | 1999-12-28 | Hyundai Electronics Industries Co., Ltd. | Method of forming a via plug in a semiconductor device |
| US7026721B2 (en) * | 1999-11-18 | 2006-04-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of improving copper pad adhesion |
| JP2010153901A (en) * | 2002-11-26 | 2010-07-08 | Freescale Semiconductor Inc | Semiconductor device having bonding pad and method of forming the same |
| JP2013171928A (en) * | 2012-02-20 | 2013-09-02 | Tdk Corp | Multilayer terminal electrode and electronic component |
-
1990
- 1990-06-25 JP JP2167149A patent/JPH0456237A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5409861A (en) * | 1993-09-15 | 1995-04-25 | Hyundai Electronics Industries Co., Ltd. | Method of forming a via plug in a semiconductor device |
| USRE36475E (en) * | 1993-09-15 | 1999-12-28 | Hyundai Electronics Industries Co., Ltd. | Method of forming a via plug in a semiconductor device |
| USRE38383E1 (en) | 1993-09-15 | 2004-01-13 | Hyundai Electronics Industries Co. Ltd. | Method for forming a via plug in a semiconductor device |
| US7026721B2 (en) * | 1999-11-18 | 2006-04-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of improving copper pad adhesion |
| JP2010153901A (en) * | 2002-11-26 | 2010-07-08 | Freescale Semiconductor Inc | Semiconductor device having bonding pad and method of forming the same |
| JP2013171928A (en) * | 2012-02-20 | 2013-09-02 | Tdk Corp | Multilayer terminal electrode and electronic component |
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