JPH1012672A - Wiring board - Google Patents
Wiring boardInfo
- Publication number
- JPH1012672A JPH1012672A JP16624396A JP16624396A JPH1012672A JP H1012672 A JPH1012672 A JP H1012672A JP 16624396 A JP16624396 A JP 16624396A JP 16624396 A JP16624396 A JP 16624396A JP H1012672 A JPH1012672 A JP H1012672A
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- solder
- wiring board
- solder layer
- wiring conductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16237—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area disposed in a recess of the surface of the item
Landscapes
- Non-Metallic Protective Coatings For Printed Circuits (AREA)
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、ＩＣチップ等の電
子部品が半田接合によって実装される配線基板の改良に
関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement in a wiring board on which electronic components such as IC chips are mounted by soldering.
【０００２】[0002]
【従来の技術】従来の配線基板は、例えば図４に示す如
く、アルミナセラミックス等から成る絶縁基板１１の上
面に金属材料から成る配線導体１２を複数個、被着配列
させるとともにこれら配線導体１２の一部上面に所定厚
みの半田層１３を形成した構造を有している。2. Description of the Related Art As shown in FIG. 4, for example, a conventional wiring board has a plurality of wiring conductors 12 made of a metal material on a top surface of an insulating substrate 11 made of alumina ceramic or the like. It has a structure in which a solder layer 13 having a predetermined thickness is formed on a part of the upper surface.
【０００３】前記半田層１３は上述した配線基板Ａ’に
外部の電子部品１４を電気的・機械的に接続させるため
のものであり、かかる接続作業は、まず配線基板Ａ’上
に電子部品１４をその端子電極１５が配線導体１２上の
半田層１３に当接するようにして載置させ、しかる後、
前記半田層１３を高温で加熱溶融し各配線導体１２と電
子部品１４の端子電極１５とを半田接合させることによ
って行われる。[0003] The solder layer 13 is for electrically and mechanically connecting an external electronic component 14 to the above-mentioned wiring board A '. Is placed such that the terminal electrode 15 is in contact with the solder layer 13 on the wiring conductor 12, and thereafter,
The solder layer 13 is heated and melted at a high temperature, and the respective wiring conductors 12 and the terminal electrodes 15 of the electronic component 14 are joined by soldering.
【０００４】[0004]
【発明が解決しようとする課題】しかしながら、このよ
うな従来の配線基板Ａ’においては、その上に実装され
る電子部品１４の端子電極１５が極めて高密度に配列さ
れているような場合、配線基板Ａ’の配線導体１２も端
子電極１５の配列密度と略等しいピッチ（例えば、１０
０μｍ以下のピッチ）で極めて高密度に配列させる必要
がある。このため、電子部品１４を配線基板Ａ’上に実
装させるにあたって半田層１３を加熱溶融させると、該
溶融した半田自身の表面張力や電子部品１４の重み等に
よって半田層１３が横に広がり、隣接する半田層１３同
士が短絡を起こす欠点が誘発される。However, in such a conventional wiring board A ', when the terminal electrodes 15 of the electronic components 14 mounted thereon are extremely densely arranged, The pitch of the wiring conductors 12 on the substrate A ′ is also substantially equal to the arrangement density of the terminal electrodes 15 (for example, 10
(A pitch of 0 μm or less) at very high density. Therefore, when the solder layer 13 is heated and melted when the electronic component 14 is mounted on the wiring board A ′, the solder layer 13 spreads laterally due to the surface tension of the melted solder itself, the weight of the electronic component 14 and the like, and This causes a short-circuit between the solder layers 13 to be short-circuited.
【０００５】[0005]
【課題を解決するための手段】本発明は上記欠点に鑑み
案出されたもので、絶縁基板上に複数個の配線導体を被
着させるとともに該配線導体の一部上面に電子部品の端
子電極が接続される半田層を設けて成る配線基板におい
て、前記絶縁基板上面の各配線導体間に、前記配線導体
及び半田層の厚みの総和と略等しい厚みを有する電気絶
縁材から成る分離帯を配設したことを特徴とする。また
本発明の配線基板は、前記分離帯がガラスにより形成さ
れていることを特徴とする。SUMMARY OF THE INVENTION The present invention has been devised in view of the above-mentioned drawbacks, and has a plurality of wiring conductors attached on an insulating substrate and a terminal electrode of an electronic component provided on a partial upper surface of the wiring conductor. In the wiring board provided with a solder layer to be connected, a separation band made of an electrical insulating material having a thickness substantially equal to the total thickness of the wiring conductor and the solder layer is provided between the wiring conductors on the upper surface of the insulating substrate. It is characterized by having been established. The wiring board of the present invention is characterized in that the separation band is formed of glass.
【０００６】[0006]
【発明の実施の形態】以下、本発明を添付図面に基づい
て詳細に説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
【０００７】図１は本発明の配線基板の一形態を示す部
分平面図、図２は図１のＸ−Ｘ線断面図であり、１は絶
縁基板、２は配線導体、３は半田層、４は分離帯であ
る。FIG. 1 is a partial plan view showing an embodiment of a wiring board according to the present invention. FIG. 2 is a cross-sectional view taken along the line XX of FIG. 1, wherein 1 is an insulating substrate, 2 is a wiring conductor, 3 is a solder layer, Reference numeral 4 denotes a separation zone.
【０００８】前記絶縁基板１は、例えば、厚み１ｍｍ程
度のホウケイ酸ガラス、ソーダライムガラス、アルミナ
セラミックス等により形成されており、その上面で複数
個の配線導体２、半田層３及び分離帯４を支持してい
る。The insulating substrate 1 is made of, for example, borosilicate glass, soda lime glass, alumina ceramics or the like having a thickness of about 1 mm, and a plurality of wiring conductors 2, solder layers 3 and separation bands 4 are formed on the upper surface thereof. I support it.
【０００９】前記絶縁基板１は、例えば、アルミナセラ
ミックスにより形成する場合、アルミナ、シリカ、マグ
ネシア等のセラミックス原料粉末に適当な有機溶剤、溶
媒を添加混合して泥漿状に成すとともにこれを従来周知
のドクターブレード法等を採用することによってセラミ
ックグリーンシートを形成し、しかる後、前記セラミッ
クグリーンシートを所定形状に打ち抜き加工するととも
に高温で焼成することによって製作される。When the insulating substrate 1 is formed of, for example, alumina ceramics, an appropriate organic solvent and a solvent are added to a ceramic raw material powder such as alumina, silica, magnesia, etc., and the mixture is formed into a slurry. A ceramic green sheet is formed by employing a doctor blade method or the like, and thereafter, the ceramic green sheet is punched into a predetermined shape and fired at a high temperature.
【００１０】また、前記絶縁基板１の上面に被着された
複数個の配線導体２は、Ａｇ、Ｃｕ、Ａｕ等の金属材料
から成っており、隣接する配線導体２との間に所定の間
隔が設けられ、例えば、３〜２０μｍの厚みをもって形
成される。The plurality of wiring conductors 2 attached to the upper surface of the insulating substrate 1 are made of a metal material such as Ag, Cu, Au or the like. Is formed, for example, with a thickness of 3 to 20 μm.
【００１１】前記配線導体２は、その一部上面に被着さ
れる半田層３を介して外部の電子部品７の端子電極８に
接続され、これによって電子部品７に電力や電気信号等
を供給するようになっている。The wiring conductor 2 is connected to a terminal electrode 8 of an external electronic component 7 via a solder layer 3 attached to a part of the upper surface thereof, thereby supplying electric power, an electric signal and the like to the electronic component 7. It is supposed to.
【００１２】尚、前記配線導体２は、例えば、銀粉末に
適当な有機溶媒、有機溶剤等を添加混合して得た銀ペー
ストを絶縁基板１の上面に従来周知のスクリーン印刷法
を採用し所定厚み（３〜２０μｍ）、所定パターンに印
刷塗布し、しかる後、これを約５８０℃の温度で焼き付
けることによって被着形成される。The wiring conductor 2 is formed, for example, by applying a well-known screen printing method on a top surface of the insulating substrate 1 by applying a silver paste obtained by adding and mixing an appropriate organic solvent, an organic solvent and the like to silver powder. It is formed by printing and applying a predetermined pattern with a thickness (3 to 20 μm) and then baking it at a temperature of about 580 ° C.
【００１３】また一方、前記半田層３は上述した配線導
体２と電子部品７の端子電極８とを電気的・機械的に接
続するためのものであり、複数個の配線導体２の各一端
に略等しい厚み（５〜３０μｍ）をもって個別に被着さ
れている。On the other hand, the solder layer 3 is for electrically and mechanically connecting the wiring conductor 2 and the terminal electrode 8 of the electronic component 7 to each other. They are individually applied with a substantially equal thickness (5 to 30 μm).
【００１４】更に、前記絶縁基板１は、その上面で各配
線導体２間に前記配線導体２及び半田層３の厚みの総和
と略等しい厚みをもった分離帯４を配設させている。Further, on the upper surface of the insulating substrate 1, a separator 4 having a thickness substantially equal to the sum of the thicknesses of the wiring conductors 2 and the solder layers 3 is disposed between the wiring conductors 2 on the upper surface.
【００１５】前記分離帯４は半田ぬれ性の悪い電気絶縁
材、例えば、ガラス、熱可塑性樹脂等によって形成され
ており、配線導体２及び半田層３の厚みの総和と略等し
い厚みに形成されているため、その表面が半田層３の上
面と同一平面を成すこととなる。The separation band 4 is formed of an electrical insulating material having poor solder wettability, for example, glass, thermoplastic resin, or the like, and is formed to have a thickness substantially equal to the total thickness of the wiring conductor 2 and the solder layer 3. Therefore, the surface thereof is flush with the upper surface of the solder layer 3.
【００１６】このように、前記絶縁基板の上面の各配線
導体２間に配線導体２及び半田層３の厚みの総和と略等
しい厚みを有する電気絶縁材から成る分離帯４を配設し
たことから、隣接する半田層３間には分離帯４による壁
が形成されることとなる。このため、外部の電子部品７
を配線基板Ａ上に実装させるにあたり半田層３を加熱溶
融させても、該溶融した半田３の幅や高さは分離帯４に
よって規制されることとなり、半田３の表面張力や電子
部品７の重み等によって隣接する半田層３同士が短絡を
起こすことはない。従って、配線基板Ａの配線導体２を
電子部品７の端子電極８に対して確実かつ良好に接続さ
せることが可能となる。As described above, the separation band 4 made of an electrically insulating material having a thickness substantially equal to the total thickness of the wiring conductor 2 and the solder layer 3 is provided between the wiring conductors 2 on the upper surface of the insulating substrate. A wall formed by the separation band 4 is formed between the adjacent solder layers 3. Therefore, external electronic components 7
Even when the solder layer 3 is heated and melted when the solder layer 3 is mounted on the wiring board A, the width and height of the melted solder 3 are regulated by the separation band 4, and the surface tension of the solder 3 and the electronic component 7 Adjacent solder layers 3 are not short-circuited by weight or the like. Therefore, the wiring conductor 2 of the wiring board A can be reliably and satisfactorily connected to the terminal electrode 8 of the electronic component 7.
【００１７】また、前記分離帯４は配線導体２及び半田
層３の厚みの総和と略等しい厚みを有していることか
ら、外部の電子部品７を配線基板Ａ上に実装する際、電
子部品７を分離帯４の上面で安定的に支持し、配線基板
Ａと電子部品７との間の距離を略一定に保つことができ
る。従って、前記半田層３の加熱溶融時に電子部品７が
バランスを崩して傾いたりすることはなく、電子部品７
を極めて安定した状態で実装させることが可能である。Further, since the separation band 4 has a thickness substantially equal to the total thickness of the wiring conductor 2 and the solder layer 3, when the external electronic component 7 is mounted on the wiring board A, 7 can be stably supported on the upper surface of the separation band 4, and the distance between the wiring board A and the electronic component 7 can be kept substantially constant. Therefore, when the solder layer 3 is heated and melted, the electronic component 7 does not lose its balance and tilt.
Can be implemented in an extremely stable state.
【００１８】更にこの場合、前記分離帯４を熱伝導率の
低いガラスにより形成しておけば、前記半田層３を溶融
させる際に外部より印加される熱が該半田層３を取り囲
むように配置される分離帯４中で良好に蓄積され、これ
によって半田リフローを短時間で効率良く行うことがで
きる。従って前記分離帯４はガラスにより形成すること
が好ましい。Furthermore, in this case, if the separation zone 4 is formed of glass having a low thermal conductivity, heat applied from the outside when melting the solder layer 3 is arranged so as to surround the solder layer 3. Therefore, the solder is re-flowed efficiently in the separation zone 4 and the solder reflow can be efficiently performed in a short time. Therefore, it is preferable that the separation zone 4 is formed of glass.
【００１９】尚、前記分離帯４は従来周知の厚膜手法、
フォトリソグラフィー技術（リフトオフ法）等を採用す
ることによって所定厚み、パターンに被着形成される。
具体的には、まず絶縁基板１の上面所定領域に液状に成
した光硬化型樹脂の前駆体をスクリーン印刷法、スピン
コート法等によって所定の厚みに塗布し、次に前記前駆
体を分離帯４の反転パターンに応じて露光、現像し、し
かる後、絶縁基板上面の電子部品７が実装される領域に
わたってガラスペーストを塗布、焼成し、最後に光硬化
型樹脂のパターンをその上に被着させたガラスと共に剥
離させることによってガラスから成る分離帯４が所定パ
ターンで被着形成されることとなる。このとき、前記分
離帯４の材料として、半田ぬれ性が悪く、且つ、軟化温
度が半田３の溶融温度よりも高く設定された電気絶縁
材、例えば、ガラス等を用いておけば、半田層３をディ
ッピング法等によって極めて簡易に被着形成することが
できる。即ち、上面に配線導体２及び分離帯４が形成さ
れた絶縁基板１を加熱溶融した半田浴の中にまるごと浸
漬すれば、半田層３が配線導体２の露出された箇所にの
み選択的に付着され、所定の半田層３を極めて簡単に得
ることができる。尚、このような半田層３を付着させた
くない領域があれば、その部分に予めソルダーレジスト
膜５を被着させておけば良い。The separation zone 4 is formed by a conventionally known thick film method.
By adopting a photolithography technique (lift-off method) or the like, a predetermined thickness and a predetermined pattern are formed.
Specifically, first, a liquid photocurable resin precursor is applied to a predetermined area on the upper surface of the insulating substrate 1 to a predetermined thickness by a screen printing method, a spin coating method, or the like. Exposure and development are performed in accordance with the reverse pattern of 4, and then a glass paste is applied and baked over the region of the upper surface of the insulating substrate on which the electronic component 7 is to be mounted. Finally, a pattern of a photocurable resin is deposited thereon. By separating the glass with the separated glass, the separation band 4 made of glass is formed in a predetermined pattern. At this time, if the material of the separation band 4 is an electric insulating material having a poor solder wettability and a softening temperature higher than the melting temperature of the solder 3, for example, glass or the like, the solder layer 3 may be used. Can be formed very easily by a dipping method or the like. That is, if the insulating substrate 1 on which the wiring conductor 2 and the separation band 4 are formed on the upper surface is completely immersed in a heated and melted solder bath, the solder layer 3 selectively adheres only to the exposed portion of the wiring conductor 2. Thus, the predetermined solder layer 3 can be obtained very easily. If there is an area where the solder layer 3 is not desired to be attached, the solder resist film 5 may be previously applied to the area.
【００２０】以上のような配線基板Ａ上に外部の電子部
品７を実装させる場合は、まず電子部品７をその端子電
極８が配線導体２上の半田層３に当接されるようにして
配線基板Ａ上に載置させ、しかる後、前記半田層３を高
温で加熱溶融させて各配線導体２と電子部品７の端子電
極８とを半田接合させることによって行われ、これによ
って配線基板Ａの配線導体２と電子部品７の端子電極８
とが電気的・機械的に接続されることとなる。When the external electronic component 7 is mounted on the wiring board A as described above, first, the electronic component 7 is connected to the wiring layer 2 such that the terminal electrode 8 is in contact with the solder layer 3 on the wiring conductor 2. This is carried out by placing the wiring layer 2 on the substrate A, and thereafter, by heating and melting the solder layer 3 at a high temperature and soldering the wiring conductors 2 to the terminal electrodes 8 of the electronic components 7. Wiring conductor 2 and terminal electrode 8 of electronic component 7
Are electrically and mechanically connected.
【００２１】尚、本発明は上述した実施形態に限定され
るものではなく、本発明の要旨を逸脱しない範囲におい
て種々の変更、改良等が可能であり、例えば、図３に示
す如く、絶縁基板１の一部をエッチング等によって加工
することで分離帯４ａを形成しても良いし、或いは、上
述の配線導体２、半田層３及び分離帯４を電子部品７が
実装される領域にのみ最初にパターン形成しておき、そ
の後で前記領域の配線導体２に別の配線導体を接続する
ことで配線基板を製作するようにしても良く、いずれの
場合においても上述の実施形態と同様の効果を奏する。It should be noted that the present invention is not limited to the above-described embodiment, and various changes and improvements can be made without departing from the scope of the present invention. For example, as shown in FIG. 1 may be processed by etching or the like to form the separation band 4a, or the wiring conductor 2, the solder layer 3 and the separation band 4 may be formed only in the region where the electronic component 7 is mounted. The wiring board may be manufactured by connecting a different wiring conductor to the wiring conductor 2 in the region after that, and in any case, the same effect as in the above-described embodiment can be obtained. Play.
【００２２】また、本発明をＬＥＤプリンタヘッドのＬ
ＥＤアレイ等を実装するための配線基板に適用する場合
は、絶縁基板をガラス等の透明材料により形成し、更に
分離帯の一部を除去する等してＬＥＤアレイからの光を
通過させるための窓部を設けるようにすれば良い。Also, the present invention relates to the LED printer head L
When applied to a wiring board for mounting an ED array or the like, an insulating substrate is formed of a transparent material such as glass, and a part of a separation band is removed to transmit light from the LED array. A window may be provided.
【００２３】[0023]
【発明の効果】本発明の配線基板によれば、絶縁基板上
面の各配線導体間に配線導体及び半田層の厚みの総和と
略等しい厚みを有する電気絶縁材から成る分離帯を配設
したことから、隣接する半田層間に分離帯による壁が形
成されることとなる。このため、外部の電子部品を配線
基板上に実装させるにあたり半田層を加熱溶融させて
も、該溶融した半田の幅や高さは分離帯によって規制さ
れることとなり、半田の表面張力や電子部品の重み等に
よって隣接する半田層同士が短絡を起こすことはない。
従って、配線基板の配線導体を電子部品の端子電極に確
実かつ良好に接続させることが可能となる。According to the wiring board of the present invention, a separation band made of an electrically insulating material having a thickness substantially equal to the total thickness of the wiring conductor and the solder layer is provided between the wiring conductors on the upper surface of the insulating substrate. Therefore, a wall formed by a separation band is formed between adjacent solder layers. For this reason, even when the solder layer is heated and melted when mounting the external electronic component on the wiring board, the width and height of the melted solder are regulated by the separator, and the surface tension of the solder and the electronic component The adjacent solder layers do not cause a short circuit due to the weight or the like.
Therefore, it is possible to reliably and satisfactorily connect the wiring conductor of the wiring board to the terminal electrode of the electronic component.
【００２４】また本発明の配線基板によれば、前記分離
帯が配線導体及び半田層の厚みの総和と略等しい厚みを
有していることから、外部の電子部品を配線基板上に実
装する際、電子部品を分離帯の上面で安定的に支持し、
配線基板と電子部品との間の距離を略一定に保つことが
できる。従って、半田層の加熱溶融時に電子部品がバラ
ンスを崩して傾いたりすることはなく、電子部品を極め
て安定した状態で実装させることが可能である。Further, according to the wiring board of the present invention, since the separator has a thickness substantially equal to the total thickness of the wiring conductor and the solder layer, it is possible to mount an external electronic component on the wiring board. , Electronic components are stably supported on the upper surface of the separator,
The distance between the wiring board and the electronic component can be kept substantially constant. Therefore, the electronic component can be mounted in an extremely stable state without the electronic component being out of balance and tilting when the solder layer is heated and melted.
【図１】本発明の配線基板の一形態を示す部分平面図で
ある。FIG. 1 is a partial plan view showing one embodiment of a wiring board of the present invention.
【図２】図１のＸ−Ｘ線断面図である。FIG. 2 is a sectional view taken along line XX of FIG.
【図３】本発明の配線基板の他の形態を示す断面図であ
る。FIG. 3 is a sectional view showing another embodiment of the wiring board of the present invention.
【図４】従来の配線基板の部分断面図である。FIG. 4 is a partial cross-sectional view of a conventional wiring board.
１・・・絶縁基板 ２・・・配線導体 ３・・・半田層 ４・・・分離帯 ７・・・電子部品 ８・・・端子電極 DESCRIPTION OF SYMBOLS 1 ... Insulating board 2 ... Wiring conductor 3 ... Solder layer 4 ... Separation band 7 ... Electronic component 8 ... Terminal electrode
───────────────────────────────────────────────────── フロントページの続き (72)発明者 重田 泰彦 京都府相楽郡精華町光台３丁目５番地 京 セラ株式会社中央研究所内 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Yasuhiko Shigeta 3-5 Koikodai, Seika-cho, Soraku-gun, Kyoto Pref.
Claims (2)
るとともに該配線導体の一部上面に電子部品の端子電極
が接続される半田層を設けて成る配線基板において、 前記絶縁基板上面の各配線導体間に、前記配線導体及び
半田層の厚みの総和と略等しい厚みを有する電気絶縁材
から成る分離帯を配設したことを特徴とする配線基板。1. A wiring board comprising a plurality of wiring conductors provided on an insulating substrate and a solder layer connected to a terminal electrode of an electronic component on a partial upper surface of the wiring conductor. A wiring board, wherein a separation band made of an electrical insulating material having a thickness substantially equal to the sum of the thicknesses of the wiring conductor and the solder layer is disposed between the respective wiring conductors.
ことを特徴とする請求項１に記載の配線基板。2. The wiring board according to claim 1, wherein said separation band is formed of glass.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16624396A JP3523418B2 (en) | 1996-06-26 | 1996-06-26 | Wiring board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16624396A JP3523418B2 (en) | 1996-06-26 | 1996-06-26 | Wiring board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH1012672A true JPH1012672A (en) | 1998-01-16 |
| JP3523418B2 JP3523418B2 (en) | 2004-04-26 |
Family
ID=15827773
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16624396A Expired - Fee Related JP3523418B2 (en) | 1996-06-26 | 1996-06-26 | Wiring board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3523418B2 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003168829A (en) * | 2001-09-19 | 2003-06-13 | Matsushita Electric Works Ltd | Light emitting device |
| JP2005150386A (en) * | 2003-11-14 | 2005-06-09 | Stanley Electric Co Ltd | Semiconductor device and its manufacturing method |
| JP2008124107A (en) * | 2006-11-09 | 2008-05-29 | Fujitsu Ltd | Wiring board, semiconductor part and manufacturing method for wiring board |
-
1996
- 1996-06-26 JP JP16624396A patent/JP3523418B2/en not_active Expired - Fee Related
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003168829A (en) * | 2001-09-19 | 2003-06-13 | Matsushita Electric Works Ltd | Light emitting device |
| JP2005150386A (en) * | 2003-11-14 | 2005-06-09 | Stanley Electric Co Ltd | Semiconductor device and its manufacturing method |
| JP4580633B2 (en) * | 2003-11-14 | 2010-11-17 | スタンレー電気株式会社 | Semiconductor device and manufacturing method thereof |
| JP2008124107A (en) * | 2006-11-09 | 2008-05-29 | Fujitsu Ltd | Wiring board, semiconductor part and manufacturing method for wiring board |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3523418B2 (en) | 2004-04-26 |
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