JP5494559B2 - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof Download PDF

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JP5494559B2
JP5494559B2 JP2011094862A JP2011094862A JP5494559B2 JP 5494559 B2 JP5494559 B2 JP 5494559B2 JP 2011094862 A JP2011094862 A JP 2011094862A JP 2011094862 A JP2011094862 A JP 2011094862A JP 5494559 B2 JP5494559 B2 JP 5494559B2
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layer
electrode
semiconductor chip
semiconductor device
surface electrode
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JP2011193007A (en
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良成 池田
岳志 藤井
克彦 吉原
祐二 飯塚
満男 山下
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Fuji Electric Co Ltd
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Fuji Electric Co Ltd
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  • Engineering & Computer Science (AREA)
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  • Electrodes Of Semiconductors (AREA)
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Description

本発明は半導体チップおよびこれを用いた半導体装置に関し、特に裏面電極が絶縁基板上に構成された回路パターンに接合され、表面電極が接続導体に接合される半導体チップと、この半導体チップを前記絶縁基板に実装した半導体装置に関する。   The present invention relates to a semiconductor chip and a semiconductor device using the semiconductor chip, and in particular, a semiconductor chip in which a back electrode is bonded to a circuit pattern formed on an insulating substrate and a front electrode is bonded to a connection conductor, and the semiconductor chip is insulated from the semiconductor chip. The present invention relates to a semiconductor device mounted on a substrate.

ＩＧＢＴ（Insulated GateBipolar Transistor）モジュールに代表されるパワー半導体装置のパッケージ構造は、ケース構造と呼ばれるものが主流である。
図５は、従来のケース構造型の半導体装置の断面図である。 A package structure of a power semiconductor device typified by an IGBT (Insulated Gate Bipolar Transistor) module is mainly called a case structure.
FIG. 5 is a cross-sectional view of a conventional case structure type semiconductor device.

従来のケース構造型半導体装置では、半導体チップ１１は、はんだ層１２ａによって裏面の電極が絶縁基板１５上に形成された回路パターンと接合される。一方、表面の電極は、アルミワイヤ１３によって、同様に絶縁基板１５上に形成された回路パターンと接合される。さらに、アルミワイヤ１３によってこの回路パターンと外部電極用端子１４とが接合されて、電気的配線経路が構成される。なお、絶縁基板１５は、複数で構成される場合もある。   In the conventional case structure type semiconductor device, the semiconductor chip 11 is joined to the circuit pattern in which the electrode on the back surface is formed on the insulating substrate 15 by the solder layer 12a. On the other hand, the surface electrode is joined to the circuit pattern similarly formed on the insulating substrate 15 by the aluminum wire 13. Further, the circuit pattern and the external electrode terminal 14 are joined by the aluminum wire 13 to form an electrical wiring path. The insulating substrate 15 may be composed of a plurality.

半導体チップ１１が実装された絶縁基板１５は、はんだ層１２ｂによって放熱ベース１６上に接合され、一体となった構造が樹脂成形されたケース１７に接着されて、パッケージ構造が形成される。また、パッケージ構造では、内部の半導体チップ１１、アルミワイヤ１３、絶縁基板１５を水分、湿気、塵から保護する目的で、ケース１７内をゲル１８で封止する。   The insulating substrate 15 on which the semiconductor chip 11 is mounted is bonded onto the heat dissipation base 16 by the solder layer 12b, and the integrated structure is bonded to the resin-molded case 17 to form a package structure. In the package structure, the inside of the case 17 is sealed with a gel 18 for the purpose of protecting the internal semiconductor chip 11, the aluminum wire 13, and the insulating substrate 15 from moisture, moisture, and dust.

上記の説明のパッケージ構造に実装される縦型構造の半導体チップ１１の表面電極には、一般にアルミワイヤ１３をボンディングできるようにアルミニウム層（以下、Ａｌ層とする）が成膜されている。また、絶縁基板１５に形成された回路パターンと接合させる裏面電極は、半導体チップとの電気的接続（オーミックコンタクト）を向上させるため、アルミニウムやチタンなどで形成される。また、電極のはんだ付け性や基板に対する密着性を向上させるため、ニッケル合金薄層と貴金属薄層を順次積層させる手法が提案されている（たとえば、特許文献１参照。）。   An aluminum layer (hereinafter referred to as an Al layer) is generally formed on the surface electrode of the vertical semiconductor chip 11 mounted on the package structure described above so that the aluminum wire 13 can be bonded. Further, the back electrode bonded to the circuit pattern formed on the insulating substrate 15 is made of aluminum, titanium, or the like in order to improve electrical connection (ohmic contact) with the semiconductor chip. Further, in order to improve the solderability of the electrodes and the adhesion to the substrate, a method of sequentially laminating a nickel alloy thin layer and a noble metal thin layer has been proposed (for example, see Patent Document 1).

最近では、電気的接続として、アルミワイヤ１３によるボンディングに替わり、半導体チップ１１の表面電極に電気配線用のリードフレームや外部電極用端子などの接続導体をはんだ接合するパッケージ構造が出現している。このような構造の半導体装置では、半導体チップ１１の表面側には、接続導体をはんだ接合できるように、表面電極を形成するＡｌ層の上に、ニッケル合金層（以下、Ｎｉ層とする）と、Ｎｉ層の上に形成される金層（以下、Ａｕ層とする）が、スパッタリング法や蒸着法などを用いて成膜されている。
特開平８−１３０２２７号公報（段落番号〔０００９〕〜〔００３０〕、図１） Recently, as an electrical connection, instead of bonding with an aluminum wire 13, a package structure has appeared in which a connection conductor such as a lead frame for electric wiring or a terminal for external electrodes is soldered to the surface electrode of the semiconductor chip 11. In the semiconductor device having such a structure, a nickel alloy layer (hereinafter referred to as Ni layer) is formed on the surface of the semiconductor chip 11 on the Al layer forming the surface electrode so that the connection conductor can be soldered. A gold layer (hereinafter referred to as an Au layer) formed on the Ni layer is formed using a sputtering method, a vapor deposition method, or the like.
JP-A-8-130227 (paragraph numbers [0009] to [0030], FIG. 1)

しかしながら、スパッタリング法や蒸着法を用いて、物理的に成膜を行う場合、半導体チップの周辺に形成される周辺耐圧構造部にも成膜されてしまう。このため、周辺耐圧構造を構成するために、半導体チップ外周部のＡｌ／Ｎｉ／Ａｕ層はエッチングする必要が生じる。ところが、金属表面が安定なＡｕおよびＮｉ層のエッチングは容易ではなく、プロセスが複雑になるという問題が生じる。   However, when a physical film is formed using a sputtering method or a vapor deposition method, the film is also formed on the peripheral pressure-resistant structure portion formed around the semiconductor chip. For this reason, it is necessary to etch the Al / Ni / Au layer on the outer peripheral portion of the semiconductor chip in order to configure the peripheral breakdown voltage structure. However, etching of Au and Ni layers with a stable metal surface is not easy and causes a problem that the process becomes complicated.

また、パワー半導体チップには、運転時（大電流通電時）において、パワー半導体チップ自体に大きな熱が発生するという特徴がある。そこで、例えば、リードフレームは、電気的な接続をおこなう配線経路として機能させるとともに、半導体チップから発生する熱を表面電極側から放熱させる放熱経路としても機能させる。放熱経路としての放熱効率を確保するため、リードフレームはある程度の体積を備えなければならず、必然的に半導体チップの表面側とリードフレームとがはんだ接合する部分の面積は広くなる。また、リードフレームとはんだ接合する部分のＮｉ／Ａｕ層に空間などが生じると熱が均等に伝導されなくなるなどの問題が発生するため、放熱経路の一部となるＮｉ／Ａｕ層は均一でなければならない。しかしながら、従来のスパッタリングや蒸着による製造方法では、カバレージの問題でリードフレームと接合する広い面積部分に均一にＮｉ／Ａｕ層から成る電極膜を形成するのは容易ではないという問題がある。このため、半導体チップの表面電極とリードフレームとのはんだ接合部の信頼性の確保が難しいという問題も生じる。なお、半導体チップの表面電極に接合する外部電極用端子にも、半導体チップからの発熱によって同様の問題が生じる。   Further, the power semiconductor chip is characterized in that a large amount of heat is generated in the power semiconductor chip itself during operation (when a large current is applied). Thus, for example, the lead frame functions as a wiring path that performs electrical connection, and also functions as a heat dissipation path that dissipates heat generated from the semiconductor chip from the surface electrode side. In order to ensure heat dissipation efficiency as a heat dissipation path, the lead frame must have a certain volume, and the area of the portion where the surface side of the semiconductor chip and the lead frame are soldered inevitably increases. Also, if a space or the like is generated in the Ni / Au layer where the lead frame is soldered, heat will not be conducted evenly, so the Ni / Au layer that forms part of the heat dissipation path must be uniform. I must. However, in the conventional manufacturing method by sputtering or vapor deposition, there is a problem that it is not easy to form an electrode film composed of a Ni / Au layer uniformly over a wide area portion to be joined to the lead frame due to the problem of coverage. For this reason, there also arises a problem that it is difficult to ensure the reliability of the solder joint between the surface electrode of the semiconductor chip and the lead frame. A similar problem occurs in the external electrode terminals joined to the surface electrode of the semiconductor chip due to the heat generated from the semiconductor chip.

また、組立工程におけるはんだ付け時には、Ａｕ層とＮｉ層の一部が消失し、さらに、実使用時にパワー半導体チップから発生する熱などの熱負荷によって、はんだ接合部に金属拡散が促進され、はんだ接合部の信頼性が低下するという問題がある。   Also, during soldering in the assembly process, a part of the Au layer and the Ni layer disappears, and further, metal diffusion is promoted in the solder joint by heat load such as heat generated from the power semiconductor chip in actual use, and the solder There exists a problem that the reliability of a junction part falls.

このように、半導体チップの裏面電極のみならず、表面電極の電気的な接続にもはんだ接合を利用する半導体装置では、半導体チップの表面のＡｌ層によって形成される電極（以下、これをＡｌ電極とする）の上に、いかにＮｉ層、さらにＡｕ層を成膜するかが課題であり、これによって表面電極とリードフレームや外部電極用端子などの接続導体とのはんだ接合部の信頼性を確保することが求められている。   Thus, in a semiconductor device that uses solder bonding not only for the back surface electrode of a semiconductor chip but also for electrical connection of the surface electrode, an electrode formed by an Al layer on the surface of the semiconductor chip (hereinafter referred to as an Al electrode). The reliability of the solder joint between the surface electrode and the connection conductor such as the lead frame and the external electrode terminal is ensured. It is requested to do.

本発明はこのような点に鑑みてなされたものであり、表面電極と接続導体との間のはんだ接合部の信頼性を確保することが可能な半導体チップおよびこれを用いた半導体装置、を提供することを目的とする。   The present invention has been made in view of the above points, and provides a semiconductor chip capable of ensuring the reliability of a solder joint between a surface electrode and a connection conductor, and a semiconductor device using the same. The purpose is to do.

本発明では上記問題を解決するために、裏面電極が絶縁基板上に構成された回路パターンに接合され、表面電極が接続導体に接合される半導体チップにおいて、アルミニウム（Ａｌ）層から形成される前記表面電極と、前記表面電極の側面に形成される周辺耐圧構造と、該周辺耐圧構造の内側の前記表面電極上にジンケート法による無電解めっき法で選択的に成膜されるニッケル（Ｎｉ）層及び該ニッケル（Ｎｉ）層の上に積層される金（Ａｕ）層からなる電極膜と、を有することを特徴とする半導体チップ、が提供される。 In the present invention, in order to solve the above problem, the semiconductor chip in which the back electrode is bonded to the circuit pattern formed on the insulating substrate and the front electrode is bonded to the connection conductor is formed from an aluminum (Al) layer. A surface electrode, a peripheral breakdown voltage structure formed on a side surface of the surface electrode, and a nickel (Ni) layer selectively formed on the surface electrode inside the peripheral breakdown voltage structure by an electroless plating method using a zincate method And an electrode film made of a gold (Au) layer stacked on the nickel (Ni) layer .

このような半導体チップによれば、接続導体とはんだ接合される半導体チップ表面のＡｌ電極の上に、無電解めっき法を用いてＮｉ層を積層し、その上にＡｕ層を積層してＮｉ層とＡｕ層の２層で構成される電極膜が形成される。 According to such a semiconductor chip, an Ni layer is laminated using an electroless plating method on an Al electrode on the surface of the semiconductor chip to be soldered to the connecting conductor, and an Au layer is laminated thereon to form an Ni layer. An electrode film composed of two layers of Au and Au is formed.

ジンケート法による無電解めっき法で形成された電極膜は、半導体チップの表面Ａｌ電極の上にだけ、均一に形成される。
なお、接続導体は、半導体チップの表面電極と絶縁基板上に構成された第２の回路パターンとに接合されるリードフレームと、半導体チップの表面電極と接合し、一端を外部電極としてモジュール外部に露出させる外部電極用端子を含む、はんだ接合によって半導体チップ表面電極に接合される導体を言う。 The electrode film formed by the electroless plating method by the zincate method is uniformly formed only on the surface Al electrode of the semiconductor chip.
The connecting conductor is joined to the surface electrode of the semiconductor chip and the second circuit pattern formed on the insulating substrate, and joined to the surface electrode of the semiconductor chip, and has one end as an external electrode outside the module. A conductor that is connected to the semiconductor chip surface electrode by solder bonding, including the exposed external electrode terminals.

また、本発明では上記問題を解決するために、裏面電極が絶縁基板上に構成された回路パターンに接合され、表面電極が接続導体に接合される半導体チップを実装した半導体装置において、アルミニウム（Ａｌ）層から形成される前記表面電極と、前記表面電極の側面に形成される周辺耐圧構造と、前記表面電極上であって前記周辺耐圧構造の内側にのみジンケート法による無電解めっき法で選択的に成膜されるニッケル（Ｎｉ）層及び該ニッケル（Ｎｉ）層の上に積層された金（Ａｕ）層からなる電極膜と、を有し、かつ、前記表面電極は前記電極膜を介し鉛フリーはんだを用いて前記接続導体と接合されている半導体装置、が提供される。 In the present invention, in order to solve the above problem, in a semiconductor device mounted with a semiconductor chip in which a back electrode is bonded to a circuit pattern formed on an insulating substrate and a front electrode is bonded to a connection conductor, aluminum (Al ) The surface electrode formed from a layer, the peripheral withstand voltage structure formed on the side surface of the surface electrode, and selectively on the surface electrode by the electroless plating method by the zincate method only inside the peripheral withstand voltage structure A nickel (Ni) layer formed on the electrode and an electrode film made of a gold (Au) layer laminated on the nickel (Ni) layer , and the surface electrode is lead through the electrode film There is provided a semiconductor device joined to the connection conductor using free solder.

このような半導体装置によれば、実装される半導体チップは、表面のＡｌ電極の上に、無電解めっき法を用いて、Ｎｉ層とＡｕ層が順次積層され、Ｎｉ層とＡｕ層の２層で構成される電極膜が形成される。そして、この電極膜が形成された半導体チップの表面電極に接続導体をはんだ接合する。 According to such a semiconductor device, a semiconductor chip to be mounted is formed by sequentially depositing an Ni layer and an Au layer on an Al electrode on the surface using an electroless plating method, and two layers of an Ni layer and an Au layer. in configured electrode film is formed. Then, the connection conductor is soldered to the surface electrode of the semiconductor chip on which the electrode film is formed.

ジンケート法による無電解めっき法で形成された電極膜は半導体チップ表面Ａｌ電極上にだけ均一に形成され、これにより、配線経路とともに放熱経路として用いられるリードフレームや外部電極用端子を含む接続導体のはんだ接合部の信頼性が確保される。   The electrode film formed by the electroless plating method by the zincate method is uniformly formed only on the Al electrode on the surface of the semiconductor chip, so that the connection conductor including the lead frame used as a heat dissipation path and the terminal for the external electrode can be used together with the wiring path. Reliability of solder joints is ensured.

本発明の半導体チップは、その側面に周辺耐圧構造が形成された表面電極の上に、ジンケート法による無電解Ｎｉ／Ａｕめっき工程を用いて、接続導体とのはんだ接合用の２層電極膜（Ｎｉ／Ａｕ層）を形成する。これにより、半導体チップの表面電極面にのみ選択的にＮｉ層とＡｕ層を析出させることが可能となり、プロセスを複雑にすることなくはんだ接合用の２層電極膜を成膜できる。また、形成される２層電極膜は均一に形成されることから、放熱経路として半導体チップが発生する熱を伝導する接続導体とのはんだ接合に好適であり、この結果、半導体チップと接続導体とのはんだ接合部の信頼性が確保される。 The semiconductor chip of the present invention has a two-layer electrode film for solder bonding with a connection conductor on the surface electrode having a peripheral pressure-resistant structure formed on its side surface by using an electroless Ni / Au plating process by a zincate method ( Ni / Au layer) is formed. This makes it possible to selectively deposit the Ni layer and the Au layer only on the surface electrode surface of the semiconductor chip, and to form a two-layer electrode film for solder bonding without complicating the process. In addition, since the two-layer electrode film to be formed is formed uniformly, it is suitable for solder bonding with a connection conductor that conducts heat generated by the semiconductor chip as a heat dissipation path. As a result, the semiconductor chip and the connection conductor The reliability of the solder joint is ensured.

また、本発明の半導体装置は、表面側のＡｌ電極の上にジンケート法による無電解Ｎｉ／Ａｕめっき工程により２層電極膜が形成された半導体チップの表面電極と接続導体とをはんだ接合により接合する。２層電極膜は、Ａｌ電極面にのみ選択的、かつ均一に形成されており、半導体チップの表面電極と接続導体との間のはんだ接合部の信頼性が確保された半導体装置が提供される。 Further, the semiconductor device of the present invention joins the surface electrode of the semiconductor chip and the connection conductor, which are formed by the electroless Ni / Au plating process by the zincate method on the Al electrode on the surface side, by solder joint. To do. The two-layer electrode film is selectively and uniformly formed only on the Al electrode surface, and a semiconductor device is provided in which the reliability of the solder joint between the surface electrode of the semiconductor chip and the connection conductor is ensured. .

本発明において、半導体チップの表面電極を形成するＡｌ層の上に、無電解めっき法を用いてＡｌ電極面にのみ選択的に２層で構成される均一なＮｉおよびＡｕ層を形成させ、接続導体とのはんだ接合部の信頼性の確保を図るものである。   In the present invention, on the Al layer that forms the surface electrode of the semiconductor chip, a uniform Ni and Au layer consisting of only two layers is selectively formed only on the Al electrode surface using an electroless plating method, and connected. It is intended to ensure the reliability of the solder joint portion with the conductor.

以下、本発明の実施の形態を図面を参照して詳細に説明する。本発明は、特に、１枚以上の絶縁基板で構成され、その絶縁基板上に構成された第１回路パターンの上に半導体チップの裏面電極をはんだ接合し、半導体チップの表面電極と絶縁基板上に構成された第２回路パターンとの間をリードフレームによって接合するパワー半導体チップに好適であるので、以下、リードフレーム構造のパワー半導体チップの場合で説明する。   Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In particular, the present invention is composed of one or more insulating substrates, and the back electrode of the semiconductor chip is soldered on the first circuit pattern formed on the insulating substrate, and the front electrode of the semiconductor chip and the insulating substrate This is suitable for a power semiconductor chip that is joined to the second circuit pattern constituted by the lead frame by means of a lead frame. Hereinafter, a power semiconductor chip having a lead frame structure will be described.

図１は、本発明の実施の形態の半導体チップの構造を示す断面図である。
本発明の実施の形態の半導体チップ１は、ベアチップ２の表面側にＡｌ膜で形成されたＡｌ電極３が積層されており、Ａｌ電極３の側面には、周辺耐圧構造４を形成するポリイミド膜が成膜される。 FIG. 1 is a cross-sectional view showing the structure of a semiconductor chip according to an embodiment of the present invention.
In the semiconductor chip 1 according to the embodiment of the present invention, an Al electrode 3 formed of an Al film is laminated on the surface side of a bare chip 2, and a polyimide film that forms a peripheral withstand voltage structure 4 on the side surface of the Al electrode 3. Is deposited.

本発明では、この状態の半導体チップ１に、後述する無電解Ｎｉ／Ａｕめっき工程を施す。無電解Ｎｉ／Ａｕめっき工程により、まず、Ａｌ電極３の上にＮｉめっき層５が形成される。無電解めっき法を用いることにより、Ａｌ電極３の上に選択的にＮｉめっき層５が析出されるため、周辺耐圧構造４部分には、Ｎｉめっき層５は形成されない。また、形成されるＮｉめっき層５は、所定の厚さに均一に形成することができる。続いて、Ｎｉめっき層５の上にＡｕめっき層６が形成される。無電解めっき法を用いることによって、Ａｕめっき層６もＮｉめっき層５と同様に、Ｎｉめっき層５の上に選択的、かつ均一に形成される。   In the present invention, the semiconductor chip 1 in this state is subjected to an electroless Ni / Au plating process described later. First, the Ni plating layer 5 is formed on the Al electrode 3 by the electroless Ni / Au plating process. Since the Ni plating layer 5 is selectively deposited on the Al electrode 3 by using the electroless plating method, the Ni plating layer 5 is not formed in the peripheral pressure-resistant structure 4 portion. Moreover, the Ni plating layer 5 to be formed can be uniformly formed to a predetermined thickness. Subsequently, an Au plating layer 6 is formed on the Ni plating layer 5. By using the electroless plating method, the Au plating layer 6 is selectively and uniformly formed on the Ni plating layer 5 similarly to the Ni plating layer 5.

こうして、半導体チップ１の表面側のＡｌ電極３の上には、Ｎｉめっき層５とＡｕめっき層６とから構成される２層電極膜が形成される。
このような無電解Ｎｉ／Ａｕめっき工程を経て２層電極膜が形成された半導体チップ１は、Ａｌ電極３の上に選択的に電極膜が形成されており、周辺耐圧構造４部に電極膜が形成されることがない。このため、半導体チッププロセスにおいて行われていたＮｉ／Ａｕ層のエッチング工程を省くことができ、プロセスを簡単にすることができる。 In this way, a two-layer electrode film composed of the Ni plating layer 5 and the Au plating layer 6 is formed on the Al electrode 3 on the surface side of the semiconductor chip 1.
In the semiconductor chip 1 on which the two-layer electrode film is formed through such an electroless Ni / Au plating process, the electrode film is selectively formed on the Al electrode 3, and the electrode film is formed on the peripheral voltage-resistant structure 4 portion. Is not formed. For this reason, the etching process of the Ni / Au layer performed in the semiconductor chip process can be omitted, and the process can be simplified.

また、無電解Ｎｉ／Ａｕめっき工程によって、Ａｌ電極３上には均一な厚さの電極膜が形成されるため、広い接合面積を有するリードフレームと接合されるはんだ接合部の接合性を確保することができる。さらに、電極膜の層内部も空間などが生じることなく均一に形成されるため、電極膜内での熱伝導率も均一にすることができる。これにより、半導体チップ１が発する熱を均一にはんだ接合部を介してリードフレームへ伝導することが可能となり、はんだ接合部にかかる熱負荷にばらつきが生じない。この結果、半導体チップの表面電極とリードフレームとの間のはんだ接合の信頼性を確保することが可能となる。   In addition, since an electrode film having a uniform thickness is formed on the Al electrode 3 by the electroless Ni / Au plating process, the bondability of the solder joint portion to be joined to the lead frame having a wide joint area is ensured. be able to. Furthermore, since the inside of the electrode film layer is uniformly formed without generating a space or the like, the thermal conductivity in the electrode film can be made uniform. As a result, the heat generated by the semiconductor chip 1 can be uniformly conducted to the lead frame through the solder joint portion, and the thermal load applied to the solder joint portion does not vary. As a result, it is possible to ensure the reliability of the solder joint between the surface electrode of the semiconductor chip and the lead frame.

次に、無電解Ｎｉ／Ａｕめっき工程について説明する。Ａｌ電極３の上の無電解Ｎｉめっきは、公知の無電解めっき技術であるジンケート法またはパラジウム触媒法を用いる。以下では、ジンゲート法による無電解Ｎｉ／Ａｕめっき工程について説明する。なお、洗浄工程である水洗についての説明は省略する。   Next, the electroless Ni / Au plating process will be described. The electroless Ni plating on the Al electrode 3 uses a zincate method or a palladium catalyst method, which is a known electroless plating technique. Below, the electroless Ni / Au plating process by the gin gate method is demonstrated. In addition, the description about the water washing which is a washing | cleaning process is abbreviate | omitted.

図２は、本発明の実施の形態の半導体チップの電極膜形成の工程を示した図である。
上記の説明のように、ベアチップ２にＡｌ電極３と周辺耐圧構造４が形成された状態で、無電解Ｎｉ／Ａｕめっき工程が開始される。すなわち、表面電極にアルミワイヤがボンディングされる従来の半導体チップがウェハ状態あるいはダイシング後のチップ状態のときに、無電解Ｎｉ／Ａｕめっき工程に入る。 FIG. 2 is a diagram showing a step of forming an electrode film of the semiconductor chip according to the embodiment of the present invention.
As described above, the electroless Ni / Au plating process is started with the Al electrode 3 and the peripheral pressure-resistant structure 4 formed on the bare chip 2. That is, the electroless Ni / Au plating process is started when a conventional semiconductor chip in which an aluminum wire is bonded to the surface electrode is in a wafer state or a chip state after dicing.

第１工程として、プラズマクリーニングが行われる。ここでは、ウェハあるいはチップの状態の半導体素子をＡｒガスおよびＯ ２ ガスによってプラズマクリーニングする。
続いて、第２工程の脱脂、第４工程の酸エッチングが実施され、Ａｌ電極３の表面の汚れと、Ａｌ酸化膜が除去される。 As the first step, plasma cleaning is performed. Here, the semiconductor element in a wafer or chip state is plasma cleaned with Ar gas and O 2 gas .
Subsequently, degreasing in the second step and acid etching in the fourth step are performed to remove the dirt on the surface of the Al electrode 3 and the Al oxide film.

次に、ジンケート法によるめっきが開始される。
第６工程でジンケートを行う浴に半導体チップを浸漬することで、イオン化傾向によりＡｌが溶出し、代わりに選択的に亜鉛（Ｚｎ）がＡｌ電極３表面に析出する（置換めっき）。その後、ＺｎとＮｉを置換する。 Next, plating by the zincate method is started.
By immersing the semiconductor chip in a bath that performs zincate in the sixth step, Al is eluted due to the ionization tendency, and instead zinc (Zn) is selectively deposited on the surface of the Al electrode 3 (substitution plating). Thereafter, Zn and Ni are replaced.

第８工程で、無電解Ｎｉめっきが施され、Ｎｉめっき層５が所定の厚さになるまで、Ｎｉめっき厚を増加させる。
続く第１０工程では、Ｎｉめっき層５表面の酸化を防止するために、上記説明のような置換めっきを用いてＮｉめっき層５の上にＡｕめっき層６を成膜する。 In the eighth step, the electroless Ni plating is performed, and the Ni plating thickness is increased until the Ni plating layer 5 has a predetermined thickness.
In the subsequent tenth step, in order to prevent oxidation of the Ni plating layer 5 surface, the Au plating layer 6 is formed on the Ni plating layer 5 using displacement plating as described above.

そして、第１２工程のアニール（熱処理）が行われ、めっき工程が終了する。
このように、従来の工程に無電解Ｎｉ／Ａｕめっき工程を追加することで、周辺耐圧構造４を形成するポリイミド膜上には金属が堆積することなく、半導体チップ１の表面Ａｌ電極３上にはんだ接合に必要なＮｉめっき層５およびＡｕめっき層６の２層電極膜を成膜することが可能となる。 Then, annealing (heat treatment) in the twelfth process is performed, and the plating process is completed.
In this way, by adding an electroless Ni / Au plating process to the conventional process, no metal is deposited on the polyimide film forming the peripheral breakdown voltage structure 4, and the surface Al electrode 3 of the semiconductor chip 1 is not deposited. It is possible to form a two-layer electrode film of the Ni plating layer 5 and the Au plating layer 6 necessary for solder joining.

次に、上記の説明の半導体チップを実装した半導体装置について説明する。
図３は、本発明の実施の形態の半導体チップが実装される半導体装置の構造を示す断面図である。 Next, a semiconductor device on which the semiconductor chip described above is mounted will be described.
FIG. 3 is a cross-sectional view showing a structure of a semiconductor device on which the semiconductor chip according to the embodiment of the present invention is mounted.

半導体チップ１は、図１に示した構造を有し、表面Ａｌ電極の上には、はんだとの接合性の高い、Ｎｉめっき層とＡｕめっき層から成る２層電極膜が形成されている。
絶縁基板１５は、セラミックなどの絶縁板の両面に金属層を形成したものであり、絶縁層１５ｂを挟んで下側（半導体チップ非搭載面）に金属層１５ａ、上側（半導体チップ搭載面）に金属層１５ｃ、１５ｄを具備する構造をとる。半導体チップが接合される側の面の金属層（１５ｃ、１５ｄ）は、所定の回路パターンとして形成されている。 The semiconductor chip 1 has the structure shown in FIG. 1, and on the surface Al electrode, a two-layer electrode film composed of a Ni plating layer and an Au plating layer, which has high solderability, is formed.
The insulating substrate 15 is formed by forming metal layers on both surfaces of an insulating plate such as ceramic. The insulating layer 15b is sandwiched between the metal layer 15a on the lower side (the semiconductor chip non-mounting surface) and the upper side (the semiconductor chip mounting surface). A structure including the metal layers 15c and 15d is adopted. The metal layers (15c, 15d) on the surface to which the semiconductor chip is bonded are formed as a predetermined circuit pattern.

半導体チップ１の裏面電極は、はんだ層１２ａを介して、絶縁基板１５上に形成された第１回路パターン１５ｃに接合する。
また、半導体チップ１の表面側は、はんだ層１２ｃを介して熱伝導性と導電性を備えたリードフレーム２０ａに接合する。図の例では、リードフレーム２０ａは、放熱効率を上げるため、半導体チップ１の表面を覆うような形状を備えているが、半導体チップ１の表面に形成された均一な２層電極膜により、信頼性の高いはんだ接合配線が確保される。リードフレーム２０ａのもう一方は、絶縁基板１５の表面に形成された第２回路パターン１５ｄに接合し、これによって電気的な配線経路が構成される。また、リードフレーム２０ｂは、外部電極用端子１４との配線経路としても用いられる。 The back electrode of the semiconductor chip 1 is bonded to the first circuit pattern 15c formed on the insulating substrate 15 via the solder layer 12a.
Further, the surface side of the semiconductor chip 1 is joined to a lead frame 20a having thermal conductivity and conductivity through a solder layer 12c. In the example shown in the figure, the lead frame 20a has a shape that covers the surface of the semiconductor chip 1 in order to increase the heat dissipation efficiency. However, the lead frame 20a is reliable by the uniform two-layer electrode film formed on the surface of the semiconductor chip 1. High quality solder joint wiring is secured. The other end of the lead frame 20a is joined to the second circuit pattern 15d formed on the surface of the insulating substrate 15, thereby forming an electrical wiring path. The lead frame 20 b is also used as a wiring path with the external electrode terminal 14.

さらに、絶縁基板１５の半導体チップ１の非搭載面の金属層１５ａは、はんだ層１２ｂを介して放熱ベース１６上に接合され、一体となった構造が樹脂成形されたケース１７に接着されて、パッケージ構造が形成される。   Further, the metal layer 15a on the non-mounting surface of the semiconductor chip 1 of the insulating substrate 15 is bonded onto the heat dissipation base 16 via the solder layer 12b, and the integrated structure is bonded to the resin-molded case 17, A package structure is formed.

このような半導体装置では、半導体チップの表面電極に無電解Ｎｉ／Ａｕめっき法で形成された２層電極膜により、半導体チップの表面電極とリードフレームとの間の接合部の信頼性が確保されている。パワー半導体チップの発する熱による熱応力は、脆弱もしくは軟質な接合部に働き、半導体装置の寿命を低下させる要因となる。その接合部の信頼性が確保されることにより、結果として半導体装置の寿命の低下を防止することができる。   In such a semiconductor device, the reliability of the joint between the surface electrode of the semiconductor chip and the lead frame is ensured by the two-layer electrode film formed by the electroless Ni / Au plating method on the surface electrode of the semiconductor chip. ing. The thermal stress caused by the heat generated by the power semiconductor chip acts on a fragile or soft joint, and becomes a factor that reduces the life of the semiconductor device. By ensuring the reliability of the joint, it is possible to prevent a decrease in the lifetime of the semiconductor device as a result.

なお、上記の説明では、半導体チップの表面電極にリードフレームが接合するとしたが、半導体チップの表面電極に外部電極端子が接続する場合もある。この場合も同様に、半導体チップの表面電極に無電解Ｎｉ／Ａｕめっき法で形成された２層電極膜により、半導体チップの表面電極と外部電極用端子との間の接合部の信頼性が確保される。   In the above description, the lead frame is joined to the surface electrode of the semiconductor chip. However, an external electrode terminal may be connected to the surface electrode of the semiconductor chip. Similarly in this case, the reliability of the joint between the surface electrode of the semiconductor chip and the external electrode terminal is ensured by the two-layer electrode film formed on the surface electrode of the semiconductor chip by the electroless Ni / Au plating method. Is done.

表面電極を形成するＡｌ層の上に、無電解めっき法を用いてＮｉ層とＡｕ層から成る電極膜を形成した半導体チップを作成した。この際、形成されるＮｉめっき層の厚さが１〜１０μｍの範囲内で、厚さがそれぞれ、１、３、５、１０μｍのサンプルが作成された。   A semiconductor chip was produced in which an electrode film composed of a Ni layer and an Au layer was formed on the Al layer forming the surface electrode using an electroless plating method. At this time, samples with thicknesses of 1, 3, 5, and 10 μm were prepared within a range of 1 to 10 μm in thickness of the Ni plating layer to be formed.

次に、このサンプルを鉛フリーはんだ（Ｓｎ−３．５Ａｇ）を用いてリードフレームとはんだ接合した。はんだ付けは、１５分間かけて行われ、途中２６０℃の温度が２分間維持されるようにした。   Next, this sample was soldered to the lead frame using lead-free solder (Sn-3.5Ag). Soldering was performed for 15 minutes, and a temperature of 260 ° C. was maintained for 2 minutes.

そして、はんだ付け後のＮｉめっき層の厚さをＥＤＸ（Energy Dispersive X-ray spectroscopy；エネルギー分散Ｘ線分光法）で測定した。
図４は、めっき層形成後のＮｉめっき層とはんだ接合後のＮｉめっき層の厚さの関係を示している。図は、横軸がはんだ接合前、すなわち、無電解めっき法によって形成されたＮｉめっき層の厚さ（図では初期Ｎｉめっき厚さ）を表しており、縦軸がはんだ接合後のＮｉめっき層の厚さを示している。 Then, the thickness of the Ni plating layer after soldering was measured by EDX (Energy Dispersive X-ray spectroscopy).
FIG. 4 shows the relationship between the thickness of the Ni plating layer after formation of the plating layer and the thickness of the Ni plating layer after solder bonding. In the figure, the horizontal axis represents the thickness of the Ni plating layer formed by the electroless plating method, that is, the initial Ni plating thickness in the figure, and the vertical axis represents the Ni plating layer after the solder bonding. Indicates the thickness.

図から明らかなように、はんだ接合により、Ｎｉとはんだ中のＳｎが拡散し、Ａｌ電極との接合を担っているＮｉ層が減っている。特に、はんだ接合前のＮｉめっきが１μｍの場合、はんだ接合後にはＮｉめっき（Ｎｉのみの層）がほとんど残っていないことがわかる。このことは、はんだ接合前のＮｉめっき層の厚さが１μｍでは、はんだ接合部の接合強度を確保することができないということを示している。   As is apparent from the figure, Ni and Sn in the solder are diffused by solder bonding, and the Ni layer responsible for bonding with the Al electrode is reduced. In particular, when the Ni plating before soldering is 1 μm, it can be seen that the Ni plating (Ni-only layer) hardly remains after the soldering. This indicates that when the thickness of the Ni plating layer before soldering is 1 μm, the joining strength of the solder joint cannot be ensured.

はんだ接合部の接合強度を確保するためには、はんだ接合後のＮｉめっき層の厚さが１μｍ程度は残っていることが望ましく、図から、はんだ接合部の信頼性を確保するためには、無電解めっきの際に、Ｎｉめっき層を３μｍ以上形成する必要があることがわかる。   In order to ensure the joining strength of the solder joint, it is desirable that the thickness of the Ni plating layer after solder joining remains about 1 μm. From the figure, in order to ensure the reliability of the solder joint, It can be seen that it is necessary to form a Ni plating layer of 3 μm or more during electroless plating.

このように、半導体チップの表面Ａｌ電極の上に形成されるＮｉめっき層の厚さを３μｍ以上とすることで、半導体チップの表面電極にリードフレームをはんだ接合する際の接合部の金属拡散を防止し、機械的、電気的、熱的に信頼性の高い接合が可能となる。   In this way, by setting the thickness of the Ni plating layer formed on the surface Al electrode of the semiconductor chip to 3 μm or more, the metal diffusion of the joint portion when the lead frame is soldered to the surface electrode of the semiconductor chip is reduced. It is possible to prevent the mechanically, electrically and thermally reliable joining.

本発明の実施の形態の半導体チップの構造を示す断面図である。It is sectional drawing which shows the structure of the semiconductor chip of embodiment of this invention. 本発明の実施の形態の半導体チップの電極膜形成の工程を示した図である。It is the figure which showed the process of electrode film formation of the semiconductor chip of embodiment of this invention. 本発明の実施の形態の半導体チップが実装される半導体装置の構造を示す断面図である。It is sectional drawing which shows the structure of the semiconductor device with which the semiconductor chip of embodiment of this invention is mounted. めっき層形成後のＮｉめっき層とはんだ接合後のＮｉめっき層の厚さの関係を示している。The relationship between the Ni plating layer after plating layer formation and the thickness of the Ni plating layer after solder bonding is shown. 従来のケース構造型の半導体装置の断面図である。It is sectional drawing of the conventional case structure type semiconductor device.

１ 半導体チップ
２ ベアチップ
３ アルミニウム（Ａｌ）電極
４ 周辺耐圧構造
５ Ｎｉめっき層
６ Ａｕめっき層
１２ａ、１２ｂ、１２ｃ はんだ層
１４ 外部電極用端子
１５ 絶縁基板
１５ａ 金属層
１５ｂ 絶縁層
１５ｃ 金属層（第１回路パターン）
１５ｄ 金属層（第２回路パターン）
１６ 放熱ベース
１７ ケース
２０ａ、２０ｂ リードフレーム DESCRIPTION OF SYMBOLS 1 Semiconductor chip 2 Bare chip 3 Aluminum (Al) electrode 4 Peripheral pressure | voltage resistant structure 5 Ni plating layer 6 Au plating layer 12a, 12b, 12c Solder layer 14 Terminal for external electrodes 15 Insulating substrate 15a Metal layer 15b Insulating layer 15c Metal layer (1st Circuit pattern)
15d metal layer (second circuit pattern)
16 Heat dissipation base 17 Case 20a, 20b Lead frame

Claims (9)

裏面電極が絶縁基板上に構成された回路パターンに接合され、表面電極が接続導体に接合される半導体チップを実装した半導体装置において、
アルミニウム（Ａｌ）層から形成される前記表面電極と、
前記表面電極の側面に形成される周辺耐圧構造と、
前記表面電極上であって前記周辺耐圧構造の内側にのみジンケート法による無電解めっき法で選択的に成膜されるニッケル（Ｎｉ）層及び該ニッケル（Ｎｉ）層の上に積層された金（Ａｕ）層からなる電極膜と、を有し、かつ、
前記表面電極は前記電極膜を介し鉛フリーはんだを用いて前記接続導体と接合されている半導体装置。 In a semiconductor device mounted with a semiconductor chip in which a back electrode is bonded to a circuit pattern formed on an insulating substrate and a front electrode is bonded to a connection conductor,
The surface electrode formed from an aluminum (Al) layer;
A peripheral withstand voltage structure formed on a side surface of the surface electrode;
A nickel (Ni) layer that is selectively formed on the surface electrode by an electroless plating method using a zincate method only on the inner side of the peripheral pressure-resistant structure, and gold laminated on the nickel (Ni) layer ( Au) layer , and
The semiconductor device, wherein the surface electrode is joined to the connection conductor using lead-free solder through the electrode film. 前記周辺耐圧構造がポリイミド膜からなる請求項１記載の半導体装置。 The semiconductor device according to claim 1, wherein the peripheral breakdown voltage structure is made of a polyimide film. 前記ニッケル（Ｎｉ）層の厚さが１μｍ以上である請求項１記載の半導体装置。 The semiconductor device according to claim 1, wherein the nickel (Ni) layer has a thickness of 1 μm or more. 前記鉛フリーはんだはＳｎ−３．５Ａｇである請求項１記載の半導体装置。 The semiconductor device according to claim 1 , wherein the lead-free solder is Sn-3.5Ag. 裏面電極が絶縁基板上に構成された回路パターンに接合され、表面電極が接続導体に接合される半導体チップを実装した半導体装置の製造方法において、
アルミニウム（Ａｌ）層から形成される前記表面電極と、前記表面電極の側面に形成される周辺耐圧構造とを有するベアチップを用意する工程と、
前記表面電極上であって前記周辺耐圧構造の内側にのみ、ニッケル（Ｎｉ）層と金（Ａｕ）層とからなる電極膜をジンケート法により選択的に形成する無電解めっき工程と、
前記表面電極と前記接続導体とを、前記電極膜を介し鉛フリーはんだを用いて接合する接合工程と、を有する半導体装置の製造方法。 In a method for manufacturing a semiconductor device in which a back surface electrode is bonded to a circuit pattern configured on an insulating substrate, and a semiconductor chip in which a front surface electrode is bonded to a connection conductor is mounted.
Preparing a bare chip having the surface electrode formed from an aluminum (Al) layer and a peripheral breakdown voltage structure formed on a side surface of the surface electrode;
An electroless plating step of selectively forming an electrode film made of a nickel (Ni) layer and a gold (Au) layer only on the surface electrode and inside the peripheral pressure-resistant structure by a zincate method;
A method for manufacturing a semiconductor device, comprising: a bonding step of bonding the surface electrode and the connection conductor using lead-free solder through the electrode film. 前記周辺耐圧構造がポリイミド膜からなる請求項５記載の半導体装置の製造方法。 6. The method of manufacturing a semiconductor device according to claim 5, wherein the peripheral breakdown voltage structure is made of a polyimide film. 前記無電解めっき工程が、前記ベアチップのプラズマクリーニングを含む請求項５記載の半導体装置の製造方法。 The method of manufacturing a semiconductor device according to claim 5 , wherein the electroless plating step includes plasma cleaning of the bare chip. 前記ニッケル（Ｎｉ）層の膜厚が３μｍ以上である請求項５記載の半導体装置の製造方法。 The method of manufacturing a semiconductor device according to claim 5, wherein the nickel (Ni) layer has a thickness of 3 μm or more. 前記接合工程の後、電極膜はＮｉに前記鉛フリーはんだのＳｎが拡散した層を含み、前記ニッケル（Ｎｉ）層の膜厚は１μｍ以上である請求項５記載の半導体装置の製造方法。 The method of manufacturing a semiconductor device according to claim 5 , wherein after the joining step, the electrode film includes a layer in which Sn of the lead-free solder is diffused in Ni, and the thickness of the nickel (Ni) layer is 1 μm or more.
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