JPH09326541A - Circuit board having capacitive element - Google Patents
Circuit board having capacitive elementInfo
- Publication number
- JPH09326541A JPH09326541A JP14447396A JP14447396A JPH09326541A JP H09326541 A JPH09326541 A JP H09326541A JP 14447396 A JP14447396 A JP 14447396A JP 14447396 A JP14447396 A JP 14447396A JP H09326541 A JPH09326541 A JP H09326541A
- Authority
- JP
- Japan
- Prior art keywords
- electrode layer
- dielectric layer
- upper electrode
- thin film
- capacitive element
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/16—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は携帯電話や衛星通信
等の通信機器に搭載される容量素子付き回路基板に関す
るものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit board with a capacitor mounted on a communication device such as a mobile phone or satellite communication.
【０００２】[0002]
【従来の技術】従来、携帯電話や衛星通信等の通信機器
には電気信号の送受信回路を構成する部品の一部に容量
素子付き回路基板が使用されている。2. Description of the Related Art Conventionally, in a communication device such as a mobile phone or satellite communication, a circuit board with a capacitive element is used as a part of components constituting an electric signal transmitting / receiving circuit.
【０００３】かかる容量素子付き回路基板は一般に上面
に所定パターンの回路配線を有する絶縁基板を準備し、
該絶縁基板上にチップ容量素子を載置するとともにその
端子を回路配線に半田等を介し電気的に接続させること
によって形成されている。For such a circuit board with a capacitive element, an insulating board having a circuit wiring of a predetermined pattern on its upper surface is generally prepared.
It is formed by mounting a chip capacitor on the insulating substrate and electrically connecting its terminals to circuit wiring via solder or the like.
【０００４】しかしながら、近時、携帯電話や衛星通信
等の通信機器は小型、軽量化が急激に進み、従来の容量
素子付き回路基板では回路配線がＭｏーＭｎ法等の厚膜
形成技術により形成されており、各回路配線の幅及び隣
接する回路配線間の間隙が広いこと、チップ容量素子の
形状が大きく全体が大型となっていること等から使用す
ることができず、小型で軽量な新規の容量素子付き回路
基板が要求されるようになってきた。However, in recent years, communication devices such as mobile phones and satellite communications have been rapidly reduced in size and weight, and in conventional circuit boards with capacitive elements, circuit wiring is formed by a thick film forming technique such as Mo-Mn method. However, it cannot be used because the width of each circuit wiring and the gap between adjacent circuit wiring are wide, and the shape of the chip capacitor is large and the whole is large. The circuit board with the capacitive element has been required.
【０００５】そこで新たに絶縁基板上に薄膜形成技術に
より回路配線と容量素子を被着し、該容量素子を回路配
線に電気的に接続することによって容量素子付き回路基
板を形成することが提案されている。Therefore, it has been proposed to newly form a circuit board with a capacitive element by depositing a circuit wiring and a capacitive element on an insulating substrate by a thin film forming technique and electrically connecting the capacitive element to the circuit wiring. ing.
【０００６】かかる容量素子付き回路基板は回路配線及
び容量素子を薄膜形成技術により形成することから回路
配線の線幅及び隣接間隔を狭くし、かつ容量素子の形状
を小さく、全体を小型として小型、軽量化が急激に進む
携帯電話や衛星通信等の通信機器に使用が可能となる。In such a circuit board with a capacitive element, since the circuit wiring and the capacitive element are formed by a thin film forming technique, the line width of the circuit wiring and the adjacent space are narrowed, and the shape of the capacitive element is small. It can be used for communication devices such as mobile phones and satellite communications, which are rapidly becoming lighter.
【０００７】尚、前記容量素子付き回路基板は、その回
路配線が酸化アルミニウム質焼結体等の電気絶縁材料か
ら成る基板上にスパッタリング法や蒸着法等の薄膜形成
技術を採用することによってアルミニウム、タンタル、
タングステン、チタン、クロム等の金属材料を所定厚み
に被着し、次にこれをフォトリソグラフィー技術により
所定パターンに加工することによって形成され、また薄
膜容量素子はまず電気絶縁材料から成る基板上にスパッ
タリング法等の薄膜形成技術によりαータンタル（窒化
タンタル）を所定厚みに被着させて下部電極層を形成
し、次に前記下部電極層の表面に酸窒化タンタル等から
成る誘電物と、チタンー金やニクロムー金等の金属材料
をスパッタリング法や蒸着法等の薄膜形成技術により被
着させ、最後にこれをエッチング法により所定パターン
に加工し、誘電体層及び上部電極層とすることによって
形成されている。In the circuit board with the capacitive element, the circuit wiring of the circuit board is made of an electrically insulating material such as an aluminum oxide sintered body, and a thin film forming technique such as a sputtering method or a vapor deposition method is applied to the circuit board. tantalum,
It is formed by depositing a metal material such as tungsten, titanium, or chromium to a predetermined thickness, and then processing this into a predetermined pattern by photolithography technology.The thin film capacitive element is first formed by sputtering on a substrate made of an electrically insulating material. The lower electrode layer is formed by depositing α-tantalum (tantalum nitride) to a predetermined thickness by a thin film forming technique such as a method, and then a dielectric material such as tantalum oxynitride is formed on the surface of the lower electrode layer and titanium-gold or It is formed by depositing a metal material such as nichrome-gold by a thin film forming technique such as a sputtering method or a vapor deposition method, and finally processing this into a predetermined pattern by an etching method to form a dielectric layer and an upper electrode layer. .
【０００８】[0008]
【発明が解決しようとする課題】しかしながら、この従
来の容量素子付き回路基板においては、容量素子の下部
電極層の表面に誘電物をスパッタリング法等の薄膜形成
技術により被着させる際、下部電極層の上面と側面との
角部に誘電物を所定厚みに被着させることができず、そ
の結果、上部電極層と下部電極層とが電気的に短絡し、
容量素子としての機能の発揮させることができないとい
う欠点を誘発した。However, in this conventional circuit board with a capacitive element, when the dielectric is deposited on the surface of the lower electrode layer of the capacitive element by a thin film forming technique such as sputtering, the lower electrode layer is formed. It is not possible to deposit a dielectric material in a predetermined thickness on the corners of the upper surface and the side surface, and as a result, the upper electrode layer and the lower electrode layer are electrically shorted,
This caused a defect that the function as a capacitive element could not be exhibited.
【０００９】[0009]
【課題を解決するための手段】本発明は上記欠点に鑑み
案出されたもので、その目的は所定の静電容量値の容量
素子が形成されて成る小型、軽量の容量素子付き回路基
板を提供することにある。The present invention has been devised in view of the above-mentioned drawbacks, and an object thereof is to provide a small-sized and lightweight circuit board with a capacitive element formed by a capacitive element having a predetermined capacitance value. To provide.
【００１０】本発明は、絶縁基板上に薄膜回路配線と薄
膜容量素子を形成して成る容量素子付き回路基板であっ
て、前記薄膜容量素子は下部電極層と、該下部電極層の
表面に被着された第１誘電体層と、該第１誘電体層の上
面に被着された第１上部電極層と、前記第１誘電体層の
上面から側面にかけて被着された第２誘電体層と、該第
２誘電体層及び前記第１上部電極層表面に被着され、一
部が第１上部電極層に接続されている第２上部電極層と
で形成されていることを特徴とするものである。The present invention is a circuit board with a capacitive element formed by forming a thin film circuit wiring and a thin film capacitive element on an insulating substrate, wherein the thin film capacitive element is provided with a lower electrode layer and a surface of the lower electrode layer. The deposited first dielectric layer, the first upper electrode layer deposited on the upper surface of the first dielectric layer, and the second dielectric layer deposited from the upper surface to the side surface of the first dielectric layer. And a second upper electrode layer that is deposited on the surface of the second dielectric layer and the first upper electrode layer and is partially connected to the first upper electrode layer. It is a thing.
【００１１】また本発明は前記第２誘電体層が第１上部
電極層の陽極酸化によって形成されていることを特徴と
するものである。The present invention is also characterized in that the second dielectric layer is formed by anodic oxidation of the first upper electrode layer.
【００１２】本発明の容量素子付き回路基板によれば、
絶縁基板上に薄膜形成技術を採用することによって回路
配線及び容量素子を形成したことから回路配線の線幅及
び隣接間隔を狭くし、かつ容量素子の形状を小さく、全
体を小型として小型、軽量化が急激に進む携帯電話等の
通信機器に搭載が可能となる。According to the circuit board with a capacitive element of the present invention,
Since the circuit wiring and the capacitive element are formed by adopting the thin film forming technology on the insulating substrate, the line width of the circuit wiring and the adjacent space are narrowed, and the shape of the capacitive element is small. It can be installed in communication devices such as mobile phones, which are rapidly advancing.
【００１３】また本発明の容量素子付き回路基板によれ
ば、薄膜容量素子が下部電極層と、該下部電極層の表面
に被着された第１誘電体層と、該第１誘電体層の上面に
被着された第１上部電極層と、前記第１誘電体層の上面
から側面にかけて被着された第２誘電体層と、該第２誘
電体層及び前記第１上部電極層表面に被着され、一部が
第１上部電極層に接続されている第２上部電極層とで形
成されており、下部電極層の上面と側面との角部に被着
される第１誘電体層の厚みが薄く下部電極層と第２上部
電極層とが電気的に短絡しようとしてもその電気的短絡
は下部電極層と第２上部電極層との間に第２誘電体層が
介在していることから有効に阻止され、その結果、薄膜
容量素子としての機能を十分に発揮させることができ
る。According to the circuit board with a capacitive element of the present invention, the thin film capacitive element includes the lower electrode layer, the first dielectric layer deposited on the surface of the lower electrode layer, and the first dielectric layer. A first upper electrode layer deposited on the upper surface, a second dielectric layer deposited from the upper surface to the side surface of the first dielectric layer, and the second dielectric layer and the surface of the first upper electrode layer. A first dielectric layer that is deposited and is formed of a second upper electrode layer that is partially connected to the first upper electrode layer, and that is deposited at the corners of the upper and side surfaces of the lower electrode layer. Even if an attempt is made to electrically short-circuit the lower electrode layer and the second upper electrode layer due to the small thickness, the second dielectric layer is interposed between the lower electrode layer and the second upper electrode layer. Therefore, it is effectively prevented, and as a result, the function as the thin film capacitive element can be sufficiently exhibited.
【００１４】更に本発明の容量素子付き回路基板によれ
ば、薄膜容量素子の静電容量は第１誘電体層を間に挟ん
だ下部電極層と第２上部電極層が電気的に接続されてい
る第１上部電極層間に形成され、第２誘電体層の比誘電
率は容量素子の静電容量に大きな影響を与えないことか
ら薄膜容量素子の静電容量は第２誘電体層によって大き
くばらつくことはなく所定の値となすことができる。Further, according to the circuit board with the capacitive element of the present invention, the capacitance of the thin film capacitive element is such that the lower electrode layer and the second upper electrode layer with the first dielectric layer interposed therebetween are electrically connected. Since the relative dielectric constant of the second dielectric layer formed between the first upper electrode layers does not significantly affect the electrostatic capacitance of the capacitive element, the electrostatic capacitance of the thin film capacitive element greatly varies depending on the second dielectric layer. It can be set to a predetermined value.
【００１５】[0015]
【発明の実施の形態】次に、本発明を添付図面に基づき
詳細に説明する。図１及び図２は本発明の容量素子付き
回路基板の一実施例を示し、１は絶縁基板、２は薄膜回
路配線、３ａ、３ｂは薄膜容量素子である。Next, the present invention will be described in detail with reference to the accompanying drawings. 1 and 2 show an embodiment of a circuit board with a capacitance element of the present invention, 1 is an insulating substrate, 2 is thin film circuit wiring, and 3a and 3b are thin film capacitance elements.
【００１６】前記絶縁基板１は酸化アルミニウム質焼結
体、ムライト質焼結体、炭化珪素質焼結体、窒化アルミ
ニウム質焼結体、ガラスセラミックス焼結体等の電気絶
縁材料から成り、例えば、酸化アルミニウム質焼結体か
ら成る場合には、酸化アルミニウム、酸化珪素、酸化マ
グネシウム、酸化カルシウム等の原料粉末に適当な有機
溶剤、溶媒を添加混合して泥漿状となすとともにこれを
従来周知のドクターブレード法やカレンダーロール法等
によりシート状に成形してセラミックグリーンシート
（セラミック生シート）を得、しかる後、前記セラミッ
クグリーンシートに適当な打ち抜き加工を施し所定形状
となすとともに約１６００℃の温度で焼成することによ
って製作される。The insulating substrate 1 is made of an electrically insulating material such as an aluminum oxide sintered body, a mullite sintered body, a silicon carbide sintered body, an aluminum nitride sintered body, and a glass ceramic sintered body. In the case of using an aluminum oxide sintered body, an appropriate organic solvent or solvent is added to and mixed with a raw material powder of aluminum oxide, silicon oxide, magnesium oxide, calcium oxide or the like to form a sludge, and this is well-known to doctors. A ceramic green sheet (ceramic green sheet) is obtained by forming into a sheet shape by a blade method or a calendar roll method, and then the ceramic green sheet is subjected to an appropriate punching process to obtain a predetermined shape and at a temperature of about 1600 ° C. It is manufactured by firing.
【００１７】前記絶縁基板１は薄膜回路配線２及び薄膜
容量素子３ａ、３ｂ等を支持する支持部材として作用
し、その上面に所定パターンの薄膜回路配線２と所定静
電容量値の２つの薄膜容量素子３ａ、３ｂが被着形成さ
れている。The insulating substrate 1 acts as a supporting member for supporting the thin film circuit wiring 2, the thin film capacitive elements 3a and 3b, and the like, and the thin film circuit wiring 2 having a predetermined pattern and two thin film capacitors having a predetermined electrostatic capacitance value on the upper surface thereof. The elements 3a and 3b are adhered and formed.
【００１８】前記絶縁基板１の上面に被着形成されてい
る薄膜回路配線２は薄膜容量素子３ａ、３ｂを絶縁基板
１の上面に実装されている他の電子部品、例えば、半導
体素子４等に接続する、或いは薄膜容量素子３ａ、３ｂ
や半導体素子４を外部の電気回路に電気的に接続する作
用を為す。The thin film circuit wiring 2 adhered and formed on the upper surface of the insulating substrate 1 is mounted on the upper surface of the insulating substrate 1 with other thin film capacitor elements 3a and 3b, such as the semiconductor element 4. Connect, or thin film capacitive elements 3a, 3b
Also, it serves to electrically connect the semiconductor element 4 to an external electric circuit.
【００１９】尚、前記薄膜回路配線２は、例えばチタ
ン、クロム、ニッケル・クロム合金等から成る密着層
と、ニッケル、パラジウム、白金等から成るバリア層
と、金、銅等から成る主導体層の３層構造を有してお
り、絶縁基体１の上面に上記各金属を順次、イオンプレ
ーティング法やスパッタリング法、メッキ法、蒸着法等
の薄膜形成技術により層着し、しかる後、これら層着し
た各層をフォトリソグラフィ技術により所定パターンに
加工することによって絶縁基板１上に所定パターンに被
着形成される。The thin film circuit wiring 2 is composed of, for example, an adhesion layer made of titanium, chromium, nickel-chromium alloy, etc., a barrier layer made of nickel, palladium, platinum, etc., and a main conductor layer made of gold, copper, etc. It has a three-layer structure, and each of the above metals is sequentially layered on the upper surface of the insulating substrate 1 by a thin film forming technique such as an ion plating method, a sputtering method, a plating method, or a vapor deposition method. The respective layers are processed into a predetermined pattern by a photolithography technique to be formed in a predetermined pattern on the insulating substrate 1.
【００２０】また前記薄膜回路配線２は絶縁基板１上に
薄膜形成技術を採用することによって形成されることか
ら薄膜回路配線２の線幅及び隣接間隔を極めて狭いもの
として絶縁基板１に高密度に被着形成することが可能と
なり、その結果、薄膜回路配線２が被着形成される絶縁
基板１を小型化させることができる。Further, since the thin film circuit wiring 2 is formed on the insulating substrate 1 by adopting a thin film forming technique, the thin film circuit wiring 2 is formed on the insulating substrate 1 with a high density by assuming that the line width and the adjoining space are extremely narrow. The insulating substrate 1 on which the thin film circuit wiring 2 is adhered and formed can be miniaturized.
【００２１】更に前記絶縁基板１の上面には２つの薄膜
容量素子３ａ、３ｂが被着形成されており、該２つの薄
膜容量素子３ａ、３ｂは図２に示すように、下部電極層
５と、該下部電極層５の表面に被着された第１誘電体層
６と、該第１誘電体層６の上面に被着された第１上部電
極層７と、前記第１誘電体層６の上面から側面にかけて
被着された第２誘電体層８と、該第２誘電体層８及び前
記第１上部電極層７の表面に被着され、一部が第１上部
電極層７に接続されている第２上部電極層９とで形成さ
れており、下部電極層５と第２上部電極層８が電気的に
接続されている第１上部電極層７との間に第１誘電体層
６の比誘電率によって決定される一定の静電容量が形成
されるようになっている。Further, on the upper surface of the insulating substrate 1, two thin film capacitive elements 3a and 3b are adhered and formed, and the two thin film capacitive elements 3a and 3b are connected to a lower electrode layer 5 as shown in FIG. A first dielectric layer 6 deposited on the surface of the lower electrode layer 5, a first upper electrode layer 7 deposited on the upper surface of the first dielectric layer 6, and the first dielectric layer 6 Of the second dielectric layer 8 applied from the upper surface to the side surfaces of the first dielectric layer 8 and the surfaces of the second dielectric layer 8 and the first upper electrode layer 7, part of which is connected to the first upper electrode layer 7. A second upper electrode layer 9 which is formed between the lower electrode layer 5 and the first upper electrode layer 7 to which the second upper electrode layer 8 is electrically connected. A constant capacitance determined by the relative permittivity of 6 is formed.
【００２２】前記２つの薄膜容量素子３ａ、３ｂはその
下部電極層５が例えば、薄膜回路配線２に接続され、上
部電極層７が半導体素子４の電極や他の薄膜回路配線２
に、直接、或いはボンディングワイヤを介して接続さ
れ、これによって所定の電気回路に接続されるようにな
っている。The lower electrode layer 5 of each of the two thin film capacitive elements 3a and 3b is connected to, for example, the thin film circuit wiring 2, and the upper electrode layer 7 is an electrode of the semiconductor element 4 or another thin film circuit wiring 2.
Directly or via a bonding wire so that it is connected to a predetermined electric circuit.
【００２３】前記２つの薄膜容量素子３ａ、３ｂの絶縁
基板１上面への被着形成は、まず絶縁基板１上に下部電
極層５を被着形成する。この下部電極層５は例えば、α
ータンタル（窒化タンタル）から成り、該αータンタル
を絶縁基板１上にスパッタリング法やイオンプレーティ
ング法等の薄膜形成技術を採用することによって所定厚
み（２５０オングストローム〜１００００オングストロ
ーム）に被着させ、しかる後、これをフォトリソグラフ
ィ技術により所定パターンに加工することによって絶縁
基板１上に形成される。To deposit the two thin film capacitive elements 3a and 3b on the upper surface of the insulating substrate 1, first, the lower electrode layer 5 is deposited on the insulating substrate 1. This lower electrode layer 5 is formed of, for example, α
-Tantalum (tantalum nitride), the α-tantalum is deposited on the insulating substrate 1 to a predetermined thickness (250 angstroms to 10000 angstroms) by adopting a thin film forming technique such as a sputtering method or an ion plating method. This is formed on the insulating substrate 1 by processing it into a predetermined pattern by a photolithography technique.
【００２４】尚、前記αータンタルから成る下部電極層
５はその厚みが２５０オングストローム未満であると下
部電極層５を絶縁基板１に強固に接合させることが困難
となり、また１００００オングストロームを越えると下
部電極層５を絶縁基板１上に被着させる際に下部電極層
５内部に大きな応力が内在し、該内在応力によって下部
電極層５が絶縁基板１より剥離し易くなる傾向にある。
従って、前記αータンタルから成る下部電極層５はその
厚みを２５０オングストローム〜１００００オングスト
ロームの範囲としておくことが好ましい。[0024] Incidentally, the α lower electrode layer 5 becomes difficult to firmly join the lower electrode layer 5 and its thickness is less than 250 Å on the insulating substrate 1 made of Tantaru, also a lower Eru Yue 10000 Å When the electrode layer 5 is deposited on the insulating substrate 1, a large stress is internally present inside the lower electrode layer 5, and the internal stress tends to cause the lower electrode layer 5 to be easily peeled off from the insulating substrate 1.
Therefore, the lower electrode layer 5 made of α-tantalum preferably has a thickness in the range of 250 Å to 10000 Å.
【００２５】次に、前記下部電極層５の表面の一部を陽
極酸化処理し、一部を酸窒化タンタルに変換させること
によって第１誘電体層６を形成する。この第１誘電体層
６は下部電極層５と後述する第２上部電極層８が電気的
に接続されている第１上部電極層７との間に所定の静電
容量を形成する作用をなし、αータンタル（窒化タンタ
ル）から成る下部電極層５をクエン酸等の電解液中にプ
ラチナ板とともに浸漬させ、次に前記下部電極層５を陽
極に、プラチナ板を陰極に接続するとともに両者間に２
９０Ｖ〜５００Ｖの電圧を印加することによって形成さ
れる。Next, a part of the surface of the lower electrode layer 5 is anodized, and a part thereof is converted into tantalum oxynitride to form the first dielectric layer 6. The first dielectric layer 6 has a function of forming a predetermined capacitance between the lower electrode layer 5 and a first upper electrode layer 7 to which a second upper electrode layer 8 described later is electrically connected. The lower electrode layer 5 made of α-tantalum (tantalum nitride) is immersed in an electrolytic solution such as citric acid together with a platinum plate, and then the lower electrode layer 5 is connected to an anode and the platinum plate is connected to a cathode, and between them. Two
It is formed by applying a voltage of 90V to 500V.
【００２６】前記第１誘電体層６はその厚みを２０００
オングストローム〜１００００オングストローム程度の
薄いものとなすことができ、これによって容量素子を小
型にして、且つ静電容量が４００ｐＦ／ｍｍ2 程度の大
きなものとなすことができる。The first dielectric layer 6 has a thickness of 2000.
The thickness can be made as thin as about 1 angstrom to 10000 angstrom, whereby the capacitance element can be made small and the capacitance can be made as large as about 400 pF / mm 2 .
【００２７】そして次に前記第１誘電体６の上面に第１
上部電極層７を、第１誘電体層６の上面から側面にかけ
て第２誘電体層８を各々被着させる。Then, on the upper surface of the first dielectric 6, a first
A second dielectric layer 8 is deposited on the upper electrode layer 7 from the upper surface to the side surface of the first dielectric layer 6.
【００２８】前記第１上部電極層７は下部電極層５とで
間に配された第１誘電体層６の比誘電率によって決定さ
れる所定の静電容量を形成する作用をなし、例えば、ア
ルミニウム等からなり、第１誘電体層６の表面にイオン
プレーティング法やスパッタリング法、蒸着法等の薄膜
形成技術により被着させ、しかる後、これをフォトリソ
グラフィ技術により所定パターンに加工することによっ
て第１誘電体層６の上面に厚さ１０００オングストロー
ム乃至５０００オングストロームに被着形成される。The first upper electrode layer 7 has a function of forming a predetermined capacitance determined by the relative dielectric constant of the first dielectric layer 6 disposed between the first upper electrode layer 7 and the lower electrode layer 5. It is made of aluminum or the like, and is deposited on the surface of the first dielectric layer 6 by a thin film forming technique such as an ion plating method, a sputtering method, or a vapor deposition method, and then processed into a predetermined pattern by a photolithography technique. A thickness of 1000 Å to 5000 Å is deposited on the upper surface of the first dielectric layer 6.
【００２９】また前記第２誘電体層８は第１誘電体層６
の厚みが薄いことによって下部電極層５の上面と側面の
角部において下部電極層５と後述する第２上部電極層９
との間に電気的短絡を発生し、薄膜容量素子としての機
能を喪失するのを有効に防止する作用をなし、例えば、
酸化アルミニウム等から成り、第１誘電体層６の上面に
アルミニウムから成る第１上部電極層７を被着形成する
際、同時にアルミニウムを第１誘電体層６の上面から側
面にかけて被着形成させておき、しかる後、これを陽極
酸化処理し、酸化アルミニウムに変換させることによっ
て第１誘電体層６の上面から側面にかけて被着形成され
る。The second dielectric layer 8 is the first dielectric layer 6
Since the thickness of the lower electrode layer 5 is small, the lower electrode layer 5 and the second upper electrode layer 9 described later are formed at the corners of the upper surface and the side surface of the lower electrode layer 5.
An electrical short circuit occurs between and, and acts to effectively prevent the loss of the function as a thin film capacitive element, for example,
When the first upper electrode layer 7 made of aluminum oxide or the like and made of aluminum is deposited on the upper surface of the first dielectric layer 6, aluminum is simultaneously deposited and formed on the upper surface and side surfaces of the first dielectric layer 6. After that, this is anodized and converted into aluminum oxide, so that the first dielectric layer 6 is deposited from the upper surface to the side surface.
【００３０】前記第２誘電体層８はその厚みが１０００
オングストローム未満であると第２誘電体層８の電気絶
縁性が劣化する傾向にある。そのため前記第２誘電体層
８はその厚みを１０００オングストローム以上としてお
くことが好ましい。The second dielectric layer 8 has a thickness of 1000
If it is less than angstrom, the electric insulation of the second dielectric layer 8 tends to deteriorate. Therefore, it is preferable that the second dielectric layer 8 has a thickness of 1000 angstroms or more.
【００３１】そして最後に前記第２誘電体層８及び前記
第１上部電極層７の表面に、一部が第１上部電極層７と
電気的に接続されるようにして第２上部電極層９を被着
させる。Finally, on the surfaces of the second dielectric layer 8 and the first upper electrode layer 7, a part of the second upper electrode layer 9 is electrically connected to the first upper electrode layer 7. Put on.
【００３２】前記第２上部電極層９は第１上部電極層７
を外部電気回路に接続する作用をなし、例えばアルミニ
ウム、銅、金等の低抵抗の金属材料で形成されている。The second upper electrode layer 9 is the first upper electrode layer 7
Is connected to an external electric circuit, and is formed of a low resistance metal material such as aluminum, copper or gold.
【００３３】前記第２上部電極層９はアルミニウムや
銅、金等をイオンプレーティング法やスパッタリング
法、蒸着法等の薄膜形成技術を採用することによって第
２誘電体層８、第１上部電極層７及び絶縁基板１の表面
に被着させ、しかる後、これをフォトリソグラフィ技術
により所定パターンに加工することによって第２誘電体
層８、第１上部電極層７及び絶縁基板１の表面に２５０
オングストローム乃至５０００オングストロームの所定
厚みに被着形成される。The second upper electrode layer 9 is made of aluminum, copper, gold or the like by adopting a thin film forming technique such as an ion plating method, a sputtering method or a vapor deposition method, and the second dielectric layer 8 and the first upper electrode layer. 7 and the surface of the insulating substrate 1 and then processed into a predetermined pattern by a photolithography technique to form 250 on the surface of the second dielectric layer 8, the first upper electrode layer 7 and the insulating substrate 1.
It is deposited to a predetermined thickness of angstrom to 5000 angstrom.
【００３４】前記第２上部電極層９はまたその厚みが２
５０オングストローム未満であると第２上部電極層９を
第２誘電体層８及び第１上部電極層７に強固に接合させ
るのが困難となる傾向にあり、また５０００オングスト
ロームを越えると第２上部電極層９を形成する際に発生
する内部応力によって第２上部電極層９が第２誘電体層
８及び第１上部電極層７より剥離し易くなる傾向にあ
る。従って、前記第２上部電極層９はその厚みを２５０
オングストローム乃至５０００オングストロームの範囲
としておくことが好ましい。The second upper electrode layer 9 also has a thickness of 2
If the thickness is less than 50 Å, it tends to be difficult to firmly bond the second upper electrode layer 9 to the second dielectric layer 8 and the first upper electrode layer 7, and if it exceeds 5000 Å, the second upper electrode layer 9 becomes difficult. The second upper electrode layer 9 tends to be more easily peeled from the second dielectric layer 8 and the first upper electrode layer 7 due to the internal stress generated when the layer 9 is formed. Therefore, the second upper electrode layer 9 has a thickness of 250
It is preferably set in the range of angstrom to 5000 angstrom.
【００３５】前記第２上部電極層９はその下部に第２誘
電体層８が配されていることから下部電極層５の上面と
側面の角部において第１誘電体層６の厚みが薄いことに
起因して下部電極層５と電気的短絡を発生しよとしても
その電気的短絡は第２誘電体層８によって有効に阻止さ
れ、その結果、薄膜容量素子３ａ、３ｂの各々に容量素
子としての所定の機能を発揮させることが可能となる。Since the second dielectric layer 8 is disposed below the second upper electrode layer 9, the thickness of the first dielectric layer 6 is thin at the corners of the upper and side surfaces of the lower electrode layer 5. Even if an electric short circuit with the lower electrode layer 5 is caused due to, the electric short circuit is effectively prevented by the second dielectric layer 8, and as a result, each of the thin film capacitive elements 3a and 3b becomes a capacitive element. It is possible to exert the predetermined function of.
【００３６】また前記第２誘電体層８はその比誘電率が
薄膜容量素子３ａ、３ｂの静電容量に殆ど影響を与えな
いことから薄膜容量素子３ａ、３ｂの静電容量が前記第
２誘電体層８によって大きくばらつくことはなく、薄膜
容量素子３ａ、３ｂの静電容量を所定の値となすことが
可能となる。Further, since the relative dielectric constant of the second dielectric layer 8 has almost no influence on the electrostatic capacitance of the thin film capacitive elements 3a and 3b, the electrostatic capacitance of the thin film capacitive elements 3a and 3b is the second dielectric layer. The body layer 8 does not greatly vary, and the capacitance of the thin film capacitive elements 3a and 3b can be set to a predetermined value.
【００３７】かくして本発明の容量素子付き回路基板に
よれば、絶縁基板１上に設けた薄膜回路配線２に半導体
素子４やその他の抵抗器を搭載接続するとともに薄膜容
量素子３ａ、３ｂの下部電極層５及び上部電極層７を所
定の薄膜回路配線２や半導体素子５の電極に、直接、或
いはボンディングワイヤを介して接続すれば、携帯電話
や衛星通信等の通信機器に実装される電気回路基板とな
る。Thus, according to the circuit board with a capacitive element of the present invention, the semiconductor element 4 and other resistors are mounted and connected to the thin film circuit wiring 2 provided on the insulating substrate 1, and the lower electrodes of the thin film capacitive elements 3a and 3b are connected. If the layer 5 and the upper electrode layer 7 are connected to predetermined thin film circuit wiring 2 and electrodes of the semiconductor element 5 directly or via bonding wires, an electric circuit board mounted on communication equipment such as a mobile phone or satellite communication. Becomes
【００３８】尚、本発明は上述の実施例に限定されるも
のではなく、本発明の要旨を逸脱しない範囲であれば種
々の変更は可能であり、例えば上述の実施例では絶縁基
板１の上面に２つの薄膜容量素子３ａ、３ｂを形成した
がこれを３個以上設けてもよく、また各薄膜容量素子３
ａ、３ｂの下部電極層５、誘電体層６及び上部電極層７
を他の材料で形成してもよく、更に各薄膜容量素子３
ａ、３ｂの下部電極層５を薄膜回路配線２と同じ材料で
形成してもよい。The present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the gist of the present invention. For example, in the above-mentioned embodiments, the upper surface of the insulating substrate 1 can be changed. Although two thin film capacitive elements 3a and 3b are formed in the above, three or more thin film capacitive elements 3a and 3b may be provided.
a, 3b lower electrode layer 5, dielectric layer 6 and upper electrode layer 7
May be made of another material, and each thin film capacitive element 3
The lower electrode layers 5 of a and 3b may be formed of the same material as the thin film circuit wiring 2.
【００３９】[0039]
【発明の効果】本発明の容量素子付き回路基板によれ
ば、絶縁基板上に薄膜形成技術を採用することによって
回路配線及び容量素子を形成したことから回路配線の線
幅及び隣接間隔を狭くし、かつ容量素子の形状を小さ
く、全体を小型として小型、軽量化が急激に進む携帯電
話等の通信機器に搭載が可能となる。According to the circuit board with a capacitive element of the present invention, since the circuit wiring and the capacitive element are formed by adopting the thin film forming technique on the insulating substrate, the line width and the adjacent space of the circuit wiring can be reduced. In addition, the shape of the capacitive element is small, and the entire device is small, so that it can be mounted on communication devices such as mobile phones, which are rapidly becoming smaller and lighter.
【００４０】また本発明の容量素子付き回路基板によれ
ば、薄膜容量素子が下部電極層と、該下部電極層の表面
に被着された第１誘電体層と、該第１誘電体層の上面に
被着された第１上部電極層と、前記第１誘電体層の上面
から側面にかけて被着された第２誘電体層と、該第２誘
電体層及び前記第１上部電極層表面に被着され、一部が
第１上部電極層に接続されている第２上部電極層とで形
成されており、下部電極層の上面と側面との角部に被着
される第１誘電体層の厚みが薄く下部電極層と第２上部
電極層とが電気的に短絡しようとしてもその電気的短絡
は下部電極層と第２上部電極層との間に第２誘電体層が
介在していることから有効に阻止され、その結果、薄膜
容量素子としての機能を十分に発揮させることができ
る。According to the circuit board with a capacitive element of the present invention, the thin film capacitive element includes the lower electrode layer, the first dielectric layer deposited on the surface of the lower electrode layer, and the first dielectric layer. A first upper electrode layer deposited on the upper surface, a second dielectric layer deposited from the upper surface to the side surface of the first dielectric layer, and the second dielectric layer and the surface of the first upper electrode layer. A first dielectric layer that is deposited and is formed of a second upper electrode layer that is partially connected to the first upper electrode layer, and that is deposited at the corners of the upper and side surfaces of the lower electrode layer. Even if an attempt is made to electrically short-circuit the lower electrode layer and the second upper electrode layer due to the small thickness, the second dielectric layer is interposed between the lower electrode layer and the second upper electrode layer. Therefore, it is effectively prevented, and as a result, the function as the thin film capacitive element can be sufficiently exhibited.
【００４１】更に本発明の容量素子付き回路基板によれ
ば、薄膜容量素子の静電容量は第１誘電体層を間に挟ん
だ下部電極層と第２上部電極層が電気的に接続されてい
る第１上部電極層間に形成され、第２誘電体層の比誘電
率は容量素子の静電容量に大きな影響を与えないことか
ら薄膜容量素子の静電容量は第２誘電体層によって大き
くばらつくことはなく所定の値となすことができる。Further, according to the circuit board with a capacitive element of the present invention, the capacitance of the thin film capacitive element is such that the lower electrode layer and the second upper electrode layer with the first dielectric layer interposed therebetween are electrically connected. Since the relative dielectric constant of the second dielectric layer formed between the first upper electrode layers does not significantly affect the electrostatic capacitance of the capacitive element, the electrostatic capacitance of the thin film capacitive element greatly varies depending on the second dielectric layer. It can be set to a predetermined value.
【図１】本発明の容量素子付き回路基板の一実施例を示
す断面図である。FIG. 1 is a cross-sectional view showing an embodiment of a circuit board with a capacitor according to the present invention.
【図２】図１に示す薄膜容量素子を説明するための拡大
断面図である。FIG. 2 is an enlarged cross-sectional view for explaining the thin film capacitive element shown in FIG.
１・・・・・・絶縁基板 ２・・・・・・薄膜回路配線 ３ａ、３ｂ・・薄膜容量素子 ５・・・・・・下部電極層 ６・・・・・・第１誘電体層 ７・・・・・・第１上部電極層 ８・・・・・・第２誘電体層 ９・・・・・・第２上部電極層 1 ... Insulating substrate 2 ... Thin film circuit wiring 3a, 3b ... Thin film capacitive element 5 ... Lower electrode layer 6 ... First dielectric layer 7 ...... First upper electrode layer 8 ...... Second dielectric layer 9 ...... Second upper electrode layer
Claims (2)
を形成して成る容量素子付き回路基板であって、前記薄
膜容量素子は下部電極層と、該下部電極層の表面に被着
された第１誘電体層と、該第１誘電体層の上面に被着さ
れた第１上部電極層と、前記第１誘電体層の上面から側
面にかけて被着された第２誘電体層と、該第２誘電体層
及び前記第１上部電極層表面に被着され、一部が第１上
部電極層に接続されている第２上部電極層とで形成され
ていることを特徴とする容量素子付き回路基板。1. A circuit board with a capacitive element, comprising a thin film circuit wiring and a thin film capacitive element formed on an insulating substrate, wherein the thin film capacitive element is attached to a lower electrode layer and a surface of the lower electrode layer. A first dielectric layer, a first upper electrode layer deposited on the upper surface of the first dielectric layer, and a second dielectric layer deposited from the upper surface to the side surface of the first dielectric layer, A capacitive element characterized by being formed of the second dielectric layer and a second upper electrode layer which is deposited on the surface of the first upper electrode layer and is partially connected to the first upper electrode layer. Circuit board with.
酸化によって形成されていることを特徴とする請求項１
に記載の容量素子付き回路基板。2. The second dielectric layer is formed by anodizing the first upper electrode layer.
A circuit board with a capacitive element according to.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14447396A JP3492853B2 (en) | 1996-06-06 | 1996-06-06 | Circuit board with capacitive element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14447396A JP3492853B2 (en) | 1996-06-06 | 1996-06-06 | Circuit board with capacitive element |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH09326541A true JPH09326541A (en) | 1997-12-16 |
| JP3492853B2 JP3492853B2 (en) | 2004-02-03 |
Family
ID=15363120
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14447396A Expired - Fee Related JP3492853B2 (en) | 1996-06-06 | 1996-06-06 | Circuit board with capacitive element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3492853B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1187184A2 (en) * | 2000-08-30 | 2002-03-13 | Alps Electric Co., Ltd. | Thin film capacitor for temperature compensation |
-
1996
- 1996-06-06 JP JP14447396A patent/JP3492853B2/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1187184A2 (en) * | 2000-08-30 | 2002-03-13 | Alps Electric Co., Ltd. | Thin film capacitor for temperature compensation |
| EP1187184A3 (en) * | 2000-08-30 | 2005-05-25 | Alps Electric Co., Ltd. | Thin film capacitor for temperature compensation |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3492853B2 (en) | 2004-02-03 |
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