JPH1131869A - Circuit board with capacitive device - Google Patents
Circuit board with capacitive deviceInfo
- Publication number
- JPH1131869A JPH1131869A JP18529497A JP18529497A JPH1131869A JP H1131869 A JPH1131869 A JP H1131869A JP 18529497 A JP18529497 A JP 18529497A JP 18529497 A JP18529497 A JP 18529497A JP H1131869 A JPH1131869 A JP H1131869A
- Authority
- JP
- Japan
- Prior art keywords
- thin film
- electrode layer
- thin
- lower electrode
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
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- Parts Printed On Printed Circuit Boards (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は携帯電話や衛星通信
等の通信機器に搭載される容量素子付き回路基板に関す
るものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit board with a capacitive element mounted on a communication device such as a cellular phone or a satellite communication.
【０００２】[0002]
【従来の技術】従来、携帯電話や衛星通信等の通信機器
には電気信号の送受信回路を構成する部品の一部に容量
素子付き回路基板が使用されている。2. Description of the Related Art Hitherto, a circuit board with a capacitance element has been used as a part of a component constituting a transmission / reception circuit of an electric signal in a communication device such as a cellular phone and a satellite communication.
【０００３】かかる容量素子付き回路基板は一般に上面
に所定パターンの回路配線を有する絶縁基板を準備し、
該絶縁基板上にチップ容量素子を載置するとともにその
端子を回路配線に半田等を介し電気的に接続させること
によって形成されている。In general, such a circuit board with a capacitance element is prepared by preparing an insulating substrate having a predetermined pattern of circuit wiring on the upper surface thereof.
It is formed by placing a chip capacitor on the insulating substrate and electrically connecting its terminals to circuit wiring via solder or the like.
【０００４】しかしながら、近時、携帯電話や衛星通信
等の通信機器は小型、軽量化が急激に進み、従来の容量
素子付き回路基板では回路配線がＭｏーＭｎ法等の厚膜
形成技術により形成されており、各回路配線の幅及び隣
接する回路配線間の間隙が広いこと、チップ容量素子の
形状が大きく全体が大型となっていること等から使用す
ることができず、小型で軽量な容量素子付き回路基板が
要求されるようになってきた。In recent years, however, communication devices such as cellular phones and satellite communications have been rapidly reduced in size and weight, and in conventional circuit boards with capacitive elements, circuit wiring has been formed by a thick film forming technique such as the Mo-Mn method. Since the width of each circuit wiring and the space between adjacent circuit wirings are wide, the shape of the chip capacitor is large and the whole is large, it cannot be used, and a small and lightweight capacitor is used. A circuit board with an element has been required.
【０００５】そこで新たに絶縁基板上に薄膜形成技術を
採用することによって回路配線と容量素子とを被着形成
し、該容量素子を回路配線に電気的に接続することによ
って容量素子付き回路基板を形成することが提案されて
いる。Therefore, a circuit wiring and a capacitor are formed by applying a thin film forming technique on an insulating substrate, and the capacitor is electrically connected to the circuit wiring to form a circuit board with a capacitor. It has been proposed to form.
【０００６】かかる容量素子付き回路基板は回路配線及
び容量素子を薄膜形成技術により形成することから回路
配線の線幅及び隣接間隔を狭くすることができるととも
に容量素子の形状を小さくすることができ、その結果、
容量素子付き回路基板の全体形状を小型として、小型、
軽量化が急激に進む携帯電話や衛星通信等の通信機器に
使用することが可能となる。In such a circuit board with a capacitor, since the circuit wiring and the capacitor are formed by a thin film forming technique, the line width and the adjacent distance of the circuit wiring can be reduced, and the shape of the capacitor can be reduced. as a result,
The overall shape of the circuit board with capacitive elements is small,
It can be used for communication devices such as mobile phones and satellite communications whose weight has been rapidly reduced.
【０００７】なお、前記容量素子付き回路基板は、その
回路配線が酸化アルミニウム質焼結体等の電気絶縁材料
から成る基板上に、スパッタリング法や蒸着法等の薄膜
形成技術を採用することによってアルミニウム、タンタ
ル、タングステン、クロム等の金属材料を所定厚みに被
着し、次にこれをフォトリソグラフィー技術により所定
パターンに加工することによって形成され、また薄膜容
量素子はまず電気絶縁材料から成る基板上にスパッタリ
ング法等の薄膜形成技術によりαータンタル（窒化タン
タル）を所定厚みに被着させて薄膜下部電極層を形成
し、次に前記薄膜下部電極層の表面の一部を陽極酸化処
理し、酸化タンタルに変換させることによって誘電体層
となし、最後に前記誘電体層の上部に蒸着法やスパッタ
リング法等の薄膜形成技術によりチタンー金やニクロム
ー金等の金属材料を所定厚みに被着させるとともにこれ
をエッチング法により所定パターンに加工することによ
って薄膜上部電極層を形成することによって製作されて
いる。[0007] The circuit board with a capacitor is formed by applying a thin film forming technique such as a sputtering method or a vapor deposition method on a substrate whose circuit wiring is made of an electrically insulating material such as an aluminum oxide sintered body. , A metal material such as tantalum, tungsten, chromium, etc. is deposited to a predetermined thickness and then formed into a predetermined pattern by a photolithography technique, and the thin film capacitor is first formed on a substrate made of an electrically insulating material. A thin film lower electrode layer is formed by depositing α-tantalum (tantalum nitride) to a predetermined thickness by a thin film forming technique such as a sputtering method, and then a part of the surface of the thin film lower electrode layer is anodized to form a tantalum oxide. Into a dielectric layer by converting it into a thin film, It is fabricated by forming a thin film upper electrode layer by processing a predetermined pattern by etching the same time depositing a metal material such as Chitan Gold and Nikuromu gold to a predetermined thickness by a technique.
【０００８】[0008]
【発明が解決しようとする課題】しかしながら、この従
来の容量素子付き回路基板においては、酸化アルミニウ
ム質焼結体等の電気絶縁材料から成る基板の表面が、例
えば、酸化アルミニウムが９０〜９２％の酸化アルミニ
ウム質焼結体である場合には中心線平均粗さ（Ｒａ）が
Ｒａ＞０．３μｍとなっており、粗れていることから基
板上に薄膜形成技術を採用することによって薄膜下部電
極層を形成した場合、薄膜下部電極層の厚みに大きなバ
ラツキが発生するとともにこの薄膜下部電極層の厚みバ
ラツキに起因して薄膜下部電極層と薄膜上部電極層との
間隔が大きくバラツキ、その結果、薄膜容量素子の静電
容量値を正確に制御することができないという欠点を誘
発した。However, in this conventional circuit board with a capacitive element, the surface of a substrate made of an electrically insulating material such as an aluminum oxide sintered body has an aluminum oxide content of, for example, 90 to 92%. In the case of an aluminum oxide sintered body, the center line average roughness (Ra) is Ra> 0.3 μm, and since it is rough, a thin film lower electrode is formed by employing a thin film forming technique on a substrate. When a layer is formed, a large variation occurs in the thickness of the thin film lower electrode layer, and the distance between the thin film lower electrode layer and the thin film upper electrode layer greatly varies due to the thickness variation of the thin film lower electrode layer. As a result, A drawback is that the capacitance value of the thin film capacitor cannot be controlled accurately.
【０００９】また同時に下部電極層と上部電極層との間
隔に大きなバラツキを発生するため容量素子の電気特性
の一つである破壊電圧が大きなバラツキを有したものと
なる欠点も誘発される。At the same time, a large variation is generated in the distance between the lower electrode layer and the upper electrode layer, which causes a disadvantage that the breakdown voltage, which is one of the electrical characteristics of the capacitor, has a large variation.
【００１０】本発明は上記欠点に鑑み案出されたもの
で、その目的は薄膜下部電極層と薄膜上部電極層との間
隔を一定とし、薄膜容量素子の静電容量値を所望する正
確な値となすことができる容量素子付き回路基板を提供
することにある。The present invention has been made in view of the above-mentioned drawbacks, and has as its object to fix the distance between the thin-film lower electrode layer and the thin-film upper electrode layer and to set the capacitance of the thin-film capacitive element to a desired value. It is another object of the present invention to provide a circuit board with a capacitance element which can be used as a circuit board.
【００１１】[0011]
【課題を解決するための手段】本発明は、絶縁基板上に
薄膜回路配線と、薄膜下部電極層と誘電体層と薄膜上部
電極層とから成る複数個の薄膜容量素子を形成して成る
容量素子付き回路基板であって、前記絶縁基板の少なく
とも薄膜容量素子が形成されている表面の粗さが中心線
平均粗さ（Ｒａ）でＲａ≦０．１μｍであることを特徴
とするのである。According to the present invention, there is provided a capacitor formed by forming a thin-film circuit wiring, a plurality of thin-film capacitive elements comprising a thin-film lower electrode layer, a dielectric layer and a thin-film upper electrode layer on an insulating substrate. A circuit board with elements, wherein the surface of the insulating substrate on which at least the thin film capacitor is formed has a center line average roughness (Ra) of Ra ≦ 0.1 μm.
【００１２】本発明の容量素子付き回路基板よれば、少
なくとも薄膜容量素子が形成される絶縁基板表面の粗さ
を中心線平均粗さ（Ｒａ）でＲａ≦０．１μｍとし、平
滑なものとしたことから絶縁基板上に薄膜形成技術を採
用することによって薄膜下部電極層を形成した場合、薄
膜下部電極層はその厚みが全体にわたって均一なものと
なるとともにこの薄膜下部電極層上に形成される誘電体
層及び薄膜上部電極層の厚みも均一となり、その結果、
薄膜下部電極層と薄膜上部電極層との間隔を均一として
得られる薄膜容量素子の静電容量値を所望する値に極め
て正確に制御することが可能となる。According to the circuit board with the capacitance element of the present invention, at least the surface roughness of the insulating substrate on which the thin film capacitance element is formed is Ra ≦ 0.1 μm in terms of the center line average roughness (Ra), and is smooth. Therefore, when the thin film lower electrode layer is formed by adopting the thin film forming technology on the insulating substrate, the thickness of the thin film lower electrode layer becomes uniform over the whole and the dielectric film formed on the thin film lower electrode layer becomes uniform. The thickness of the body layer and the thin film upper electrode layer are also uniform, and as a result,
It is possible to control the capacitance value of the thin-film capacitive element obtained with a uniform distance between the thin-film lower electrode layer and the thin-film upper electrode layer to a desired value extremely accurately.
【００１３】また同時に薄膜下部電極層と薄膜上部電極
層との間隔を均一としたことから薄膜容量素子の破壊電
圧もバラツキの少ない所定の値となすことができる。At the same time, since the distance between the thin film lower electrode layer and the thin film upper electrode layer is made uniform, the breakdown voltage of the thin film capacitive element can be set to a predetermined value with less variation.
【００１４】[0014]
【発明の実施の形態】次に本発明を添付図面に基づき詳
細に説明する。図１は本発明の容量素子付き回路基板の
一実施例を示し、１は絶縁基板、２は薄膜回路配線、３
ａ、３ｂは薄膜容量素子である。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described in detail with reference to the accompanying drawings. FIG. 1 shows an embodiment of a circuit board with a capacitance element according to the present invention, wherein 1 is an insulating substrate, 2 is a thin film circuit wiring,
Reference numerals a and 3b denote thin film capacitive elements.
【００１５】前記絶縁基板１は、酸化アルミニウム質焼
結体、ムライト質焼結体、炭化珪素質焼結体、窒化アル
ミニウム質焼結体、ガラスセラミックス焼結体等の電気
絶縁材料から成り、例えば、酸化アルミニウム質焼結体
から成る場合には、酸化アルミニウム、酸化珪素、酸化
マグネシウム、酸化カルシウム等の原料粉末に適当な有
機溶剤、溶媒を添加混合して泥漿状となすとともにこれ
を従来周知のドクターブレード法やカレンダーロール法
等によりシート状に成形してセラミックグリーンシート
（セラミック生シート）を得、しかる後、前記セラミッ
クグリーンシートに適当な打ち抜き加工を施し所定形状
となすとともに約１６００℃の温度で焼成することによ
って製作される。The insulating substrate 1 is made of an electrical insulating material such as an aluminum oxide sintered body, a mullite sintered body, a silicon carbide sintered body, an aluminum nitride sintered body, a glass ceramic sintered body, etc. In the case of an aluminum oxide-based sintered body, a raw material powder such as aluminum oxide, silicon oxide, magnesium oxide, and calcium oxide is mixed with a suitable organic solvent and a solvent to form a slurry, which is conventionally known. A ceramic green sheet (ceramic green sheet) is obtained by forming the sheet into a sheet shape by a doctor blade method, a calendar roll method, or the like. Thereafter, the ceramic green sheet is subjected to an appropriate punching process to form a predetermined shape and a temperature of about 1600 ° C. It is manufactured by firing.
【００１６】前記絶縁基板１は薄膜回路配線２及び薄膜
容量素子３ａ、３ｂ等を支持する支持部材として作用
し、その上面に所定パターンの薄膜回路配線２と所定静
電容量値の２つの薄膜容量素子３ａ、３ｂが被着形成さ
れている。The insulating substrate 1 functions as a support member for supporting the thin film circuit wiring 2 and the thin film capacitance elements 3a, 3b, etc., and has on its upper surface a thin film circuit wiring 2 of a predetermined pattern and two thin film capacitors of a predetermined capacitance value. The elements 3a and 3b are formed by attachment.
【００１７】前記絶縁基板１の上面に被着形成されてい
る薄膜回路配線２は薄膜容量素子３ａ、３ｂを絶縁基板
１の上面に実装される他の電子部品、例えば、半導体素
子４等に接続する、或いは薄膜容量素子３ａ、３ｂや半
導体素子４を外部の電気回路に電気的に接続する作用を
なす。The thin film circuit wiring 2 attached to the upper surface of the insulating substrate 1 connects the thin film capacitive elements 3a and 3b to other electronic components mounted on the upper surface of the insulating substrate 1, for example, the semiconductor element 4 and the like. Or electrically connect the thin film capacitive elements 3a, 3b and the semiconductor element 4 to an external electric circuit.
【００１８】前記薄膜回路配線２は、例えば、チタン、
クロム、ニッケル・クロム合金等から成る密着層と、ニ
ッケル、パラジウム、白金等から成るバリア層と、金、
銅等から成る主導体層の３層構造を有しており、絶縁基
板１の上面に上記各金属を順次、イオンプレーティング
法やスパッタリング法、メッキ法、蒸着法等の薄膜形成
技術により被着させ、しかる後、これらの各層をフォト
リソグラフィー技術により所定パターンに加工すること
によって絶縁基板１上に所定パターンに被着形成され
る。The thin film circuit wiring 2 is made of, for example, titanium,
An adhesion layer made of chromium, nickel-chromium alloy, etc., a barrier layer made of nickel, palladium, platinum, etc., gold,
It has a three-layer structure of a main conductor layer made of copper or the like, and the above metals are sequentially deposited on the upper surface of the insulating substrate 1 by a thin film forming technique such as an ion plating method, a sputtering method, a plating method, and a vapor deposition method. Thereafter, each of these layers is processed into a predetermined pattern by photolithography, thereby forming a predetermined pattern on the insulating substrate 1.
【００１９】また前記薄膜回路配線２は絶縁基板１上に
薄膜形成技術を採用することによって形成されることか
ら薄膜回路配線２の線幅及び隣接間隔を極めて狭いもの
として絶縁基板１に高密度に被着形成することが可能と
なり、その結果、薄膜回路配線２が被着形成される絶縁
基板１を小型化させることができる。Further, since the thin film circuit wiring 2 is formed on the insulating substrate 1 by employing a thin film forming technique, the line width and the adjacent distance of the thin film circuit wiring 2 are extremely narrow, and the thin film circuit wiring 2 is formed on the insulating substrate 1 with high density. The insulating substrate 1 on which the thin film circuit wiring 2 is formed can be reduced in size.
【００２０】更に前記絶縁基板１の上面には２つの薄膜
容量素子３ａ、３ｂが被着形成されており、該２つの薄
膜容量素子３ａ、３ｂは、例えば、αータンタル（窒化
タンタル）から成る薄膜下部電極層５と、該薄膜下部電
極層５の上面に被着形成された酸窒化タンタル等から成
る誘電体層６と、該誘電体層６の表面に被着される薄膜
上部電極層７とから成り、薄膜下部電極層５と薄膜上部
電極層７との間に誘電体層６の比誘電率によって決定さ
れる一定の静電容量が形成されるようになっている。Further, two thin-film capacitors 3a and 3b are formed on the upper surface of the insulating substrate 1, and the two thin-film capacitors 3a and 3b are made of, for example, a thin film made of α-tantalum (tantalum nitride). A lower electrode layer 5, a dielectric layer 6 made of tantalum oxynitride or the like formed on the upper surface of the thin film lower electrode layer 5, and a thin film upper electrode layer 7 formed on the surface of the dielectric layer 6; The constant capacitance determined by the relative permittivity of the dielectric layer 6 is formed between the thin film lower electrode layer 5 and the thin film upper electrode layer 7.
【００２１】前記２つの薄膜容量素子３ａ、３ｂはその
薄膜下部電極層５が例えば、薄膜回路配線２に接続さ
れ、薄膜上部電極層７が半導体素子４の電極や他の薄膜
回路配線２にボンディングワイヤ８を介して接続され、
これによって所定の電気回路に接続されるようになって
いる。The two thin film capacitors 3a and 3b have their thin film lower electrode layers 5 connected, for example, to the thin film circuit wiring 2, and the thin film upper electrode layer 7 bonded to the electrodes of the semiconductor element 4 and other thin film circuit wirings 2. Connected via wire 8,
As a result, it is connected to a predetermined electric circuit.
【００２２】前記２つの薄膜容量素子３ａ、３ｂの絶縁
基板１上への被着形成は、まず絶縁基板１上に薄膜下部
電極層５を被着形成する。この薄膜下部電極層５は、例
えば、αータンタル（窒化タンタル）から成り、該αー
タンタルを絶縁基板１上にスパッタリング法やイオンプ
レーティング法の薄膜形成技術を採用することによって
所定厚み（２５０オングストローム〜１００００オング
ストローム）に被着させ、しかる後、これをフォトリソ
グラフィー技術を採用することにより所定パターンに加
工することによって絶縁基板１上に形成される。In the formation of the two thin film capacitors 3a and 3b on the insulating substrate 1, first, a thin film lower electrode layer 5 is formed on the insulating substrate 1. The thin film lower electrode layer 5 is made of, for example, α-tantalum (tantalum nitride), and the α-tantalum is formed on the insulating substrate 1 by a thin film forming technique such as a sputtering method or an ion plating method. (10000 Angstroms), and thereafter, it is formed on the insulating substrate 1 by processing it into a predetermined pattern by employing photolithography technology.
【００２３】なお、前記αータンタルから成る薄膜下部
電極層５はその厚みが２５０オングストローム未満であ
ると薄膜下部電極層５を絶縁基板１に強固に接合させる
ことが困難となり、また１００００オングストロームを
超えると薄膜下部電極層５を絶縁基板１上に被着させる
際に薄膜下部電極層５内部に大きな応力が内在し、該内
在応力によって薄膜下部電極層５が絶縁基板１より剥離
し易くなる傾向にある。従って、前記αータンタルから
成る薄膜下部電極層５はその厚みを２５０オングストロ
ーム〜１００００オングストロームの範囲としておくこ
とが好ましい。If the thickness of the thin film lower electrode layer 5 made of α-tantalum is less than 250 angstroms, it becomes difficult to firmly join the thin film lower electrode layer 5 to the insulating substrate 1, and if it exceeds 10,000 angstroms. When the thin film lower electrode layer 5 is applied on the insulating substrate 1, a large stress is present inside the thin film lower electrode layer 5, and the thin film lower electrode layer 5 tends to peel off from the insulating substrate 1 due to the intrinsic stress. . Therefore, it is preferable that the thickness of the thin film lower electrode layer 5 made of α-tantalum be in the range of 250 Å to 10000 Å.
【００２４】次に前記薄膜下部電極層５の表面の一部を
陽極酸化処理し、一部を酸窒化タンタルに変換させる、
或いは薄膜下部電極層５の表面に酸窒化タンタル等をス
パッタリング等の薄膜形成技術を採用し、所定厚みに被
着させることによって誘電体層６を形成する。この誘電
体層６は薄膜下部電極層５と薄膜上部電極層７と間に所
定の静電容量を形成する作用を為し、薄膜下部電極層５
の表面に２０００オングストローム〜１００００オング
ストロームの厚みに被着される。Next, a part of the surface of the thin film lower electrode layer 5 is anodized, and a part of the surface is converted to tantalum oxynitride.
Alternatively, the dielectric layer 6 is formed by depositing tantalum oxynitride or the like on the surface of the thin film lower electrode layer 5 to a predetermined thickness by employing a thin film forming technique such as sputtering. The dielectric layer 6 has a function of forming a predetermined capacitance between the thin film lower electrode layer 5 and the thin film upper electrode layer 7.
At a thickness of 2000 Å to 10000 Å.
【００２５】前記誘電体層６は薄膜下部電極層５の表面
の一部を陽極酸化処理することによって形成する場合、
αータンタルから成る薄膜下部電極層５をクエン酸等の
電解液中にプラチナ板とともに浸漬させ、次に前記薄膜
下部電極層５を陽極に、プラチナ板を陰極に接続すると
ともに両者間に１５０Ｖ〜７００Ｖの電圧を印加するこ
とによって行われる。When the dielectric layer 6 is formed by anodizing a part of the surface of the thin film lower electrode layer 5,
The thin film lower electrode layer 5 made of α-tantalum is immersed in an electrolytic solution such as citric acid together with a platinum plate. Then, the thin film lower electrode layer 5 is connected to the anode, the platinum plate is connected to the cathode, and 150 V to 700 V is applied between them. Is performed by applying a voltage of
【００２６】そして最後に、前記誘電体層６の表面に薄
膜上部電極層７を被着し、薄膜上部電極層７と前述の薄
膜下部電極層５との間に誘電体層６を位置させることに
よって所定の静電容量値を有する薄膜容量素子３ａ、３
ｂが絶縁基板１上の所定位置に被着形成されることとな
る。Finally, a thin film upper electrode layer 7 is deposited on the surface of the dielectric layer 6, and the dielectric layer 6 is positioned between the thin film upper electrode layer 7 and the above-mentioned thin film lower electrode layer 5. Thin film capacitors 3a, 3a having a predetermined capacitance value
b is formed at a predetermined position on the insulating substrate 1.
【００２７】前記薄膜上部電極層７は、例えば、チタン
層と金層、ニッケル・クロム層と金層等の金属材料を２
層に積層したもので形成され、従来周知の蒸着法やスパ
ッタリング法等の薄膜形成技術及びフォトリソグラフィ
ー技術を採用することによって誘電体層６の表面に被着
される。The thin film upper electrode layer 7 is made of a metal material such as a titanium layer and a gold layer, and a nickel-chromium layer and a gold layer.
It is formed by laminating layers, and is adhered to the surface of the dielectric layer 6 by adopting a conventionally known thin film forming technique such as an evaporation method or a sputtering method and a photolithography technique.
【００２８】なお、前記薄膜上部電極層７は、例えば、
チタン層と金層の２層で形成する場合、チタン層は薄膜
上部電極層７を誘電体層６上に強固に被着させる作用を
なし、その厚みが２５０オングストローム未満であると
薄膜上部電極層７を誘電体層６上に強固に被着させるの
が困難となり、また１００００オングストロームを超え
ると誘電体層６上に薄膜上部電極層７を被着させる際に
内部に大きな応力が発生するとともに内在し、該内在応
力によって薄膜容量素子３ａ、３ｂの絶縁特性、耐電圧
特性が劣化してしまう傾向にある。従って、前記薄膜上
部電極層７はチタン層と金層の２層で形成した場合、チ
タン層の厚みは２５０オングストローム〜１００００オ
ングストロームの範囲としておくことが好ましい。また
金層は、薄膜上部電極層７の主導体層として作用し、そ
の厚みが０．３μｍ未満であると後述する薄膜上部電極
層７と回路配線２等とをボンディングワイヤ８を介して
接続する際、薄膜上部電極層７とボンディングワイヤ８
との電気的接続の信頼性が低くなる傾向にあり、また１
０μｍを超えると金層を形成する際に内部に大きな応力
が発生するとともに内在し、該内在応力によって薄膜容
量素子３ａ、３ｂの絶縁特性、耐電圧特性が劣化してし
まう傾向にある。従って、前記薄膜上部電極層７をチタ
ン層と金層の２層で形成した場合、金層の厚みは０．３
μｍ〜１０μｍの範囲としておくことが好ましい。The thin film upper electrode layer 7 is formed by, for example,
When formed of two layers, a titanium layer and a gold layer, the titanium layer has a function of firmly depositing the thin film upper electrode layer 7 on the dielectric layer 6, and if the thickness is less than 250 Å, the thin film upper electrode layer is formed. It becomes difficult to firmly adhere the dielectric layer 7 on the dielectric layer 6, and if it exceeds 10,000 angstroms, a large stress is generated inside when the thin film upper electrode layer 7 is deposited on the dielectric layer 6 and the internal stress is increased. However, the intrinsic stress tends to degrade the insulation characteristics and withstand voltage characteristics of the thin film capacitors 3a and 3b. Therefore, when the thin film upper electrode layer 7 is formed of two layers of a titanium layer and a gold layer, it is preferable that the thickness of the titanium layer be in the range of 250 Å to 10000 Å. The gold layer acts as a main conductor layer of the thin film upper electrode layer 7, and connects the thin film upper electrode layer 7, which will be described later, to the circuit wiring 2 and the like via a bonding wire 8 if the thickness is less than 0.3 μm. At this time, the thin film upper electrode layer 7 and the bonding wire 8
The reliability of the electrical connection with
When the thickness exceeds 0 μm, a large stress is generated inside when forming the gold layer, and the stress is inherent therein, and the insulating property and the withstand voltage property of the thin film capacitive elements 3a and 3b tend to deteriorate due to the intrinsic stress. Therefore, when the thin film upper electrode layer 7 is formed of two layers of a titanium layer and a gold layer, the thickness of the gold layer is 0.3
It is preferable to set the range of μm to 10 μm.
【００２９】また前記薄膜容量素子３ａ、３ｂはそれを
構成する薄膜下部電極層５、誘電体層６及び薄膜上部電
極層７のいずれもが薄膜形成技術により形成されている
ことから全体の形状が小さく、小型、軽量化が急激に進
む携帯電話や衛星通信等の通信機器に搭載が可能とな
る。Since the thin film capacitive elements 3a and 3b are all formed by a thin film forming technique, all of the thin film lower electrode layer 5, the dielectric layer 6 and the thin film upper electrode layer 7 are formed by a thin film forming technique. It can be mounted on communication devices such as mobile phones and satellite communications, which are rapidly becoming smaller, smaller and lighter.
【００３０】更に前記薄膜容量素子３ａ、３ｂが被着形
成されている絶縁基板１はその薄膜容量素子３ａ、３ｂ
が被着形成されている領域の表面が中心線平均粗さ（Ｒ
ａ）でＲａ≦０．１μｍの平滑なものとなっており、こ
れによって絶縁基板１上に薄膜形成技術を採用すること
によって薄膜下部電極層５を形成した場合、薄膜下部電
極層５はその厚みが全体にわたって均一なものとなると
ともにこの薄膜下部電極層５上に形成される誘電体層６
及び薄膜上部電極層７の厚みも均一となり、その結果、
薄膜下部電極層５と薄膜上部電極層７との間隔を均一と
して得られる薄膜容量素子３ａ、３ｂの静電容量値を所
望する値に極めて正確に制御することが可能となる。Further, the insulating substrate 1 on which the thin film capacitors 3a, 3b are adhered is formed by the thin film capacitors 3a, 3b
Has a center line average roughness (R
In the case of a), Ra ≦ 0.1 μm is smooth, and when the thin film lower electrode layer 5 is formed on the insulating substrate 1 by employing the thin film forming technique, the thin film lower electrode layer 5 has a thickness of Is uniform over the whole, and a dielectric layer 6 formed on the thin film lower electrode layer 5 is formed.
Also, the thickness of the thin film upper electrode layer 7 becomes uniform, and as a result,
It is possible to control the capacitance values of the thin film capacitive elements 3a and 3b, which can obtain the uniform distance between the thin film lower electrode layer 5 and the thin film upper electrode layer 7, to a desired value extremely accurately.
【００３１】前記薄膜容量素子３ａ、３ｂが被着形成さ
れる絶縁基板１の表面を中心線平均粗さ（Ｒａ）でＲａ
≦０．１μｍの平滑なものとするには、例えば、絶縁基
板１の表面に対し、鏡面研磨等の機械的研磨処理等を施
すことによって行われる。The surface of the insulating substrate 1 on which the thin film capacitive elements 3a and 3b are formed is defined by a center line average roughness (Ra).
In order to achieve a smoothness of ≦ 0.1 μm, for example, the surface of the insulating substrate 1 is subjected to a mechanical polishing process such as mirror polishing or the like.
【００３２】また前記薄膜容量素子３ａ、３ｂが被着形
成される絶縁基板１の表面が中心線平均粗さ（Ｒａ）で
Ｒａ＞０．１μｍとなると絶縁基板１上に薄膜形成技術
を採用することによって薄膜下部電極層５を形成した場
合、薄膜下部電極層５の厚みに大きなバラツキが発生す
るとともにこの薄膜下部電極層５の厚みバラツキに起因
して薄膜下部電極層５と薄膜上部電極層７との間隔が大
きくバラツキ、その結果、薄膜容量素子３ａ、３ｂの静
電容量値を所望する値に正確に制御することができなく
なる。従って、前記薄膜容量素子３ａ、３ｂが被着形成
される絶縁基板１の表面は中心線平均粗さ（Ｒａ）でＲ
ａ≦０．１μｍの平滑なものに特定される。When the surface of the insulating substrate 1 on which the thin film capacitive elements 3a and 3b are formed is Ra> 0.1 μm in center line average roughness (Ra), a thin film forming technique is employed on the insulating substrate 1. Thus, when the thin film lower electrode layer 5 is formed, a large variation occurs in the thickness of the thin film lower electrode layer 5 and the thickness variation of the thin film lower electrode layer 5 causes the thin film lower electrode layer 5 and the thin film upper electrode layer 7 to vary. , The distance between the thin film capacitors 3a and 3b cannot be accurately controlled to a desired value. Accordingly, the surface of the insulating substrate 1 on which the thin-film capacitive elements 3a and 3b are formed is R in center line average roughness (Ra).
It is specified to be smooth with a ≦ 0.1 μm.
【００３３】かくして上述の容量素子付き回路基板によ
れば、絶縁基板１上に設けた薄膜回路配線２に半導体素
子４やその他の抵抗器等を搭載接続するとともに薄膜容
量素子３ａ、３ｂの薄膜下部電極層５及び薄膜上部電極
層７を所定の薄膜回路配線２や半導体素子４の電極に直
接、或いはボンディングワイヤ８を介して接続すれば、
携帯電話や衛星通信等の通信機器に実装される電気回路
基板となる。Thus, according to the above-described circuit board with a capacitance element, the semiconductor element 4 and other resistors are mounted and connected to the thin film circuit wiring 2 provided on the insulating substrate 1 and the thin film lower parts of the thin film capacitance elements 3a and 3b are connected. If the electrode layer 5 and the thin film upper electrode layer 7 are connected to the predetermined thin film circuit wiring 2 or the electrode of the semiconductor element 4 directly or via a bonding wire 8,
It is an electric circuit board mounted on communication devices such as mobile phones and satellite communications.
【００３４】なお、本発明は上述の実施例に限定される
ものではなく、本発明の要旨を逸脱しない範囲であれば
種々の変更は可能であり、例えば図２に示す如く、薄膜
下部電極層５と誘電体層６と薄膜上部電極層７とで形成
される薄膜容量素子３の誘電体層６と薄膜上部電極層７
との間で、薄膜下部電極層５の上面と側面との角部に対
向する領域にふっ素樹脂やポリフェニレンエーテル樹脂
等の比誘電率が３（室温１ＭＨｚ）以下の電気絶縁性の
材料から成る絶縁物９を介在させておくと薄膜上部電極
層７と薄膜下部電極層５との間の電気的短絡が発生する
のを有効に防止することができる。また図３に示すよう
に薄膜容量素子３を薄膜下部電極層５と該薄膜下部電極
層５の表面に被着された酸窒化タンタル等から成る第１
誘電体層６ａと、該第１誘電体層６ａの上面に被着され
た第１薄膜上部電極層７ａと、前記第１誘電体層６ａの
上面から側面にかけて被着された第２誘電体層６ｂと、
該第２誘電体層６ｂ及び前記第１薄膜上部電極層７ａ表
面に被着され、一部が第１薄膜上部電極層７ａに接続さ
れている第２薄膜上部電極層７ｂとで形成すると、薄膜
下部電極層５の上面と側面との角部に被着される第１誘
電体層６ａの厚みが薄く、薄膜下部電極層５と第２薄膜
上部電極層７ｂとが電気的に短絡しようとしてもその電
気的短絡は薄膜下部電極層５と第２薄膜上部電極層７ｂ
との間に第２誘電体層６ｂが介在していることから有効
に阻止され、これによって薄膜容量素子としての機能を
十分に発揮させることができる。The present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the gist of the present invention. For example, as shown in FIG. Dielectric layer 6 and thin-film upper electrode layer 7 of thin-film capacitive element 3 formed of layer 5, dielectric layer 6 and thin-film upper electrode layer 7
In a region opposed to the corner between the upper surface and the side surface of the thin film lower electrode layer 5, an insulating material made of an electrically insulating material such as a fluororesin or a polyphenylene ether resin having a relative dielectric constant of 3 (room temperature 1 MHz) or less. The interposition of the object 9 can effectively prevent an electrical short circuit between the thin film upper electrode layer 7 and the thin film lower electrode layer 5 from occurring. As shown in FIG. 3, the thin-film capacitive element 3 is formed of a first thin-film lower electrode layer 5 and a first
A dielectric layer 6a, a first thin film upper electrode layer 7a applied on the upper surface of the first dielectric layer 6a, and a second dielectric layer applied from the upper surface to the side surface of the first dielectric layer 6a 6b,
When formed with the second dielectric layer 6b and the second thin film upper electrode layer 7b which is attached to the surface of the first thin film upper electrode layer 7a and partially connected to the first thin film upper electrode layer 7a, the thin film Even when the thickness of the first dielectric layer 6a attached to the corner between the upper surface and the side surface of the lower electrode layer 5 is small, and the thin film lower electrode layer 5 and the second thin film upper electrode layer 7b try to electrically short-circuit. The electrical short circuit occurs between the thin film lower electrode layer 5 and the second thin film upper electrode layer 7b.
Is effectively prevented because the second dielectric layer 6b is interposed therebetween, whereby the function as a thin film capacitor can be sufficiently exhibited.
【００３５】[0035]
【発明の効果】本発明の容量素子付き回路基板よれば、
少なくとも薄膜容量素子が形成される絶縁基板表面の粗
さを中心線平均粗さ（Ｒａ）でＲａ≦０．１μｍとし、
平滑なものとしたことから絶縁基板上に薄膜形成技術を
採用することによって薄膜下部電極層を形成した場合、
薄膜下部電極層はその厚みが全体にわたって均一なもの
となるとともにこの薄膜下部電極層上に形成される誘電
体層及び薄膜上部電極層の厚みも均一となり、その結
果、薄膜下部電極層と薄膜上部電極層との間隔を均一と
して得られる薄膜容量素子の静電容量値を所望する値に
極めて正確に制御することが可能となる。According to the circuit board with the capacitance element of the present invention,
At least the roughness of the surface of the insulating substrate on which the thin film capacitive element is formed is Ra ≦ 0.1 μm in terms of center line average roughness (Ra),
When the thin film lower electrode layer is formed by adopting the thin film forming technology on the insulating substrate because it is smooth,
The thickness of the thin film lower electrode layer becomes uniform throughout, and the thicknesses of the dielectric layer and the thin film upper electrode layer formed on the thin film lower electrode layer are also uniform. As a result, the thin film lower electrode layer and the thin film upper It is possible to control the capacitance value of the thin-film capacitance element having a uniform distance from the electrode layer to a desired value extremely accurately.
【００３６】また本発明の容量素子付き回路基板よれ
ば、薄膜下部電極層と薄膜上部電極層との間隔が均一と
なることから薄膜容量素子の破壊電圧もバラツキの少な
い所定の値となすことができる。Further, according to the circuit board with the capacitor element of the present invention, since the distance between the thin film lower electrode layer and the thin film upper electrode layer becomes uniform, the breakdown voltage of the thin film capacitor element can be set to a predetermined value with little variation. it can.
【００３７】更に本発明の容量素子付き回路基板よれ
ば、絶縁基板上に薄膜形成技術を採用することによって
回路配線及び容量素子を形成したことから回路配線の線
幅及び隣接間隔を狭くすることができるとともに容量素
子の形状を小さくすることができ、その結果、容量素子
付き回路基板の全体形状を小型として、小型、軽量化が
急激に進む携帯電話や衛星通信等の通信機器に使用する
ことが可能となる。Further, according to the circuit board with the capacitance element of the present invention, since the circuit wiring and the capacitance element are formed by adopting the thin film forming technique on the insulating substrate, the line width and the adjacent distance of the circuit wiring can be reduced. As a result, the shape of the capacitive element can be reduced, and as a result, the overall shape of the circuit board with the capacitive element can be reduced, so that it can be used for communication devices such as cellular phones and satellite communications, which are rapidly becoming smaller and lighter. It becomes possible.
【図１】本発明の容量素子付き回路基板の一実施例を示
す断面図である。FIG. 1 is a cross-sectional view showing one embodiment of a circuit board with a capacitance element of the present invention.
【図２】本発明の他の実施例を説明するための要部拡大
断面図である。FIG. 2 is an enlarged sectional view of a main part for explaining another embodiment of the present invention.
【図３】本発明の他の実施例を説明するための要部拡大
断面図である。FIG. 3 is an enlarged sectional view of a main part for explaining another embodiment of the present invention.
１・・・・・・・・絶縁基板 ２・・・・・・・・薄膜回路配線 ３ａ、３ｂ・・・・薄膜容量素子 ５・・・・・・・・薄膜下部電極層 ６・・・・・・・・誘電体層 ７・・・・・・・・薄膜上部電極層 1 ... Insulating substrate 2 ... Thin film circuit wiring 3a, 3b ... Thin film capacitive element 5 ... Thin film lower electrode layer 6 ... ..... Dielectric layer 7 ........ Thin film upper electrode layer
Claims (1)
極層と誘電体層と薄膜上部電極層とから成る複数個の薄
膜容量素子を形成して成る容量素子付き回路基板であっ
て、前記絶縁基板の少なくとも薄膜容量素子が形成され
ている表面の粗さが中心線平均粗さ（Ｒａ）でＲａ≦
０．１μｍであることを特徴とする容量素子付き回路基
板。1. A circuit board with a capacitive element, comprising a plurality of thin-film capacitive elements comprising a thin-film circuit wiring, a thin-film lower electrode layer, a dielectric layer and a thin-film upper electrode layer formed on an insulating substrate. The roughness of at least the surface of the insulating substrate on which the thin film capacitive element is formed has a center line average roughness (Ra) of Ra ≦
A circuit board with a capacitance element having a thickness of 0.1 μm.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18529497A JPH1131869A (en) | 1997-07-10 | 1997-07-10 | Circuit board with capacitive device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18529497A JPH1131869A (en) | 1997-07-10 | 1997-07-10 | Circuit board with capacitive device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH1131869A true JPH1131869A (en) | 1999-02-02 |
Family
ID=16168351
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18529497A Pending JPH1131869A (en) | 1997-07-10 | 1997-07-10 | Circuit board with capacitive device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH1131869A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6689498B2 (en) * | 2000-12-04 | 2004-02-10 | Kabushiki Kaisha Toshiba | Aluminum nitride substrate and thin film substrate therewith, and manufacturing method thereof |
-
1997
- 1997-07-10 JP JP18529497A patent/JPH1131869A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6689498B2 (en) * | 2000-12-04 | 2004-02-10 | Kabushiki Kaisha Toshiba | Aluminum nitride substrate and thin film substrate therewith, and manufacturing method thereof |
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