JPH09307200A - Printed circuit board for evaluating semiconductor device - Google Patents
Printed circuit board for evaluating semiconductor deviceInfo
- Publication number
- JPH09307200A JPH09307200A JP12299196A JP12299196A JPH09307200A JP H09307200 A JPH09307200 A JP H09307200A JP 12299196 A JP12299196 A JP 12299196A JP 12299196 A JP12299196 A JP 12299196A JP H09307200 A JPH09307200 A JP H09307200A
- Authority
- JP
- Japan
- Prior art keywords
- circuit board
- printed circuit
- surface mount
- semiconductor device
- semiconductor devices
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0286—Programmable, customizable or modifiable circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/111—Pads for surface mounting, e.g. lay-out
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3421—Leaded components
Landscapes
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Structure Of Printed Boards (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は表面実装型半導体装
置のアウターリードはんだ濡れ性、はんだ接続強度評
価、はんだ接続部の熱応力評価およびイオンマイグレー
ション評価等に用いるための半導体装置の評価用プリン
ト基板に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device evaluation printed circuit board for use in outer lead solder wettability, solder connection strength evaluation, solder connection part thermal stress evaluation, ion migration evaluation, etc. of surface mount semiconductor devices. It is about.
【０００２】[0002]
【従来の技術】近年、電子機器の小型化、軽量化に伴
い、電子部品の高密度な実装技術が求められている。な
かでも、表面実装技術は比較的容易に高密度実装が得ら
れる手段として広く用いられている。2. Description of the Related Art In recent years, with the miniaturization and weight reduction of electronic devices, there has been a demand for high-density mounting technology for electronic components. Above all, the surface mounting technique is widely used as a means for achieving high-density mounting relatively easily.
【０００３】半導体装置においても、表面実装型半導体
装置の小型化、薄型化が著しく、アウターリードピンの
微細化やリードピンピッチの狭小化がますます進んでい
る。Also in the semiconductor device, the surface mounting type semiconductor device is remarkably miniaturized and thinned, and the outer lead pins are becoming finer and the lead pin pitch is becoming narrower.
【０００４】同時に、表面実装型半導体装置のプリント
基板実装後のはんだ接続部の面積が微細となり、また、
はんだ接続部のピッチも狭小となり、安定なはんだ濡れ
性、はんだ接続強度の確保が品質、信頼性の面で重要課
題といえる。At the same time, the area of the solder connection portion after mounting the printed circuit board of the surface mount type semiconductor device becomes fine, and
Since the pitch of the solder joints is also narrowed, ensuring stable solder wettability and solder joint strength is an important issue in terms of quality and reliability.
【０００５】このため、表面実装型半導体装置のアウタ
ーリードのはんだ接続部の有効な評価手法が必要となっ
ている。Therefore, there is a need for an effective evaluation method for the solder connection portion of the outer lead of the surface mount semiconductor device.
【０００６】以下、従来の表面実装型半導体装置のアウ
ターリードはんだ接続部の評価用プリント基板について
説明する。A printed circuit board for evaluation of the outer lead solder connection portion of the conventional surface mount semiconductor device will be described below.
【０００７】図４は従来の半導体装置の評価用プリント
基板の平面図である。１はプリント基板、２はプリント
基板上のランドである。FIG. 4 is a plan view of a conventional printed circuit board for evaluation of a semiconductor device. Reference numeral 1 is a printed circuit board, and 2 is a land on the printed circuit board.
【０００８】但し、プリント基板上のランド以外の部分
にはレジスト薄膜が塗布されており、ランド部（金属
部）は表面に露出している。However, a resist thin film is applied to a portion other than the land on the printed board, and the land portion (metal portion) is exposed on the surface.
【０００９】従来の半導体装置の評価用プリント基板は
各種外形寸法、およびリードピンピッチの異なる表面実
装型半導体装置が個別に実装されるものである。A conventional printed circuit board for evaluation of a semiconductor device is one in which surface mounting type semiconductor devices having various outer dimensions and lead pin pitches are individually mounted.
【００１０】[0010]
【発明が解決しようとする課題】しかしながら、上記、
従来の構成では、各種外形寸法およびリードピンピッチ
の異なる表面実装型半導体装置が個別に実装されるもの
であったので、プリント基板の外形寸法が実装される表
面実装型半導体装置の個数によって異なり、大面積とな
るため、はんだ濡れ性等のはんだ接続部の評価を実施す
る際、パッケージ毎に切り離す必要がある。また、多種
にわたる表面実装型半導体装置の外形寸法、リードピン
ピッチ毎にプリント基板を作成しなければならないた
め、その分、コストがかかるという問題があった。SUMMARY OF THE INVENTION However,
In the conventional configuration, surface mounting type semiconductor devices having various outer dimensions and lead pin pitches are individually mounted, so that the outer dimensions of the printed circuit board may vary depending on the number of surface mounting type semiconductor devices to be mounted. Because of the area, it is necessary to separate each package when evaluating the solder connection part such as solder wettability. In addition, there is a problem in that the printed circuit board has to be formed for each of various external dimensions and lead pin pitches of the surface mount type semiconductor devices, which causes a cost increase.
【００１１】本発明は、上記、従来の問題を解決するも
ので、一定のコンパクトサイズの同一プリント基板上に
数種類の表面実装型半導体装置の実装に対応可能な、半
導体装置の評価用プリント基板を提供することを目的と
する。The present invention solves the above-mentioned conventional problems, and provides a semiconductor device evaluation printed circuit board capable of mounting several types of surface mount semiconductor devices on the same compact printed circuit board. The purpose is to provide.
【００１２】[0012]
【課題を解決するための手段】この目的を達成するため
に、本発明の半導体装置の評価用プリント基板は外形寸
法の異なる表面実装型半導体装置を各種リードピンピッ
チ毎に同一プリント基板上にランドが配置され、さら
に、各種外形寸法の異なる表面実装型半導体装置のアウ
ターリードはんだ接続部の電気的特性がとれるようにラ
ンド間を金属配線した構成を有している。In order to achieve this object, in the printed circuit board for evaluation of the semiconductor device of the present invention, surface mount type semiconductor devices having different outer dimensions are mounted on the same printed circuit board at various lead pin pitches. Further, the lands are provided with metal wiring so that the electrical characteristics of the outer lead solder connection portions of the surface mounting type semiconductor devices having different outer dimensions can be obtained.
【００１３】[0013]
【発明の実施の形態】この構成によって、同一プリント
基板上に外形寸法の異なる表面実装型半導体装置を実装
できるものであり、また、一定のコンパクトサイズのプ
リント基板であるため、アウターリードはんだ接続部の
評価の際、表面実装型半導体装置毎にプリント基板を切
り離す必要がなく、一種類のプリント基板で数種類の表
面実装型半導体装置のアウターリードはんだ接続部の評
価を実施できる。With this structure, surface mount type semiconductor devices having different outer dimensions can be mounted on the same printed circuit board, and since the printed circuit board is of a constant compact size, the outer lead solder connection portion At the time of evaluation, it is not necessary to separate the printed circuit board for each surface mount type semiconductor device, and it is possible to evaluate the outer lead solder connection portions of several kinds of surface mount type semiconductor devices with one kind of printed circuit board.
【００１４】以下、本発明の一実施形態について、図面
を参照しながら説明する。図１は本発明の一実施形態に
おける半導体装置の評価用プリント基板の平面図であ
る。An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a plan view of a printed circuit board for evaluation of a semiconductor device according to an embodiment of the present invention.
【００１５】１はプリント基板、２はプリント基板上の
ランド、３はランド間を結ぶ金属配線である。Reference numeral 1 is a printed circuit board, 2 is a land on the printed circuit board, and 3 is a metal wiring connecting the lands.
【００１６】但し、プリント基板上のランド以外の部分
にはレジスト薄膜が塗布されており、ランド部（金属
部）は表面に露出している。これは従来例の構成と同じ
である。However, a resist thin film is applied to the portion other than the land on the printed board, and the land portion (metal portion) is exposed on the surface. This is the same as the configuration of the conventional example.
【００１７】以上のように構成された本実施形態の半導
体装置の評価用プリント基板は同一リードピンピッチの
表面実装型半導体装置の各種外形寸法に合わせて、ラン
ドを配置しているため、同一プリント基板で数種類の表
面実装型半導体装置の実装が対応可能である。In the printed circuit board for evaluation of the semiconductor device of the present embodiment configured as described above, the lands are arranged according to various external dimensions of the surface mount type semiconductor device having the same lead pin pitch. It is possible to mount several types of surface mount semiconductor devices.
【００１８】さらに、プリント基板の外周に設けられた
ランドに各種表面実装型半導体装置のアウターリードに
対応するランドがそれぞれ金属細線によって結線され、
電気的導通がとれるため、外部よりバイアスを印加する
ことができ、表面実装型半導体装置の内部発熱による、
アウターリードはんだ接続部の熱疲労特性の評価が実施
できる。また、外部環境の温度変化によるアウターリー
ドはんだ接続部の熱応力特性の評価やアウターリードピ
ン間のイオンマイグレーション評価が実施可能である。Further, lands corresponding to the outer leads of various surface mount type semiconductor devices are connected to the lands provided on the outer periphery of the printed circuit board by thin metal wires, respectively.
Since electrical conduction can be achieved, a bias can be applied from the outside, and due to internal heat generation of the surface mount semiconductor device,
The thermal fatigue characteristics of the outer lead solder joints can be evaluated. Further, it is possible to evaluate the thermal stress characteristics of the outer lead solder joint portion due to the temperature change of the external environment and the ion migration evaluation between the outer lead pins.
【００１９】図２は本発明の一実施形態における半導体
装置の評価用プリント基板のコネクターによる外部バイ
アス印加方法を示す。FIG. 2 shows an external bias applying method using a connector of a printed circuit board for evaluation of a semiconductor device according to an embodiment of the present invention.
【００２０】なお、本実施形態では表面実装型半導体装
置はＱＦＰタイプでリードピンピッチが０．６５mmの場
合を示した。In this embodiment, the surface mount type semiconductor device is the QFP type and the lead pin pitch is 0.65 mm.
【００２１】さらに、ＱＦＰタイプのリードピンピッチ
が０．５mmの場合を図３に示す。１はプリント基板、２
はプリント基板上のランド、３はランド間を結ぶ金属配
線である。Further, FIG. 3 shows the case where the QFP type lead pin pitch is 0.5 mm. 1 is a printed circuit board, 2
Is a land on the printed circuit board, and 3 is a metal wiring connecting the lands.
【００２２】リードピンピッチ０．５mmピッチの場合も
０．６５mmピッチの場合と同様の効果が得られる。In the case of the lead pin pitch of 0.5 mm, the same effect as in the case of 0.65 mm pitch can be obtained.
【００２３】[0023]
【発明の効果】本発明は同一リードピンピッチの表面実
装型半導体装置の各種外形寸法に合わせて、同一プリン
ト基板上にランドを配置しており、さらに、プリント基
板の外周に設けられたランドに、各種表面実装型半導体
装置のアウターリードに対応するランドがそれぞれ金属
細線により結線されていることにより、コンパクトサイ
ズの同一基板上に数種類の表面実装型半導体装置が実現
でき、なおかつ、外部よりバイアスを印加することがで
きる優れた半導体装置の評価用プリント基板を実現でき
るものである。According to the present invention, lands are arranged on the same printed circuit board according to various external dimensions of the surface mount type semiconductor device having the same lead pin pitch, and further, lands are provided on the outer periphery of the printed circuit board. Since the lands corresponding to the outer leads of various surface-mount type semiconductor devices are connected by thin metal wires, several types of surface-mount type semiconductor devices can be realized on the same compact substrate, and bias is applied from the outside. It is possible to realize an excellent printed circuit board for evaluation of a semiconductor device that can be manufactured.
【図１】本発明の一実施形態における半導体装置の評価
用プリント基板の平面図FIG. 1 is a plan view of a semiconductor device evaluation printed circuit board according to an embodiment of the present invention.
【図２】本発明の一実施形態において外部バイアス印加
のためのコネクターを接続した場合の概略図FIG. 2 is a schematic diagram when a connector for applying an external bias is connected in an embodiment of the present invention.
【図３】本発明の一実施形態の半導体装置の評価用プリ
ント基板の平面図FIG. 3 is a plan view of a printed circuit board for evaluation of a semiconductor device according to an embodiment of the present invention.
【図４】従来の半導体装置の評価用プリント基板の平面
図FIG. 4 is a plan view of a conventional printed circuit board for evaluation of a semiconductor device.
１ プリント基板 ２ プリント基板上のランド ３ プリント基板上のランド間を結ぶ金属配線 ４ 外部バイアス印加するためのコネクター ５ 表面実装型半導体装置 1 Printed Circuit Board 2 Land on Printed Circuit Board 3 Metal Wiring Connecting Lands on Printed Circuit Board 4 Connector for Applying External Bias 5 Surface Mount Semiconductor Device
Claims (1)
を各種リードピンピッチ毎に、同一プリント基板上に実
装できるようにランドが配置され、また、各種外形寸法
の異なる表面実装型半導体装置のアウターリードはんだ
接続部の電気的特性がとれるようにランド間に金属配線
を備えた半導体装置の評価用プリント基板。1. Outer leads of a surface-mounting type semiconductor device having different external dimensions and having lands arranged so as to be mounted on the same printed circuit board at various lead pin pitches, and having different external dimensions. A printed circuit board for evaluation of a semiconductor device, which is provided with a metal wiring between lands so that the electrical characteristics of a solder connection portion can be obtained.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12299196A JPH09307200A (en) | 1996-05-17 | 1996-05-17 | Printed circuit board for evaluating semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12299196A JPH09307200A (en) | 1996-05-17 | 1996-05-17 | Printed circuit board for evaluating semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH09307200A true JPH09307200A (en) | 1997-11-28 |
Family
ID=14849588
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12299196A Pending JPH09307200A (en) | 1996-05-17 | 1996-05-17 | Printed circuit board for evaluating semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH09307200A (en) |
-
1996
- 1996-05-17 JP JP12299196A patent/JPH09307200A/en active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP3294740B2 (en) | Semiconductor device | |
| JP2568748B2 (en) | Semiconductor device | |
| US4674811A (en) | Apparatus for connecting pin grid array devices to printed wiring boards | |
| JPH08125379A (en) | Shield device | |
| JP2907127B2 (en) | Multi-chip module | |
| JP2000331734A (en) | Manufacture of surface mounting type connector and circuit device | |
| US20020184759A1 (en) | Process for producing a contact-making device | |
| KR20010112322A (en) | A method and an arrangement for the electrical contact of comp0nents | |
| JP3309099B2 (en) | Connection method between circuit board and surface mount LSI | |
| US5444299A (en) | Electronic package with lead wire connections | |
| KR960035997A (en) | Semiconductor package and manufacturing method | |
| JPH09307200A (en) | Printed circuit board for evaluating semiconductor device | |
| JP3311675B2 (en) | Film carrier tape | |
| JPH08191128A (en) | Electronic device | |
| JPH0125491Y2 (en) | ||
| JPH07297236A (en) | Film and structure for mounting semiconductor element thereon | |
| JPS59123291A (en) | Circuit board for electronic device | |
| JP2000174161A (en) | Flexible substrate and method for mounting semiconductor device using the same | |
| JPS6318688A (en) | Ceramic package | |
| JPH0380599A (en) | Electronic circuit module | |
| JPS60201692A (en) | Wiring circuit device | |
| JPH01297882A (en) | Printed board | |
| JPH11260959A (en) | Semiconductor package | |
| JPS62244156A (en) | Surface mounting package | |
| JP2002158427A (en) | Printed wiring board, component mounting board and electronic apparatus |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A02 | Decision of refusal |
Effective date: 20040601 Free format text: JAPANESE INTERMEDIATE CODE: A02 |