JPH09270464A - Method of producing minute aerial wiring - Google Patents
Method of producing minute aerial wiringInfo
- Publication number
- JPH09270464A JPH09270464A JP10382396A JP10382396A JPH09270464A JP H09270464 A JPH09270464 A JP H09270464A JP 10382396 A JP10382396 A JP 10382396A JP 10382396 A JP10382396 A JP 10382396A JP H09270464 A JPH09270464 A JP H09270464A
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- Prior art keywords
- insulating film
- resist
- wiring
- forming
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- Drying Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、空中配線を形成す
るための微細加工技術に関する。The present invention relates to a fine processing technique for forming an aerial wiring.
【０００２】[0002]
【従来の技術】近時、半導体装置の高集積化と高密度化
に伴い、空中配線の微細化が必要とされている。しかし
ながら、従来、広く用いられているフォトリソグラフィ
技術では、形成できる形状の最小寸法が、ほぼ１０-4ｃ
ｍに限られている。2. Description of the Related Art In recent years, as semiconductor devices have become more highly integrated and higher in density, it has become necessary to miniaturize aerial wiring. However, conventionally, with the photolithography technology widely used, the minimum dimension of a shape that can be formed is approximately 10 −4 c.
m.
【０００３】このため、微細な空中配線を形成する場
合、電子ビームリソグラフィなどが利用される。この技
術を用いた空中配線の作製方法として、例えば特開平４
−２１３８６１号公報には、少なくとも３層の多層レジ
ストを形成し、異なる露光密度で露光することにより、
下層レジストが残った部分と残らない部分とからなるレ
ジストパターンを形成し、その後、リフトオフ加工法に
よりレジストを除去することによって下層レジスト除去
後の空間を形成し、空中配線を形成するようにした方法
が提案されている。[0003] For this reason, when forming fine aerial wiring, electron beam lithography or the like is used. As a method of manufacturing an aerial wiring using this technology, for example,
Japanese Patent No. -213861 discloses that a multilayer resist of at least three layers is formed and exposed at different exposure densities.
A method in which a resist pattern composed of a portion where a lower layer resist remains and a portion where no lower layer resist remains is formed, and then the resist is removed by a lift-off processing method to form a space after removing the lower layer resist, thereby forming an aerial wiring. Has been proposed.
【０００４】空中配線作製のこの従来技術について、図
２を参照して以下に説明する。図２には、半導体装置の
部分断面図が製造工程順に模式的に示されている。This conventional technique for producing aerial wiring will be described below with reference to FIG. FIG. 2 schematically shows a partial cross-sectional view of the semiconductor device in the order of the manufacturing process.
【０００５】まず、半導体基板２０に低感度電子ビーム
露光用レジスト２２、高感度電子ビーム露光用レジスト
２３、及び中感度電子ビーム露光用レジスト２４を順次
塗布する。次に、空中配線のアーチとなる部分を、低密
度電子ビーム２６で露光し、空中配線の柱となる部分を
高密度電子ビーム２５で露光する（図２（Ａ）参照）。First, a resist 22 for low-sensitivity electron beam exposure, a resist 23 for high-sensitivity electron beam exposure, and a resist 24 for medium-sensitivity electron beam exposure are sequentially applied to a semiconductor substrate 20. Next, the part which becomes the arch of the aerial wiring is exposed with the low-density electron beam 26, and the part which becomes the pillar of the aerial wiring is exposed with the high-density electron beam 25 (see FIG. 2A).
【０００６】空中配線のアーチとなる部分を低感度レジ
スト２２まで現像し、かつ同時に、空中配線の柱となる
部分を半導体基板２０まで現像する（図２（Ｂ）参
照）。The arch portion of the aerial wiring is developed to the low-sensitivity resist 22, and at the same time, the column portion of the aerial wiring is developed to the semiconductor substrate 20 (see FIG. 2B).
【０００７】配線金属２８を蒸着し（図２（Ｃ）参
照）、リフトオフ法を用いて低感度レジストを除去し空
中配線２９を形成する（図２（Ｄ）参照）。A wiring metal 28 is deposited (see FIG. 2C), and the low-sensitivity resist is removed by a lift-off method to form an aerial wiring 29 (see FIG. 2D).
【０００８】この方法では、多層レジスト層が、アンダ
カット（ｕｎｄｅｒｃｕｔ）形状となるのでリフトオフ
が容易である。In this method, since the multilayer resist layer has an undercut shape, lift-off is easy.
【０００９】[0009]
【発明が解決しようとする課題】しかしながら、上記し
た空中配線を形成する従来技術では、リフトオフを容易
化するために、多層レジストが必要となり、総レジスト
膜厚が厚くなる。そして、この総レジスト膜厚が厚くな
ると、電子ビームの散乱増大によって、微細加工が難し
くなるという問題が生じることになる。However, in the prior art for forming the above-mentioned aerial wiring, a multilayer resist is required in order to facilitate lift-off, and the total resist film thickness is increased. When the total resist film thickness increases, a problem arises in that fine processing becomes difficult due to an increase in scattering of electron beams.
【００１０】従って、本発明は、上記事情に鑑みて為さ
れたものであって、その目的は、微細空中配線の形成に
好適な加工方法を提供することを目的とする。Therefore, the present invention has been made in view of the above circumstances, and an object thereof is to provide a processing method suitable for forming fine aerial wiring.
【００１１】[0011]
【課題を解決するための手段】前記目的を達成するた
め、本発明は、（ａ）基板上に絶縁膜を被着する工程
と、（ｂ）前記絶縁膜に前記基板の表面までオーバハン
グ又はアンダカット状の開口部を形成する工程と、
（ｃ）前記基板上にレジストマスクを前記絶縁膜の開口
部内において所定の箇所に複数開口する工程と、（ｄ）
配線金属を形成する工程と、（ｅ）前記レジストマスク
を用いて、リフトオフ法により前記配線金属から空中配
線を形成する工程と、を含むことを特徴とする空中配線
を作製する方法を提供する。In order to achieve the above object, the present invention comprises: (a) a step of depositing an insulating film on a substrate; and (b) an overhang or underhang of the insulating film to the surface of the substrate. Forming a cut-shaped opening;
(C) a step of forming a plurality of resist masks on the substrate at predetermined positions in the openings of the insulating film;
A method for manufacturing an aerial wiring, comprising: forming a wiring metal; and (e) forming an aerial wiring from the wiring metal by a lift-off method using the resist mask.
【００１２】[0012]
【発明の実施の形態】本発明の好ましい実施の形態につ
いて図面を参照して以下に説明する。図１は、本発明の
実施の形態を説明するための図であり、製造工程順に部
分断面図を模式的に示したものである。図１を参照し
て、本発明に係る微細空中配線作製方法は、基板４０上
に絶縁膜（４２、４３）を被着し（図１（Ａ）参照）、
この絶縁膜上にレジスト４４を塗布し、絶縁膜を基板４
０の表面にまで、エッチング開口の断面形状が、オーバ
ハングもしくはアンダカット状にエッチングする（図１
（Ｂ）参照）。なお、図１には、絶縁膜のエッチング開
口はオーバハング形状のものが示されている。Preferred embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a view for explaining an embodiment of the present invention, and schematically shows a partial cross-sectional view in the order of manufacturing steps. Referring to FIG. 1, in the method for manufacturing a fine air wiring according to the present invention, an insulating film (42, 43) is deposited on a substrate 40 (see FIG. 1A).
A resist 44 is applied on this insulating film, and the insulating film is
0, the cross-sectional shape of the etching opening is etched in an overhang or undercut shape (FIG. 1).
(B)). FIG. 1 shows an etching opening of the insulating film having an overhang shape.
【００１３】次に、基板上に電子露光用レジスト５１を
塗布し（図１（Ｃ）参照）て、開口内において、基板４
０上のレジスト５１に所定の箇所（図では２箇所）を開
口した後に、配線金属４８を蒸着し（図１（Ｄ）参
照）、このレジストマスク５１を用いて、リフトオフ法
により、空中配線を形成する（図１（Ｅ）参照）、もの
である。Next, an electron exposure resist 51 is applied on the substrate (see FIG. 1C), and the substrate 4 is placed in the opening.
After opening predetermined locations (two locations in the figure) in the resist 51 on the substrate 0, a wiring metal 48 is vapor-deposited (see FIG. 1D), and an aerial wiring is formed by a lift-off method using the resist mask 51. (See FIG. 1E).
【００１４】上記した本発明の実施形態をより詳細に説
明すべく実施例を説明する。Examples will be described in order to explain the above-described embodiment of the present invention in more detail.
【００１５】図１（Ａ）を参照して、まず半導体基板４
０上に、２層絶縁膜４２、４３を順次形成する。下層絶
縁膜４２としては、ＣＶＤ（化学気相成長；chemical v
apordeposition）酸化膜からなり、膜厚は好ましくは８
００〜１６００ｎｍ、基板温度は好ましくは３００〜３
５０℃で形成され、上層絶縁膜４３としては、ＰＥＣＶ
Ｄ（プラズマＣＶＤ；plasma enhanced CVD）窒化膜 、
膜厚は好ましくは８０〜１６０ｎｍ、基板温度は好まし
くは２６０〜３５０℃）で被着される。Referring to FIG. 1A, first, a semiconductor substrate 4
On layer 0, two-layer insulating films 42 and 43 are sequentially formed. As the lower insulating film 42, CVD (chemical vapor deposition; chemical v
apordeposition) It is composed of an oxide film, and the film thickness is preferably 8
00 to 1600 nm, the substrate temperature is preferably 300 to 3
The upper insulating film 43 is formed at 50 ° C.
D (plasma enhanced CVD) nitride film,
The film thickness is preferably 80 to 160 nm, and the substrate temperature is preferably 260 to 350 ° C.).
【００１６】次に、フォトリソグラフィ法を用いて、フ
ォトレジスト（photoresist）４４のマスクを配線形状
に形成する。次に、このマスクを用いて２層絶縁膜を例
えばバッファードフッ酸（buffered hydrofluoric aci
d）による化学的エッチングにより、半導体基板４０ま
で配線形状にエッチングする（図１（Ｂ）参照）。Next, a mask of a photoresist (photoresist) 44 is formed in a wiring shape by using a photolithography method. Next, using this mask, the two-layer insulating film is formed, for example, into buffered hydrofluoric acid.
By the chemical etching according to d), the semiconductor substrate 40 is etched into a wiring shape (see FIG. 1B).
【００１７】バッファードフッ酸の酸化膜（下層絶縁膜
４２）のエッチング速度（etch rate）は、窒化膜（上
層絶縁膜４３）のエッチング速度よりも、大きいので、
この絶縁膜４２、４３のエッチング開口部は、図１
（Ｂ）に示すように、オーバハング形状となる。Since the etching rate of the buffered hydrofluoric acid oxide film (lower insulating film 42) is higher than that of the nitride film (upper insulating film 43),
The etching openings of the insulating films 42 and 43 correspond to FIG.
As shown in (B), the overhang shape is obtained.
【００１８】次に、電子ビームレジスト５１を基板４０
上に塗布する（図１（Ｃ）参照）。ここで、電子ビーム
レジスト５１は、２層の絶縁膜４２、４３に沿ってオー
バハング形状となる。Next, an electron beam resist 51 is applied to the substrate 40.
It is applied on top (see FIG. 1 (C)). Here, the electron beam resist 51 has an overhang shape along the two insulating films 42 and 43.
【００１９】次に、電子ビームリソグラフィを用いて、
半導体基板４０上に接触する部分の電子ビームレジスト
５１を開口し、配線金属４８を蒸着する（図１（Ｄ）参
照）。Next, using electron beam lithography,
An opening is formed in a portion of the electron beam resist 51 that is in contact with the semiconductor substrate 40, and a wiring metal 48 is deposited (see FIG. 1D).
【００２０】次に、リフトオフ法を用いて、電子ビーム
レジストを除去し、空中配線５０を形成する（図１
（Ｅ）参照）。Next, the lift-off method is used to remove the electron beam resist, thereby forming an aerial wiring 50 (FIG. 1).
(E)).
【００２１】本実施例によれば、電子露光用のレジスト
５１は、オーバハング形状の開口に沿うので、このレジ
スト５１の膜厚を薄くしてもリフトオフ法は容易であ
る。レジスト膜厚が薄くなると、電子ビームの散乱減少
によって微細加工が容易になる。According to the present embodiment, since the resist 51 for electron exposure is along the overhang-shaped opening, the lift-off method is easy even if the thickness of the resist 51 is reduced. When the resist film thickness is reduced, fine processing is facilitated by the reduction in scattering of the electron beam.
【００２２】上記実施例では、フォトリソグラフィを用
いて、配線形状のエッチングをしたが（図１（Ｂ）参
照）、電子ビームソグラフィ等を用いてもよい。In the above embodiment, the wiring shape was etched using photolithography (see FIG. 1B), but electron beam lithography or the like may be used.
【００２３】上記実施例で用いた酸化膜と窒化膜の代わ
りに、ＴｉＮｘ、ＴｉＯｘ、ＡｌＯｘなどの絶縁膜を用
いても同様の作用効果を奏することができる。Similar effects can be obtained by using an insulating film such as TiNx, TiOx, or AlOx instead of the oxide film and the nitride film used in the above embodiment.
【００２４】また、上記したＣＶＤとＰＥＣＶＤの代わ
りに、スパッタリング法や蒸着法等で絶縁膜を成長して
もよい。Further, instead of the above-described CVD and PECVD, an insulating film may be grown by a sputtering method, a vapor deposition method, or the like.
【００２５】さらに、上記実施例で示した多層絶縁膜の
代わりに、１層の絶縁膜を用いた場合でも同様な作用効
果を得ることも可能である。すなわち、例えば、１層の
ＰＥＣＶＤ窒化膜を用いた場合、成長時の圧力を減ら
す、またはＲＦ出力（プラズマＣＶＤの高周波電力）を
上げる、または基板温度を上げる、または雰囲気の窒素
密度を増やすことにより、成長膜のエッチング速度を、
表面から基板の方向へ向かって速くすることができる。Further, even when a single-layer insulating film is used instead of the multilayer insulating film shown in the above-described embodiment, the same function and effect can be obtained. That is, for example, when a single PECVD nitride film is used, the pressure during growth is reduced, the RF output (high-frequency power of plasma CVD) is increased, the substrate temperature is increased, or the nitrogen density of the atmosphere is increased. , The growth rate of the growth film,
The speed can be increased from the surface toward the substrate.
【００２６】このため、オーバハングもしくはアンダカ
ット開口を同様にして得ることができる。For this reason, an overhang or undercut opening can be obtained in the same manner.
【００２７】また、絶縁膜のエッチング開口部の形成
は、バッファードフッ酸による化学的エッチングの代わ
りに、ドライエッチングなども使用することもできる。Further, in order to form the etching opening of the insulating film, dry etching or the like can be used instead of chemical etching using buffered hydrofluoric acid.
【００２８】さらに、電子ビームの代わりに、イオンビ
ームまたは光を用いて露光することも可能である。Further, it is possible to perform exposure using an ion beam or light instead of an electron beam.
【００２９】このように上記実施例は本発明を限定する
ものでなく、本発明は、本発明の原理に準ずる、各種形
態及び変形を含むことは勿論である。As described above, the above-described embodiment does not limit the present invention. The present invention naturally includes various forms and modifications according to the principle of the present invention.
【００３０】[0030]
【発明の効果】以上説明したように、本発明によれば、
微細空中配線の作製を容易化し、素子密度の高い集積回
路の作製を容易化し、その結果、歩留まりを向上すると
いう効果を奏する。特に、本発明によれば、電子ビーム
レジストの膜厚が厚くなることによる電子ビームの散乱
増大によって、微細加工が難しくなるという問題点を完
全に解消し、微細空中配線加工に好適な加工方法を提供
するものである。As described above, according to the present invention,
This facilitates the fabrication of fine aerial wiring and facilitates the fabrication of an integrated circuit having a high element density, thereby improving the yield. In particular, according to the present invention, the problem that fine processing becomes difficult due to an increase in electron beam scattering due to an increase in the thickness of the electron beam resist is completely solved, and a processing method suitable for fine aerial wiring processing is provided. To provide.
【図１】本発明の実施例を説明するための図であり、製
造工程順に模式的に示した部分断面図である。FIG. 1 is a view for explaining an embodiment of the present invention, and is a partial cross-sectional view schematically showing the order of manufacturing steps.
【図２】従来の技術を説明するための図であり、製造工
程順に模式的に示した部分断面図である。FIG. 2 is a view for explaining a conventional technique, and is a partial cross-sectional view schematically showing the order of manufacturing steps.
２０、４０ 半導体基板 ２２ 低感度電子ビーム露光用 ２３ 高感度電子ビーム露光用 ２４ 中感度電子ビーム露光用 ２５ 電子ビーム（高密度） ２６ 電子ビーム（低密度） ２８、４８ 配線金属 ２９、５０ 空中配線 ４２ 下層絶縁膜 ４３ 上層絶縁膜 ４４ フォトレジスト ５１ 電子ビーム露光用レジスト 20, 40 Semiconductor substrate 22 For low-sensitivity electron beam exposure 23 For high-sensitivity electron beam exposure 24 For medium-sensitivity electron beam exposure 25 Electron beam (high density) 26 Electron beam (low density) 28, 48 Wiring metal 29, 50 Aerial wiring 42 lower insulating film 43 upper insulating film 44 photoresist 51 resist for electron beam exposure
Claims (7)
はアンダカット状の開口部を形成する工程と、 （ｃ）前記基板上にレジストマスクを前記絶縁膜の開口
部内において所定の箇所に複数開口する工程と、 （ｄ）配線金属を形成する工程と、 （ｅ）前記レジストマスクを用いて、リフトオフ法によ
り前記配線金属から空中配線を形成する工程と、 を含むことを特徴とする空中配線を作製する方法。(A) forming an insulating film on a substrate; (b) forming an overhang or undercut opening in the insulating film up to the surface of the substrate; A step of forming a plurality of resist masks at predetermined positions in the opening of the insulating film on the substrate; (d) a step of forming a wiring metal; and (e) a step of forming the wiring metal by a lift-off method using the resist mask. Forming an aerial wiring from the following. A method for manufacturing an aerial wiring, comprising:
とを特徴とする請求項１記載の空中配線を作製する方
法。2. The method according to claim 1, wherein said insulating film comprises a plurality of insulating films.
くとも二種の絶縁膜からなることを特徴とする請求項１
記載の空中配線を作製する方法。3. The insulating film according to claim 1, wherein said insulating film comprises at least two kinds of insulating films having different etch rates.
A method for producing the aerial wiring as described.
面から基板方向にエッチング比を可変することにより、
オーバハング又はアンダカット状に開口部を形成するこ
とを特徴とする請求項１記載の空中配線を作製する方
法。4. The method according to claim 1, wherein the insulating film comprises a single layer, and the etching ratio is varied from the surface of the insulating film toward the substrate.
The method for producing an aerial wiring according to claim 1, wherein the opening is formed in an overhang or undercut shape.
層の絶縁膜からなることを特徴とする請求項３記載の空
中配線を作製する方法。5. The semiconductor device according to claim 1, wherein said insulating film comprises a nitride film and an oxide film.
4. The method for manufacturing an air wiring according to claim 3, comprising a layer of an insulating film.
の絶縁膜に、前記基板に達するエッチング開口部を形成
し、 （ｂ）続いて塗布されるレジストについて、前記絶縁膜
の開口部内の前記基板上の該レジストに、空中配線の柱
となる箇所を前記基板まで開口し、 （ｃ）前記レジストを覆うように配線金属を形成し、 （ｄ）リフトオフ法により、前記絶縁膜の開口部内の前
記配線金属の下層レジストを除去し、前記基板上に空中
配線を形成する、 ことを特徴とする空中配線を作製する方法。6. An etching opening reaching the substrate is formed in one or more insulating films formed on the substrate, and (b) an opening of the insulating film is formed with respect to a resist applied subsequently. (C) forming a wiring metal so as to cover the resist; and (d) forming a wiring metal so as to cover the resist. A method for manufacturing an aerial wiring, comprising: removing an underlayer resist of the wiring metal in an opening to form an aerial wiring on the substrate.
ハング又はアンダカット形状とされたことを特徴とする
請求項６記載の空中配線を作製する方法。7. The method of manufacturing an aerial wiring according to claim 6, wherein a sectional shape of said etching opening is an overhang or an undercut shape.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10382396A JP2765561B2 (en) | 1996-03-29 | 1996-03-29 | Fabrication method of fine aerial wiring |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10382396A JP2765561B2 (en) | 1996-03-29 | 1996-03-29 | Fabrication method of fine aerial wiring |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH09270464A true JPH09270464A (en) | 1997-10-14 |
| JP2765561B2 JP2765561B2 (en) | 1998-06-18 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10382396A Expired - Fee Related JP2765561B2 (en) | 1996-03-29 | 1996-03-29 | Fabrication method of fine aerial wiring |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2765561B2 (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002139842A (en) * | 2000-11-01 | 2002-05-17 | Fujitsu Ltd | Pattern forming method and semiconductor device |
| CN112103241A (en) * | 2020-11-17 | 2020-12-18 | 腾讯科技（深圳）有限公司 | Air bridge manufacturing method, air bridge and electronic equipment |
| CN112271133A (en) * | 2020-09-25 | 2021-01-26 | 华东光电集成器件研究所 | Metal stripping method based on three layers of glue |
| WO2022017073A1 (en) * | 2020-07-23 | 2022-01-27 | 腾讯科技（深圳）有限公司 | Photoresist structure, patterned deposition layer, semiconductor chip and manufacturing method therefor |
| KR20220071150A (en) * | 2020-11-17 | 2022-05-31 | 텐센트 테크놀로지(센젠) 컴퍼니 리미티드 | Manufacturing method of air bridge, air bridge and electronic device |
| KR20220091531A (en) * | 2020-11-20 | 2022-06-30 | 텐센트 테크놀로지(센젠) 컴퍼니 리미티드 | Air bridge manufacturing method, air bridge structure and superconducting quantum chip |
| KR20220091532A (en) * | 2020-10-15 | 2022-06-30 | 텐센트 테크놀로지(센젠) 컴퍼니 리미티드 | Air bridge structure and manufacturing method thereof, and superconducting quantum chip and manufacturing method thereof |
-
1996
- 1996-03-29 JP JP10382396A patent/JP2765561B2/en not_active Expired - Fee Related
Cited By (11)
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|---|---|---|---|---|
| JP2002139842A (en) * | 2000-11-01 | 2002-05-17 | Fujitsu Ltd | Pattern forming method and semiconductor device |
| WO2022017073A1 (en) * | 2020-07-23 | 2022-01-27 | 腾讯科技（深圳）有限公司 | Photoresist structure, patterned deposition layer, semiconductor chip and manufacturing method therefor |
| CN112271133A (en) * | 2020-09-25 | 2021-01-26 | 华东光电集成器件研究所 | Metal stripping method based on three layers of glue |
| KR20220091532A (en) * | 2020-10-15 | 2022-06-30 | 텐센트 테크놀로지(센젠) 컴퍼니 리미티드 | Air bridge structure and manufacturing method thereof, and superconducting quantum chip and manufacturing method thereof |
| CN112103241A (en) * | 2020-11-17 | 2020-12-18 | 腾讯科技（深圳）有限公司 | Air bridge manufacturing method, air bridge and electronic equipment |
| WO2022105232A1 (en) * | 2020-11-17 | 2022-05-27 | 腾讯科技（深圳）有限公司 | Method for manufacturing air bridge, and air bridge and electronic device |
| KR20220071150A (en) * | 2020-11-17 | 2022-05-31 | 텐센트 테크놀로지(센젠) 컴퍼니 리미티드 | Manufacturing method of air bridge, air bridge and electronic device |
| EP4030468A4 (en) * | 2020-11-17 | 2022-07-20 | Tencent Technology (Shenzhen) Company Limited | Method for manufacturing air bridge, and air bridge and electronic device |
| JP2023507685A (en) * | 2020-11-17 | 2023-02-27 | テンセント・テクノロジー・（シェンジェン）・カンパニー・リミテッド | Air bridge manufacturing method, air bridge and electronic device |
| US11996319B2 (en) | 2020-11-17 | 2024-05-28 | Tencent Technology (Shenzhen) Company Limited | Manufacturing method of air bridge, air bridge and electronic device |
| KR20220091531A (en) * | 2020-11-20 | 2022-06-30 | 텐센트 테크놀로지(센젠) 컴퍼니 리미티드 | Air bridge manufacturing method, air bridge structure and superconducting quantum chip |
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| Publication number | Publication date |
|---|---|
| JP2765561B2 (en) | 1998-06-18 |
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