JPH09246554A - Manufacture of thin-film transistor and liquid-crystal display device - Google Patents
Manufacture of thin-film transistor and liquid-crystal display deviceInfo
- Publication number
- JPH09246554A JPH09246554A JP4526496A JP4526496A JPH09246554A JP H09246554 A JPH09246554 A JP H09246554A JP 4526496 A JP4526496 A JP 4526496A JP 4526496 A JP4526496 A JP 4526496A JP H09246554 A JPH09246554 A JP H09246554A
- Authority
- JP
- Japan
- Prior art keywords
- thin film
- resist
- light
- metal thin
- silicon thin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000010409 thin film Substances 0.000 title claims abstract description 107
- 239000004973 liquid crystal related substance Substances 0.000 title claims description 12
- 238000004519 manufacturing process Methods 0.000 title claims description 6
- 229910052751 metal Inorganic materials 0.000 claims abstract description 28
- 239000002184 metal Substances 0.000 claims abstract description 28
- 239000000758 substrate Substances 0.000 claims abstract description 27
- 239000004065 semiconductor Substances 0.000 claims abstract description 26
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 17
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 12
- 238000000151 deposition Methods 0.000 claims description 4
- 238000000059 patterning Methods 0.000 claims description 2
- 239000011521 glass Substances 0.000 abstract description 20
- 238000000034 method Methods 0.000 abstract description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract 2
- 229910052710 silicon Inorganic materials 0.000 abstract 2
- 239000010703 silicon Substances 0.000 abstract 2
- 239000010410 layer Substances 0.000 description 13
- 239000010408 film Substances 0.000 description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 229910052814 silicon oxide Inorganic materials 0.000 description 6
- 239000011229 interlayer Substances 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 229910001936 tantalum oxide Inorganic materials 0.000 description 3
- 239000012298 atmosphere Substances 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 229910000838 Al alloy Inorganic materials 0.000 description 1
- 101100269850 Caenorhabditis elegans mask-1 gene Proteins 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78633—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a light shield
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Liquid Crystal (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Thin Film Transistor (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体装置などに
応用される薄膜トランジスタの製造方法と、この薄膜ト
ランジスタを用いた液晶表示装置に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a thin film transistor applied to a semiconductor device and the like, and a liquid crystal display device using the thin film transistor.
【０００２】[0002]
【従来の技術】従来の液晶表示装置には、逆スタガ型非
晶質シリコン薄膜トランジスタがよく用いられている。
この逆スタガ構造は、ガラス基板の上に先ずゲート配線
を形成するため、ガラス基板の側から光が入射しても半
導体薄膜に光が直接に入射することがない。2. Description of the Related Art Inverted stagger type amorphous silicon thin film transistors are often used in conventional liquid crystal display devices.
In this inverted staggered structure, since the gate wiring is first formed on the glass substrate, the light does not directly enter the semiconductor thin film even when the light enters from the glass substrate side.
【０００３】また、ポリシリコン薄膜トランジスタの場
合コプレナ型が主流であるが、コプレナ構造のためガラ
ス基板と半導体層の間に遮光用の金属薄膜を形成する。
また、金属薄膜を形成した後に半導体薄膜を形成する際
にはそれぞれのマスクでパターンを形成する。In the case of a polysilicon thin film transistor, a coplanar type is mainly used, but a metal thin film for light shielding is formed between a glass substrate and a semiconductor layer because of the coplanar structure.
When forming a semiconductor thin film after forming a metal thin film, a pattern is formed with each mask.
【０００４】[0004]
【発明が解決しようとする課題】多結晶シリコンを用い
た薄膜トランジスタは、自己整合型のドーピング領域を
形成しやすいゲート電極が半導体薄膜の上側に位置する
コプレナ構造がよく用いられる。A thin film transistor using polycrystalline silicon often has a coplanar structure in which a gate electrode that easily forms a self-aligned doping region is located above a semiconductor thin film.
【０００５】この場合、ガラス基板の上に半導体薄膜は
直接に形成されるため、光に関して直接に影響を受ける
ことになる。そのためコプレナ構造の多結晶シリコン薄
膜トランジスタを液晶表示装置に用いる場合（特に強い
光を入射する投射型液晶表示装置の場合）には、光電流
による画質の劣化が生じるという問題が生じる。In this case, since the semiconductor thin film is directly formed on the glass substrate, it is directly affected by light. Therefore, when a polycrystalline silicon thin film transistor having a coplanar structure is used in a liquid crystal display device (especially in the case of a projection type liquid crystal display device in which strong light is incident), there arises a problem that image quality is deteriorated by photocurrent.
【０００６】また、前記課題を解決するために金属薄膜
をガラス基板の上に所定の形状に形成し、その後に半導
体薄膜を形成することによりガラス基板の側からの遮光
を実現できるが、半導体薄膜より遮光用の金属薄膜が大
きくなる場合、上部のゲート配線およびソース・ドレイ
ン配線との容量成分が生じて液晶表示装置の画質に問題
となる場合がある。In order to solve the above problems, a metal thin film is formed on a glass substrate in a predetermined shape, and then a semiconductor thin film is formed, so that light can be shielded from the glass substrate side. When the light-shielding metal thin film becomes larger, a capacitance component with the upper gate wiring and source / drain wiring may occur, which may cause a problem in the image quality of the liquid crystal display device.
【０００７】[0007]
【課題を解決するための手段】コプレナ型の多結晶シリ
コン薄膜トランジスタを液晶表示装置に用いる場合、ガ
ラス基板の上に金属薄膜を形成した後、絶縁膜を介して
半導体薄膜を形成する。また、ガラス基板の上に形成し
た金属薄膜をマスクにしてガラス基板の裏面から半導体
層の上のレジストのパターニングを行う。When a coplanar type polycrystalline silicon thin film transistor is used in a liquid crystal display device, a metal thin film is formed on a glass substrate and then a semiconductor thin film is formed via an insulating film. Further, the resist on the semiconductor layer is patterned from the back surface of the glass substrate using the metal thin film formed on the glass substrate as a mask.
【０００８】ガラス基板の上に金属薄膜を形成し遮光層
とすることによりガラス基板の側からの半導体薄膜への
光の入射を阻止することが可能となり、強い光を入射し
ても画質の劣化を生じることがない。また、金属薄膜を
マスクにしてガラス基板の裏面から半導体層の上のレジ
ストをパターニングすることにより自己整合的に半導体
薄膜のパターニングを行うことができ、ゲート配線およ
びソース・ドレイン配線と遮光薄膜との容量成分の問題
をなくすことができる。By forming a metal thin film on the glass substrate to form a light-shielding layer, it becomes possible to prevent light from entering the semiconductor thin film from the glass substrate side, and image quality deteriorates even when strong light enters. Does not occur. In addition, the semiconductor thin film can be patterned in a self-aligning manner by patterning the resist on the semiconductor layer from the back surface of the glass substrate using the metal thin film as a mask. The problem of capacitive component can be eliminated.
【０００９】[0009]
【発明の実施の形態】以下、本発明の薄膜トランジスタ
の製造方法を具体的な実施例に基づいて説明する。BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, a method for manufacturing a thin film transistor according to the present invention will be described based on specific examples.
【００１０】〔実施例１〕図１の（ａ）に示すように、
ガラス基板１０１に金属薄膜１０２を堆積し所定の形状
にパターニングを行う。その際、金属薄膜はＣｒ、Ｔ
ｉ、Ｔａ、Ａｌ、Ａｌ合金、ＮｉまたはＷを 30 〜 200
ｎｍの膜厚で堆積する。Example 1 As shown in FIG. 1 (a),
A metal thin film 102 is deposited on the glass substrate 101 and patterned into a predetermined shape. At that time, the metal thin film is made of Cr, T
i, Ta, Al, Al alloy, Ni or W 30 to 200
deposited to a thickness of nm.
【００１１】次に図１の（ｂ）に示すように、金属薄膜
１０２の上に酸化シリコン薄膜１０３を 100〜 1000 ｎ
ｍ堆積する。その際、酸化シリコン薄膜の代わりに酸化
タンタル薄膜、窒化シリコン薄膜、酸化シリコン薄膜と
窒化シリコン薄膜２層、酸化シリコン薄膜と酸化タンタ
ル薄膜２層または酸化タンタル薄膜と窒化シリコン薄膜
２層などの構成でもよい。さらに図１の（ｂ）に示すよ
うに、プラズマＣＶＤ法により非晶質シリコン薄膜１０
４を堆積する。その際、堆積方法としてはＬＰ−ＣＶＤ
法、スパッタ法を用いてもよい。Next, as shown in FIG. 1B, a silicon oxide thin film 103 is formed on the metal thin film 102 in an amount of 100 to 1000 n.
m. At that time, instead of the silicon oxide thin film, a structure such as a tantalum oxide thin film, a silicon nitride thin film, a silicon oxide thin film and a silicon nitride thin film 2 layers, a silicon oxide thin film and a tantalum oxide thin film 2 layers, or a tantalum oxide thin film and a silicon nitride thin film 2 layers may be used. Good. Further, as shown in FIG. 1B, the amorphous silicon thin film 10 is formed by the plasma CVD method.
4 is deposited. At that time, the deposition method is LP-CVD.
Method or sputtering method may be used.
【００１２】次に図１の（ｃ）に示すように、エキシマ
レーザー１０６を用いて非晶質シリコン薄膜を溶融・結
晶化を行い、多結晶シリコン薄膜１０５を形成する。エ
キシマレーザーとしてはＸｅＣｌ、ＫｒＦもしくはＡｒ
Ｆなどを用いる。また、多結晶シリコン薄膜の形成方法
として固層成長を用いてもよい。Next, as shown in FIG. 1C, the amorphous silicon thin film is melted and crystallized by using an excimer laser 106 to form a polycrystalline silicon thin film 105. XeCl, KrF or Ar as the excimer laser
F or the like is used. Further, solid layer growth may be used as a method for forming a polycrystalline silicon thin film.
【００１３】次に図１の（ｄ）に示すように、多結晶シ
リコン薄膜の上にレジスト１０７を塗布し、ガラス基板
１０１の裏面から紫外光１０８によりレジスト１０７を
露光する。図１の（ｅ）はレジストを露光後に現像した
ものである。Next, as shown in FIG. 1D, a resist 107 is applied on the polycrystalline silicon thin film, and the resist 107 is exposed from the back surface of the glass substrate 101 by ultraviolet light 108. FIG. 1E shows the resist developed after exposure.
【００１４】次に図１の（ｆ）に示すように、レジスト
１０７をマスクにして多結晶シリコン１０５をエッチン
グする。次に図１の（ｇ）に示すように、レジスト１０
７を除去すると自己整合で半導体薄膜の形成ができる。Next, as shown in FIG. 1F, the polycrystalline silicon 105 is etched using the resist 107 as a mask. Next, as shown in FIG.
When 7 is removed, a semiconductor thin film can be formed by self-alignment.
【００１５】ここで、非晶質シリコン薄膜をエキシマレ
ーザー１０６で溶融・結晶化する際に、溶融時の突沸を
避けるため、非晶質シリコン薄膜中の水素を一部脱離さ
せるために 350〜 500℃の温度で基板１０１を加熱処理
する工程を行う場合もある。処理時間は 10 〜 180分程
度で、処理雰囲気は、真空中、窒素雰囲気中、酸素雰囲
気中または大気中などである。Here, when the amorphous silicon thin film is melted and crystallized by the excimer laser 106, 350- In some cases, the step of heat-treating the substrate 101 at a temperature of 500 ° C. may be performed. The processing time is about 10 to 180 minutes, and the processing atmosphere is vacuum, nitrogen atmosphere, oxygen atmosphere or air.
【００１６】〔実施例２〕図２は本発明により作製した
薄膜トランジスタを示す。ガラス基板２０１の上には、
遮光用金属薄膜として遮光層２０２が形成されている。
その上部に絶縁層として酸化シリコン薄膜２０３を堆積
する。さらに非晶質シリコン薄膜を堆積し、膜中の水素
の一部を脱離させるための熱処理を行う。その後に前記
の非晶質シリコン薄膜を多結晶シリコン薄膜にするた
め、エキシマレーザーを非晶質シリコン薄膜に照射す
る。Example 2 FIG. 2 shows a thin film transistor manufactured according to the present invention. On the glass substrate 201,
A light shielding layer 202 is formed as a light shielding metal thin film.
A silicon oxide thin film 203 is deposited on top of it as an insulating layer. Further, an amorphous silicon thin film is deposited, and heat treatment is performed to remove part of hydrogen in the film. After that, in order to make the amorphous silicon thin film into a polycrystalline silicon thin film, the amorphous silicon thin film is irradiated with an excimer laser.
【００１７】次にゲート絶縁膜２０５を堆積し、ゲート
電極２０６の形成を行う。続いてソース・ドレイン領域
２０４にドーピングを行い、第１の層間絶縁膜２０７を
堆積する。次にＩＴＯを画素電極２０９として形成し、
第２の層間絶縁膜２０８を堆積する。続いてコンタクト
ホールを形成した後、ソース・ドレイン電極２１０を形
成し、保護膜２１１を堆積する。最後に画素部を開口し
て薄膜トランジスタが完成する。Next, a gate insulating film 205 is deposited and a gate electrode 206 is formed. Then, the source / drain regions 204 are doped to deposit a first interlayer insulating film 207. Next, ITO is formed as the pixel electrode 209,
A second interlayer insulating film 208 is deposited. Subsequently, after forming contact holes, source / drain electrodes 210 are formed and a protective film 211 is deposited. Finally, the pixel portion is opened to complete the thin film transistor.
【００１８】この薄膜トランジスタを液晶表示装置に用
いることにより、アレイ基板側から投射光２１２を照射
しても半導体のチャネル領域２０４’に光は照射されず
に、光電流の発生を防ぐことができる。By using this thin film transistor in a liquid crystal display device, even if the projection light 212 is irradiated from the array substrate side, the semiconductor channel region 204 'is not irradiated with light and the generation of photocurrent can be prevented.
【００１９】[0019]
【発明の効果】以上のように本発明によると、マスク１
枚で半導体薄膜と半導体薄膜下層の遮光用の金属薄膜の
形成が可能となり、さらに遮光層と半導体層を自己整合
的に作製することが可能となる。As described above, according to the present invention, the mask 1
The semiconductor thin film and the metal thin film for shielding the lower layer of the semiconductor thin film can be formed by one sheet, and the light shielding layer and the semiconductor layer can be manufactured in a self-aligned manner.
【００２０】また、前記薄膜トランジスタを用いた液晶
表示装置は、ガラス基板の裏面より光を照射しても半導
体薄膜に直接に照射されることがなく、従って、光電流
の発生を防止することができる。そのため、オフ電流を
低く抑えることができ、良好な画質を得ることが可能と
なる。Further, in the liquid crystal display device using the thin film transistor, even if light is irradiated from the back surface of the glass substrate, the semiconductor thin film is not directly irradiated, so that the generation of photocurrent can be prevented. . Therefore, the off current can be suppressed to a low level, and good image quality can be obtained.
【図１】本発明による金属薄膜と半導体薄膜の自己整合
的な製造方法の断面図FIG. 1 is a cross-sectional view of a self-aligned manufacturing method of a metal thin film and a semiconductor thin film according to the present invention.
【図２】本発明により製造された薄膜トランジスタの断
面図FIG. 2 is a cross-sectional view of a thin film transistor manufactured according to the present invention.
１０１ ガラス基板 １０２ 遮光用金属薄膜 １０３ 絶縁性薄膜 １０４ 非晶質シリコン薄膜 １０５ 多結晶シリコン薄膜 １０６ エキシマレーザー １０７ レジスト １０８ 紫外光 ２０１ ガラス基板 ２０２ 遮光用金属薄膜 ２０３ 酸化シリコン ２０４ ソース・ドレイン領域 ２０４’ チャネル領域 ２０５ ゲート絶縁膜 ２０６ ゲート電極 ２０７ 第１の層間絶縁膜 ２０８ 第２の層間絶縁膜 ２０９ 画素電極 ２１０ ソース・ドレイン電極 ２１１ 保護膜 ２１２ 投射光 101 glass substrate 102 light-shielding metal thin film 103 insulating thin film 104 amorphous silicon thin film 105 polycrystalline silicon thin film 106 excimer laser 107 resist 108 ultraviolet light 201 glass substrate 202 light-shielding metal thin film 203 silicon oxide 204 source / drain region 204 'channel Region 205 Gate insulating film 206 Gate electrode 207 First interlayer insulating film 208 Second interlayer insulating film 209 Pixel electrode 210 Source / drain electrode 211 Protective film 212 Projected light
───────────────────────────────────────────────────── フロントページの続き (72)発明者 前川 茂樹 大阪府門真市大字門真1006番地 松下電器 産業株式会社内 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Shigeki Maekawa 1006 Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd.
Claims (5)
形成する第１の工程と、 前記金属薄膜の上に絶縁性薄膜を堆積する第２の工程
と、 前記絶縁性薄膜の上に非晶質シリコン薄膜を堆積する第
３の工程と、 前記非晶質シリコン薄膜を多結晶シリコン薄膜にする第
４の工程と、 前記多結晶シリコン薄膜の上にレジストを塗布し基板裏
面から露光し現像する第５の工程と、 パターンを形成した前記レジストで多結晶シリコン薄膜
をパターニングする第６の工程とを少なくとも有する薄
膜トランジスタの製造方法。1. A first step of forming a metal thin film in a predetermined shape on a transparent substrate, a second step of depositing an insulating thin film on the metal thin film, and a step of depositing the insulating thin film. A third step of depositing an amorphous silicon thin film thereon, a fourth step of converting the amorphous silicon thin film into a polycrystalline silicon thin film, and a resist applied on the polycrystalline silicon thin film to form a back surface of the substrate. A method of manufacturing a thin film transistor, comprising at least a fifth step of exposing and developing, and a sixth step of patterning a polycrystalline silicon thin film with the patterned resist.
を堆積し、第４の工程をなくした請求項１に記載の薄膜
トランジスタの製造方法。2. The method of manufacturing a thin film transistor according to claim 1, wherein a polycrystalline silicon thin film is deposited in the third step, and the fourth step is eliminated.
金属薄膜と、 前記金属薄膜の上に堆積された絶縁性薄膜と、 前記絶縁性薄膜の上に前記金属薄膜と同一形状で形成さ
れた半導体薄膜を有する薄膜トランジスタとを設けた液
晶表示装置。3. A metal thin film formed in a predetermined shape on a transparent substrate, an insulating thin film deposited on the metal thin film, and the same shape as the metal thin film on the insulating thin film. A liquid crystal display device provided with a thin film transistor having a semiconductor thin film formed in.
金属薄膜と、 前記金属薄膜の上に堆積された絶縁性薄膜と、 前記絶縁性薄膜の上に前記金属薄膜を覆うように形成さ
れた半導体薄膜を有する薄膜トランジスタとを設けた液
晶表示装置。4. A metal thin film formed in a predetermined shape on a translucent substrate, an insulating thin film deposited on the metal thin film, and a metal thin film covering the insulating thin film. And a thin film transistor having a semiconductor thin film formed on the liquid crystal display device.
ることを特徴をする請求項３〜４に記載の液晶表示装
置。5. The liquid crystal display device according to claim 3, wherein the semiconductor layer is a polycrystalline silicon thin film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4526496A JPH09246554A (en) | 1996-03-04 | 1996-03-04 | Manufacture of thin-film transistor and liquid-crystal display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4526496A JPH09246554A (en) | 1996-03-04 | 1996-03-04 | Manufacture of thin-film transistor and liquid-crystal display device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH09246554A true JPH09246554A (en) | 1997-09-19 |
Family
ID=12714447
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4526496A Pending JPH09246554A (en) | 1996-03-04 | 1996-03-04 | Manufacture of thin-film transistor and liquid-crystal display device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH09246554A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0984492A2 (en) * | 1998-08-31 | 2000-03-08 | Sel Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device comprising organic resin and process for producing semiconductor device |
| JP2002343970A (en) * | 2001-05-10 | 2002-11-29 | Koninkl Philips Electronics Nv | Method for manufacturing thin film transistor, thin film transistor manufactured by using the method, and liquid crystal display panel |
| CN104900710A (en) * | 2015-06-08 | 2015-09-09 | 京东方科技集团股份有限公司 | Thin film transistor and preparation method thereof, and array substrate |
| CN112542386A (en) * | 2020-11-03 | 2021-03-23 | 北海惠科光电技术有限公司 | Method and apparatus for manufacturing display panel and thin film transistor |
-
1996
- 1996-03-04 JP JP4526496A patent/JPH09246554A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0984492A2 (en) * | 1998-08-31 | 2000-03-08 | Sel Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device comprising organic resin and process for producing semiconductor device |
| EP0984492A3 (en) * | 1998-08-31 | 2000-05-17 | Sel Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device comprising organic resin and process for producing semiconductor device |
| JP2002343970A (en) * | 2001-05-10 | 2002-11-29 | Koninkl Philips Electronics Nv | Method for manufacturing thin film transistor, thin film transistor manufactured by using the method, and liquid crystal display panel |
| CN104900710A (en) * | 2015-06-08 | 2015-09-09 | 京东方科技集团股份有限公司 | Thin film transistor and preparation method thereof, and array substrate |
| CN112542386A (en) * | 2020-11-03 | 2021-03-23 | 北海惠科光电技术有限公司 | Method and apparatus for manufacturing display panel and thin film transistor |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100659921B1 (en) | Semiconductor device and the fabricating method therefor | |
| US6359320B1 (en) | Thin-film transistor with lightly-doped drain | |
| US5585647A (en) | Integrated circuit device having an insulating substrate, and a liquid crystal display device having an insulating substrate | |
| EP0797844A2 (en) | Electronic device manufacture | |
| JPH01241862A (en) | Manufacture of display device | |
| JP3296975B2 (en) | Thin film transistor and method of manufacturing the same | |
| JPH0964364A (en) | Manufacture of semiconductor device | |
| JPS6132471A (en) | Thin film transistor | |
| JP4785258B2 (en) | Semiconductor device and manufacturing method thereof | |
| JPS6113670A (en) | Method of producing thin film field effect transistor and transistor obtained by same method | |
| JPH09246554A (en) | Manufacture of thin-film transistor and liquid-crystal display device | |
| JPH0855993A (en) | Thin film transistor | |
| JP3175390B2 (en) | Thin film transistor and method of manufacturing the same | |
| JPH07120806B2 (en) | Method of manufacturing thin film field effect transistor | |
| JPH0691105B2 (en) | Method of manufacturing thin film transistor | |
| JPH07142737A (en) | Manufacture of thin-film transistor | |
| JPH0411226A (en) | Manufacture of display device | |
| JP2694912B2 (en) | Active matrix substrate manufacturing method | |
| JPH05206166A (en) | Thin film transistor | |
| JP3331642B2 (en) | Method for manufacturing thin film transistor | |
| KR100254924B1 (en) | Method of fabricating image display device | |
| JPH01236655A (en) | Thin film field-effect transistor and manufacture thereof | |
| JPH07193252A (en) | Thin film transistor and its manufacture | |
| JPH0562996A (en) | Manufacture of thin film transistor | |
| JP3192807B2 (en) | Method for manufacturing thin film transistor |