JPH0562996A - Manufacture of thin film transistor - Google Patents
Manufacture of thin film transistorInfo
- Publication number
- JPH0562996A JPH0562996A JP4017591A JP4017591A JPH0562996A JP H0562996 A JPH0562996 A JP H0562996A JP 4017591 A JP4017591 A JP 4017591A JP 4017591 A JP4017591 A JP 4017591A JP H0562996 A JPH0562996 A JP H0562996A
- Authority
- JP
- Japan
- Prior art keywords
- film
- gate electrode
- resist film
- semiconductor film
- resist
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
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- Thin Film Transistor (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は薄膜トランジスタの製造
方法の改良に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improved method of manufacturing a thin film transistor.
【０００２】[0002]
【従来の技術】近年、薄膜トランジスタ（ＴＦＴ）は、
フラットパネルディスプレイ、イメ−ジセンサ、イメ−
ジバ−等のスイッチング素子として広く用いられてい
る。2. Description of the Related Art In recent years, thin film transistors (TFTs) are
Flat panel display, image sensor, image
It is widely used as a switching element such as a jig.
【０００３】例えば、薄膜トランジスタをガラス基板上
にマトリックス状に形成し、この薄膜トランジスタによ
って液晶セルへの印加電圧を制御するアクティブマトリ
ックス表示素子が知られている。この場合の代表的な逆
スタガ−ト型の薄膜トランジスタの製造方法を図２に示
す工程図に基づいて以下に説明する。For example, an active matrix display element is known in which thin film transistors are formed in a matrix on a glass substrate and the voltage applied to a liquid crystal cell is controlled by the thin film transistors. A typical method of manufacturing an inverted staggered thin film transistor in this case will be described below with reference to the process chart shown in FIG.
【０００４】即ち、ガラス基板（以下、基板と称する）
１上にゲ−ト電極２をパタ−ニングして形成した後(a)
、基板１及びゲ−ト電極２の上にプラズマＣＶＤ法に
よってゲ−ト絶縁膜３、半導体膜４及び表面保護膜５を
連続着膜する(b) 。次に、表面保護膜５をゲ−ト電極２
の上部にだけ残すようにパタ−ニングする(c) 。この
後、ソ−ス及びドレインのオ−ミック層としてｎ+ −ａ
−Ｓｉからなる半導体膜６を着膜し、表面保護膜５とオ
−バ−ラップする形にパタ−ニングする。さらに、半導
体膜６の上面にソ−ス電極７及びドレイン電極８を形成
する(d) 。That is, a glass substrate (hereinafter referred to as a substrate)
After forming the gate electrode 2 on 1 by patterning (a)
A gate insulating film 3, a semiconductor film 4 and a surface protective film 5 are continuously deposited on the substrate 1 and the gate electrode 2 by the plasma CVD method (b). Next, the surface protection film 5 is applied to the gate electrode 2
Pattern so that it is left only on the top of the (c). After that, n + -a is formed as an ohmic layer for the source and drain.
A semiconductor film 6 made of -Si is deposited and patterned so as to overlap the surface protection film 5. Further, the source electrode 7 and the drain electrode 8 are formed on the upper surface of the semiconductor film 6 (d).
【０００５】しかし、前述した製造方法ではゲ−ト電極
２と半導体膜６との間の重なりによる寄生容量及びチャ
ンネル部分の容量が大きくなり、ドレイン電圧が低下す
るという問題点があった。However, the above-mentioned manufacturing method has a problem that the drain voltage is lowered because the parasitic capacitance and the channel capacitance are increased due to the overlap between the gate electrode 2 and the semiconductor film 6.
【０００６】この問題点を解決するために、リフトオフ
法を用いてソ−ス及びドレインのオ−ミック層である半
導体膜６をパタ−ニングし、ゲ−ト電極２と半導体膜６
とのオ−バ−ラップを少なくする薄膜トランジスタの製
造方法が提案されている（特開昭６３−１５４７０号公
報）。In order to solve this problem, the semiconductor film 6 which is an ohmic layer of the source and the drain is patterned by using the lift-off method to obtain the gate electrode 2 and the semiconductor film 6.
There has been proposed a method for manufacturing a thin film transistor that reduces the overlap of the above (Japanese Patent Laid-Open No. 63-15470).
【０００７】この薄膜トランジスタの製造方法は、ガラ
ス基板上面にパタ−ン化したゲ−ト電極、第１の絶縁
膜、第１のアモルファスシリコン半導体膜、第２の絶縁
膜並びに第１レジスト膜を順次堆積した状態で前記ガラ
ス基板の下面側から、第１レジスト膜を露光して前記ゲ
−ト電極の上方にのみ第１レジスト膜を残し、この状態
で前記第２の絶縁膜をエッチングする。In this method of manufacturing a thin film transistor, a patterned gate electrode, a first insulating film, a first amorphous silicon semiconductor film, a second insulating film and a first resist film are sequentially formed on the upper surface of a glass substrate. In the deposited state, the first resist film is exposed from the lower surface side of the glass substrate to leave the first resist film only above the gate electrode, and in this state, the second insulating film is etched.
【０００８】その後、前記ゲ−ト電極上方の第１レジス
ト膜を除去した後、第２のアモルファスシリコン膜と第
２のレジスト膜とを順次堆積した状態で前記ガラス基板
の下面側から第２レジスト膜を露光して前記ゲ−ト電極
の上方にのみ第２レジスト膜を残し、この状態で第２の
レジスト膜及び第２のアモルファスシリコン膜の上面に
金属膜を被着する。After that, after removing the first resist film above the gate electrode, a second amorphous silicon film and a second resist film are sequentially deposited, and the second resist is applied from the lower surface side of the glass substrate. The film is exposed to leave the second resist film only above the gate electrode, and in this state, a metal film is deposited on the upper surfaces of the second resist film and the second amorphous silicon film.
【０００９】次いで第２レジスト膜を溶解除去して前記
ゲ−ト電極の上方の前記金属膜を除去した後、残った金
属膜をマスクとして前記ゲ−ト電極の上方の第２のアモ
ルファスシリコン膜をエッチング除去してソ−ス電極と
ドレイン電極を形成するものである。Then, the second resist film is dissolved and removed to remove the metal film above the gate electrode, and then the remaining amorphous metal film is used as a mask to form a second amorphous silicon film above the gate electrode. Is removed by etching to form a source electrode and a drain electrode.
【００１０】これにより、ゲ−ト電極とソ−ス及びドレ
インのオ−ミック層である第２のアモルファスシリコン
膜とがオ−バ−ラップすることがなく、これらの間の寄
生容量及びチャンネル部分の容量を減少させることがで
きる。As a result, the gate electrode and the second amorphous silicon film, which is the ohmic layer of the source and drain, do not overlap with each other, and the parasitic capacitance and the channel portion between them do not occur. The capacity of can be reduced.
【００１１】[0011]
【発明が解決しようとする課題】しかしながら、前述し
た後者の薄膜トランジスタの製造方法においては、ガラ
ス基板の下面側から露光する工程が２回必要であると共
に、アモルファスシリコン膜を厚く形成すると下面側か
らの露光時間が非常に長くなり生産効率が悪くなるとい
う問題点があった。However, in the latter method of manufacturing a thin film transistor described above, the step of exposing from the lower surface side of the glass substrate is required twice, and when the amorphous silicon film is formed thickly, the lower surface side is exposed from the lower surface side. There is a problem that the exposure time becomes very long and the production efficiency deteriorates.
【００１２】本発明の目的は上記の問題点に鑑み、簡単
な工程で、ゲ−ト電極とオ−バラップしないソ−ス及び
ドレインのオ−ミック層を形成することができる薄膜ト
ランジスタの製造方法を提供することにある。In view of the above problems, an object of the present invention is to provide a method of manufacturing a thin film transistor capable of forming ohmic layers of a source and a drain which do not overlap the gate electrode by a simple process. To provide.
【００１３】[0013]
【課題を解決するための手段】本発明は上記の目的を達
成するために、透光性絶縁基板上にパタ−ン化したゲ−
ト電極を形成すると共に、第１の絶縁膜、第１の半導体
膜、第２の絶縁膜、第１のレジスト膜を順次堆積して着
膜した後、前記透光性絶縁基板の下面側から前記第１の
レジスト膜を露光して前記ゲ−ト電極の上方にのみ前記
第１のレジスト膜を残し、該第１のレジスト膜をマスク
として前記第２の絶縁膜をエッチング除去し、この状態
で電子サイクロトロン共鳴プラズマＣＶＤ法により前記
第１の半導体膜及び前記第１のレジスト膜の上面に第２
の半導体膜を着膜した後、前記第１のレジスト膜を溶解
除去して前記ゲ−ト電極の上方の前記第２の半導体膜を
除去することによりソ−ス及びドレインのオ−ミック層
を形成する薄膜トランジスタの製造方法を提案する。In order to achieve the above-mentioned object, the present invention provides a patterned gate on a translucent insulating substrate.
A first insulating film, a first semiconductor film, a second insulating film, and a first resist film, which are sequentially deposited and deposited, and then from the lower surface side of the translucent insulating substrate. The first resist film is exposed to light to leave the first resist film only above the gate electrode, and the second insulating film is removed by etching using the first resist film as a mask. Then, a second layer is formed on the upper surfaces of the first semiconductor film and the first resist film by electron cyclotron resonance plasma CVD.
After the first semiconductor film is deposited, the first resist film is dissolved and removed to remove the second semiconductor film above the gate electrode, thereby forming the source and drain ohmic layers. A method for manufacturing a thin film transistor to be formed is proposed.
【００１４】[0014]
【作用】本発明によれば、透光性絶縁基板上にパタ−ン
化したゲ−ト電極が形成されると共に、第１の絶縁膜、
第１の半導体膜、第２の絶縁膜、第１のレジスト膜が順
次堆積して着膜される。この後、前記透光性絶縁基板の
下面側から前記第１のレジスト膜が露光されて前記ゲ−
ト電極の上方にのみ前記第１のレジスト膜が残される。
次いで、この第１のレジスト膜をマスクとして前記第２
の絶縁膜がエッチング除去され、この状態で電子サイク
ロトロン共鳴プラズマＣＶＤ法により前記第１の半導体
膜及び前記第１のレジスト膜の上面に第２の半導体膜が
着膜される。この後、前記第１のレジスト膜は溶解除去
される。このとき前記ゲ−ト電極の上方の前記第２の半
導体膜も共に除去され、ゲ−ト電極にオ−バラップしな
いソ−ス及びドレインのオ−ミック層が形成される。According to the present invention, the patterned gate electrode is formed on the translucent insulating substrate, and the first insulating film,
The first semiconductor film, the second insulating film, and the first resist film are sequentially deposited and deposited. Then, the first resist film is exposed from the lower surface side of the transparent insulating substrate to expose the gate.
The first resist film is left only above the gate electrode.
Then, using the first resist film as a mask, the second
The insulating film is removed by etching, and in this state, the second semiconductor film is deposited on the upper surfaces of the first semiconductor film and the first resist film by the electron cyclotron resonance plasma CVD method. After that, the first resist film is dissolved and removed. At this time, the second semiconductor film above the gate electrode is also removed, and source and drain ohmic layers that do not overlap are formed on the gate electrode.
【００１５】[0015]
【実施例】以下、本発明の実施例を図面を用いて詳述す
る。Embodiments of the present invention will be described in detail below with reference to the drawings.
【００１６】図１は本発明の一実施例の薄膜トランジス
タの製造工程における薄膜トランジスタの要部を断面構
造で示したものである。FIG. 1 is a sectional view showing a main part of a thin film transistor in a manufacturing process of a thin film transistor according to an embodiment of the present invention.
【００１７】例えば、ガラス等からなる透明な絶縁基板
（以下、基板と称する）１１上にクロム（Ｃｒ）、タン
タル（Ｔａ）、或いはモリブデン（Ｍｏ）等の金属電極
を着膜した後、パタ−ニングしてゲ−ト電極１２を形成
する(a) 。次いで、プラズマＣＶＤ法により窒化シリコ
ン（ＳｉＮｘ）からなるゲ−ト絶縁膜１３、ｉ−ａ−Ｓ
ｉからなる半導体膜１４、窒化シリコンからなる表面保
護膜１５を順次、連続して着膜する(b) 。これらを連続
して着膜することは、半導体膜１４とゲ−ト絶縁膜１
３、表面保護膜１５との界面における不必要な界面準位
の形成を防ぎ、良好なトランジスタ特性を得るために必
要である。For example, after depositing a metal electrode such as chromium (Cr), tantalum (Ta) or molybdenum (Mo) on a transparent insulating substrate (hereinafter referred to as substrate) 11 made of glass or the like, a pattern is formed. To form the gate electrode 12 (a). Then, the gate insulating film 13 made of silicon nitride (SiN x ) and i-a-S are formed by the plasma CVD method.
The semiconductor film 14 made of i and the surface protection film 15 made of silicon nitride are sequentially and continuously deposited (b). The continuous deposition of these means that the semiconductor film 14 and the gate insulating film 1
3. It is necessary to prevent the formation of unnecessary interface states at the interface with the surface protective film 15 and obtain good transistor characteristics.
【００１８】この後、表面保護膜１５の上面にポジ型レ
ジストをスピン塗布し、基板１１の下面側から露光する
ことによって、ゲ−ト電極１２に自己整合されてパタ−
ン化したレジスト膜１６を形成する(c) 。After that, a positive type resist is spin-coated on the upper surface of the surface protective film 15 and exposed from the lower surface side of the substrate 11, so that the pattern is self-aligned with the gate electrode 12.
A resist film 16 which has been turned into a resist is formed (c).
【００１９】次に、ゲ−ト電極１２の上方にのみ残った
レジスト膜１６をマスクとして表面保護膜１５をエッチ
ングしてパタ−ン化する(d) 。この後、電子サイクロト
ロン共鳴（ＥＣＲ）プラズマＣＶＤ法により、室温にて
半導体膜１４及びレジスト膜１６の上面にｎ+ −ａ−Ｓ
ｉからなる半導体膜１７を着膜する(e) 。ＥＣＲプラズ
マＣＶＤ法は着膜の指向性が非常に強いので、半導体膜
１７がレジスト膜１６の側壁に付着することがない。ま
た、基板１１を室温として、半導体膜１７の着膜を行っ
た場合にも、高品質、即ち比抵抗の小さな半導体膜１７
を形成することができる。Next, the surface protection film 15 is etched and patterned using the resist film 16 remaining only above the gate electrode 12 as a mask (d). After that, n + -a-S is formed on the upper surfaces of the semiconductor film 14 and the resist film 16 at room temperature by an electron cyclotron resonance (ECR) plasma CVD method.
A semiconductor film 17 made of i is deposited (e). In the ECR plasma CVD method, the directivity of the deposited film is so strong that the semiconductor film 17 does not adhere to the side wall of the resist film 16. Further, even when the semiconductor film 17 is deposited with the substrate 11 at room temperature, the semiconductor film 17 having high quality, that is, a small specific resistance is obtained.
Can be formed.
【００２０】さらに、前述のように成膜した基板１１を
アセトン等の溶剤に浸漬し、レジスト膜１６を溶解除去
する。このとき、ゲ−ト電極１２の上方の半導体膜１
７、即ちレジスト膜１６の上面の半導体膜１７も共に除
去される(f) 。これにより、ゲ−ト電極１２にオ−バラ
ップしないソ−ス及びドレインのオ−ミック層が半導体
膜１７によって形成される。レジスト膜１６を剥離する
際、前述したように半導体膜１７の着膜を室温にて行っ
ているので、レジスト膜１６が変質することながなく、
レジスト膜１６を容易に剥離することができ、歩留まり
を高めることができる。Further, the substrate 11 formed as described above is dipped in a solvent such as acetone to dissolve and remove the resist film 16. At this time, the semiconductor film 1 above the gate electrode 12
7, that is, the semiconductor film 17 on the upper surface of the resist film 16 is also removed (f). As a result, the source and drain ohmic layers that do not overlap the gate electrode 12 are formed by the semiconductor film 17. When the resist film 16 is peeled off, since the semiconductor film 17 is deposited at room temperature as described above, the resist film 16 is not deteriorated.
The resist film 16 can be easily peeled off, and the yield can be increased.
【００２１】次に、半導体膜１４，１７を所定の形状に
パタ−ン化した後、これらの上に窒化シリコン等からな
る絶縁膜１８をプラズマＣＶＤ法によって着膜する。さ
らに、この絶縁膜１８にコンタクト孔１９，２０を形成
する。これらのコンタクト孔１９，２０は、ソ−ス及び
ドレインのオ−ミック層となる半導体膜１７のそれぞれ
の上部に対応すると共に、ゲ−ト電極１２から所定距離
の位置に形成する(g)。 この後、アルミニウム（Ａ
ｌ）等からなる金属膜を着膜し、ソ−ス電極２１及びド
レイン電極２２を形成する(h) 。このとき、ソ−ス電極
２１及びドレイン電極２２のそれぞれは、ゲ−ト電極１
２とオ−バラップしないように形成する。Next, after patterning the semiconductor films 14 and 17 into a predetermined shape, an insulating film 18 made of silicon nitride or the like is deposited thereon by plasma CVD. Further, contact holes 19 and 20 are formed in the insulating film 18. These contact holes 19 and 20 correspond to the upper portions of the semiconductor films 17 serving as the source and drain ohmic layers, respectively, and are formed at a predetermined distance from the gate electrode 12 (g). After this, aluminum (A
A metal film made of 1) or the like is deposited to form the source electrode 21 and the drain electrode 22 (h). At this time, the source electrode 21 and the drain electrode 22 are respectively connected to the gate electrode 1.
It is formed so as not to overlap with 2.
【００２２】前述したように本実施例によれば、簡単な
工程で、ゲ−ト電極とオ−バラップしないソ−ス及びド
レインのオ−ミック層を形成することができ、これらの
間の寄生容量及びチャンネル部分の容量を減少させるこ
とができる。これにより、ドレイン電圧の低下を防止す
ることができ、薄膜トランジスタの特性を向上させるこ
とができる。さらに、基板１１の下面側からの露光が１
回で済むと共に、レジスト膜１６のリフトオフを容易に
行うことができるので、生産効率を向上させることがで
きる。As described above, according to this embodiment, the source and drain ohmic layers which do not overlap the gate electrode can be formed by a simple process, and the parasitic layers between them can be formed. The capacity and the capacity of the channel portion can be reduced. As a result, the drain voltage can be prevented from decreasing and the characteristics of the thin film transistor can be improved. Furthermore, the exposure from the lower surface side of the substrate 11 is 1
The number of times is sufficient, and the lift-off of the resist film 16 can be easily performed, so that the production efficiency can be improved.
【００２３】尚、本実施例では、ＥＣＲプラズマＣＶＤ
法により形成する半導体膜１７（オ−ミック層）にｎ+
−ａ−Ｓｉを用いたが、ｎ型微結晶シリコンを用いても
同様の効果を得ることができる。In this embodiment, ECR plasma CVD is used.
N + on the semiconductor film 17 (ohmic layer) formed by the
Although -a-Si is used, the same effect can be obtained by using n-type microcrystalline silicon.
【００２４】[0024]
【発明の効果】以上説明したように本発明によれば、電
子サイクロトロン共鳴（ＥＣＲ）プラズマＣＶＤ法及び
リフトオフ法を用いることにより、ゲ−ト電極にオ−バ
ラップしないソ−ス及びドレインのオ−ミック層を簡単
に形成することができる。これにより、ドレイン電圧の
低下を防止することができ、薄膜トランジスタの特性を
向上させることができる。さらに、透光性絶縁基板の下
面側からの露光が１回で済むので、生産効率を向上させ
ることができるという優れた効果を発揮するものであ
る。As described above, according to the present invention, by using the electron cyclotron resonance (ECR) plasma CVD method and the lift-off method, the source and drain gates which do not overlap with the gate electrode can be formed. The Mick layer can be easily formed. As a result, the drain voltage can be prevented from decreasing and the characteristics of the thin film transistor can be improved. Furthermore, since the exposure from the lower surface side of the translucent insulating substrate only needs to be performed once, the excellent effect that the production efficiency can be improved is exhibited.
【図面の簡単な説明】[Brief description of drawings]
【図１】 本発明の薄膜トランジスタの製造方法を示す
工程図FIG. 1 is a process diagram showing a method of manufacturing a thin film transistor of the present invention.
【図２】 従来の薄膜トランジスタの製造方法の一例を
示す工程図FIG. 2 is a process chart showing an example of a conventional method of manufacturing a thin film transistor.
【符号の説明】 １１…基板、１２…ゲ−ト電極、１３…ゲ−ト絶縁膜、
１４，１７…半導体膜、１５…表面保護膜、１６…レジ
スト膜、１８…絶縁膜、１９，２０…コンタクト孔、２
１…ソ−ス電極、２２…ドレイン電極。[Explanation of symbols] 11 ... Substrate, 12 ... Gate electrode, 13 ... Gate insulating film,
14, 17 ... Semiconductor film, 15 ... Surface protective film, 16 ... Resist film, 18 ... Insulating film, 19, 20 ... Contact hole, 2
1 ... Source electrode, 22 ... Drain electrode.
Claims (1)
ト電極を形成すると共に、 第１の絶縁膜、第１の半導体膜、第２の絶縁膜、第１の
レジスト膜を順次堆積して着膜した後、 前記透光性絶縁基板の下面側から前記第１のレジスト膜
を露光して前記ゲ−ト電極の上方にのみ前記第１のレジ
スト膜を残し、 該第１のレジスト膜をマスクとして前記第２の絶縁膜を
エッチング除去し、 この状態で電子サイクロトロン共鳴プラズマＣＶＤ法に
より前記第１の半導体膜及び前記第１のレジスト膜の上
面に第２の半導体膜を着膜した後、 前記第１のレジスト膜を溶解除去して前記ゲ−ト電極の
上方の前記第２の半導体膜を除去することによりソ−ス
及びドレインのオ−ミック層を形成する、 ことを特徴とする薄膜トランジスタの製造方法。1. A patterned gate on a translucent insulating substrate.
A first insulating film, a first semiconductor film, a second insulating film, and a first resist film, which are sequentially deposited and deposited, and then from the lower surface side of the translucent insulating substrate. The first resist film is exposed to light to leave the first resist film only above the gate electrode, and the second insulating film is removed by etching using the first resist film as a mask. After depositing a second semiconductor film on the upper surfaces of the first semiconductor film and the first resist film by electron cyclotron resonance plasma CVD method, the first resist film is dissolved and removed to remove the gate. A method for manufacturing a thin film transistor, comprising forming the source and drain ohmic layers by removing the second semiconductor film above the electrodes.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4017591A JPH0562996A (en) | 1991-03-06 | 1991-03-06 | Manufacture of thin film transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4017591A JPH0562996A (en) | 1991-03-06 | 1991-03-06 | Manufacture of thin film transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0562996A true JPH0562996A (en) | 1993-03-12 |
Family
ID=12573440
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4017591A Pending JPH0562996A (en) | 1991-03-06 | 1991-03-06 | Manufacture of thin film transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0562996A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006190852A (en) * | 2005-01-07 | 2006-07-20 | Future Vision:Kk | Thin-film transistor and liquid crystal display using the same |
| CN100371816C (en) * | 2005-03-22 | 2008-02-27 | 友达光电股份有限公司 | TFT array substrate of liquid crystal display, liquid crystal display panel and its mfg. method |
| JP2008511999A (en) * | 2004-09-01 | 2008-04-17 | ハネウェル・インターナショナル・インコーポレーテッド | Amorphous silicon thin film transistor and manufacturing method thereof |
| JP2011155303A (en) * | 2006-04-21 | 2011-08-11 | Beijing Boe Optoelectronics Technology Co Ltd | Tft-lcd array substrate and method of manufacturing the same |
-
1991
- 1991-03-06 JP JP4017591A patent/JPH0562996A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008511999A (en) * | 2004-09-01 | 2008-04-17 | ハネウェル・インターナショナル・インコーポレーテッド | Amorphous silicon thin film transistor and manufacturing method thereof |
| JP2006190852A (en) * | 2005-01-07 | 2006-07-20 | Future Vision:Kk | Thin-film transistor and liquid crystal display using the same |
| CN100371816C (en) * | 2005-03-22 | 2008-02-27 | 友达光电股份有限公司 | TFT array substrate of liquid crystal display, liquid crystal display panel and its mfg. method |
| JP2011155303A (en) * | 2006-04-21 | 2011-08-11 | Beijing Boe Optoelectronics Technology Co Ltd | Tft-lcd array substrate and method of manufacturing the same |
| US8642404B2 (en) | 2006-04-21 | 2014-02-04 | Beijing Boe Optoelectronics Technology Co., Ltd | Thin film transistor liquid crystal display array substrate and manufacturing method thereof |
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