JPH09203764A - Method for judging presence or absence of poorly connected lead by using four-terminal measuring method - Google Patents
Method for judging presence or absence of poorly connected lead by using four-terminal measuring methodInfo
- Publication number
- JPH09203764A JPH09203764A JP8031360A JP3136096A JPH09203764A JP H09203764 A JPH09203764 A JP H09203764A JP 8031360 A JP8031360 A JP 8031360A JP 3136096 A JP3136096 A JP 3136096A JP H09203764 A JPH09203764 A JP H09203764A
- Authority
- JP
- Japan
- Prior art keywords
- circuit board
- measured
- lead
- value
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Testing Of Short-Circuits, Discontinuities, Leakage, Or Incorrect Line Connections (AREA)
- Measurement Of Resistance Or Impedance (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は四端子測定法による
接続不良リードの有無判別方法に係り、さらに詳しく
は、実装部品のリードと回路パターンとの間の接続状態
の良否をその時々の検査環境条件に柔軟に対応させなが
らより高い信頼性をもって判別できるようにした四端子
測定法による接続不良リードの有無判別方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for determining the presence / absence of a connection failure lead by a four-terminal measurement method, and more specifically, a test environment for the quality of the connection between a lead of a mounted component and a circuit pattern at each time. The present invention relates to a method for determining the presence / absence of a defective connection lead by a four-terminal measurement method that enables flexible determination of conditions and determination with higher reliability.
【０００２】[0002]
【従来の技術】表面実装技術のもとで回路基板上に搭載
されるＩＣチップ等の実装部品は、リードを回路パター
ンにはんだ付けすることにより接続固定されるものであ
るため、はんだ付け不良により回路パターンに対しリー
ドが正しく接続されないこともある。2. Description of the Related Art Mounting components such as IC chips mounted on a circuit board based on the surface mounting technique are connected and fixed by soldering leads to a circuit pattern. The leads may not be properly connected to the circuit pattern.
【０００３】そして、このような接続不良リードの存在
は、回路基板が備えていなければならない所定の回路機
能を阻害する要因のひとつとなることから、その有無も
厳格にチェックされることになり、かかるチェックを経
ることにより良品と判断された回路基板のみが製品とし
てユーザーに提供されることになる。Since the presence of such a poorly connected lead is one of the factors that hinder the predetermined circuit function that the circuit board must have, the presence or absence thereof must be strictly checked. Only the circuit boards that are determined to be non-defective products are provided to the user as products through such checks.
【０００４】この場合、接続不良リードの有無をチェッ
クするために従来から採用されている手法は、回路基板
上の実装部品のリードと、該リードが接続されるべき回
路パターンとに対し四端子測定用プローブを各別に同時
接触させ、その際に得られる微小な抵抗値（以下、「計
測値」という。）を、接続不良リードの有無を判別をす
るための指標としてある幅をもたせて予め設定されてい
る基準範囲値と比較し、その範囲内にあれば接続良、範
囲外にあれば接続不良と判別することにより行われてい
る。なお、前記基準範囲値は、予め固定的に定められて
いる基準値に対し経験的に得られる上限幅と下限幅とを
付与し、これら上限幅と下限幅とで許容範囲を仕切るこ
とにより設定されている。In this case, the method conventionally used for checking the presence or absence of a poorly connected lead is a four-terminal measurement for the lead of a mounted component on a circuit board and the circuit pattern to which the lead is connected. The probe for each is simultaneously contacted separately, and the minute resistance value obtained at that time (hereinafter referred to as "measurement value") is set in advance with a certain width as an index for determining the presence or absence of a poorly connected lead. It is performed by comparing with a reference range value that is set, and if it is within the range, it is determined that the connection is good, and if it is outside the range, it is determined that the connection is bad. The reference range value is set by giving an empirically obtained upper limit width and lower limit width to a reference value that is fixedly fixed in advance, and dividing the allowable range by these upper limit width and lower limit width. Has been done.
【０００５】[0005]
【発明が解決しようとする課題】ところで、上記従来手
法によっても、実装部品のリードと回路パターンとの間
の接続状態を個別にチェックすることにより、非接続状
態と不完全接続状態とを含む接続不良リードの有無を判
別することはできる。By the way, even by the above-mentioned conventional method, by individually checking the connection state between the lead of the mounted component and the circuit pattern, the connection including the non-connection state and the incomplete connection state can be obtained. It is possible to determine whether there is a defective lead.
【０００６】一方、回路基板におけるリードと回路パタ
ーンとに対し四端子測定用プローブを接触させて抵抗値
を測定する場合、得られる計測値は、微小であるが故に
その時々における検査環境条件により同一仕様の回路基
板であっても、例えば図３において基板１と基板２とに
つきリードと回路パターンとが接続状態にある計測値
（抵抗値）の分布と非接続状態（足浮きリード）にある
計測値（抵抗値）の分布とを示す正規分布図にみられる
ように個々の回路基板により微妙に変動することにな
る。On the other hand, when the four-terminal measuring probe is brought into contact with the lead and the circuit pattern on the circuit board to measure the resistance value, the measured value obtained is very small and therefore the same depending on the inspection environment condition at that time. Even if the circuit board has the specifications, for example, in FIG. 3, the measurement value (resistance value) distribution in which the lead and the circuit pattern are connected to each other and the measurement value in the non-connection state (foot floating lead) in FIG. As can be seen from the normal distribution diagram showing the distribution of the value (resistance value), it varies slightly depending on each circuit board.
【０００７】しかし、前記基準値は、固定的な数値とし
て用いられており、この基準値を中心にして許容範囲
（基準範囲値）を画一的に設定してしまうと、現実の検
査環境条件の如何により良品を不良品として判別するお
それがある。このため、実際の基準範囲値は、個々の回
路基板により微妙に変動する微小抵抗値に対応させるべ
く、ある程度の幅をもたせた上限値と下限値を用意し、
これら上限値と下限値とで範囲を広げて仕切った許容範
囲（例えば図３における基板１と基板２との正規分布相
互を合成して仕切られる許容範囲）として設定せざるを
得なくなり、結果的に不完全接続状態にある接続不良リ
ードが存在していてもこれを良品と誤認して検査結果の
信頼性を損なってしまう不都合があった。However, the reference value is used as a fixed numerical value, and if the allowable range (reference range value) is uniformly set around this reference value, the actual inspection environment condition will be set. There is a possibility that a non-defective product may be determined as a defective product. For this reason, the actual reference range value has an upper limit value and a lower limit value with a certain width in order to correspond to a minute resistance value that slightly varies depending on each circuit board,
There is no choice but to set as an allowable range (for example, an allowable range in which the normal distributions of the substrate 1 and the substrate 2 in FIG. 3 are combined and partitioned) which is divided by expanding the upper limit value and the lower limit value. Even if there is a poorly connected lead in an incompletely connected state, there is a disadvantage that it is misidentified as a non-defective product and the reliability of the inspection result is impaired.
【０００８】また、このような不都合を回避するために
は、その時々の検査環境条件に合致する基準値を新規に
設定（例えば、図３における基板１の正規分布から基板
２の正規分布に変更）し、この新たな基準値を中心にし
て既定の上限幅と下限幅とを付与することにより前記基
準範囲値を設定し直す必要があり、作業的に非常に煩雑
になってしまう不具合があった。In order to avoid such an inconvenience, a reference value that matches the inspection environment condition at that time is newly set (for example, the normal distribution of the substrate 1 in FIG. 3 is changed to the normal distribution of the substrate 2). ) However, it is necessary to reset the reference range value by giving the predetermined upper limit width and lower limit width around this new reference value, and there is a problem that it becomes very complicated in work. It was
【０００９】本発明は従来手法にみられた上記課題に鑑
みなされたものであり、基準範囲値を設定し直すことな
く、検査結果の信頼性を向上させることができる四端子
測定法による接続不良リードの有無判別方法を提供する
ことにその目的がある。The present invention has been made in view of the above problems in the conventional method, and it is possible to improve the reliability of the inspection result without resetting the reference range value, and the connection failure by the four-terminal measurement method. Its purpose is to provide a method for determining the presence or absence of a lead.
【００１０】[0010]
【課題を解決するための手段】本発明は上記目的を達成
しようとするものであり、その構成上の特徴は、回路基
板上の実装部品のリードと、該リードが接続されるべき
回路パターンとの二点間で構成される被測定部位への接
触を自在に移動制御される四端子測定用プローブと、こ
れら四端子測定用プローブを経て取り込まれる電気的信
号から計測値を得る低抵抗測定回路と、前記計測値等に
基づき必要な演算処理を行う中央処理部と、演算後の処
理データ等を表示する表示器とを少なくとも備え、今回
検査すべき同一仕様の回路基板群中におけるサンプリン
グ用の回路基板の前記被測定部位のそれぞれから明白な
不良値を除いて個別に得られる複数の計測値につきその
平均値をまず求め、リード接続状態の良否を仕分けるた
めの正規分布範囲を前記平均値との関係に基づいて設定
した後、サンプリング用の前記回路基板の被測定部位と
対応するある１枚の回路基板の被測定部位から個別に得
られる計測値のそれぞれを予め設定されている前記正規
分布範囲との関係で各別に比較し、範囲内にあれば接続
良とし、範囲外にあれば接続不良と判別することにより
当該回路基板における接続不良リードの有無をチェック
し、このような判別処理を今回検査すべき各回路基板の
すべてに対し同様にして行うことにある。DISCLOSURE OF THE INVENTION The present invention is intended to achieve the above-mentioned object, and its structural feature is that the leads of the mounted components on the circuit board and the circuit pattern to which the leads are connected. A four-terminal measurement probe that is freely moved and controlled to contact the site to be measured composed of two points, and a low-resistance measurement circuit that obtains a measured value from an electrical signal captured through these four-terminal measurement probe. And a central processing unit for performing necessary arithmetic processing based on the measured values and the like, and a display for displaying the processed data after arithmetic, and for sampling in a circuit board group of the same specifications to be inspected this time. Normal distribution range for sorting the goodness of the lead connection state by first obtaining the average value of the multiple measured values obtained individually from each of the measured parts of the circuit board excluding the apparently bad values After setting based on the relationship with the average value, each of the measurement values individually obtained from the measured portion of one circuit board corresponding to the measured portion of the circuit board for sampling is set in advance. By comparing each with the above normal distribution range, if it is within the range, it is judged that the connection is good, and if it is out of the range, it is judged that the connection is bad and the presence or absence of the connection failure lead on the circuit board is checked. The same discrimination process is performed on all of the circuit boards to be inspected this time in the same manner.
【００１１】[0011]
【発明の実施の形態】図１は、本発明の実施に供される
基板検査装置の基本構成を模式的に示す説明図であり、
その全体は、回路基板２１上の実装部品２３のリード２
４と、該リード２４が接続されるべき回路パターン２２
との二点間で構成される被測定部位への接触を自在に移
動制御される四端子測定用プローブ１３，１４と、これ
ら四端子測定用プローブ１３，１４を経て取り込まれる
電気的信号から計測値を得る低抵抗測定回路１２と、前
記計測値等に基づき必要な演算処理を行う中央処理部
（ＣＰＵ）１１と、演算後の処理データ等を表示するＣ
ＲＴなどからなる表示器１５とを少なくとも備えて構成
されている。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is an explanatory view schematically showing the basic structure of a substrate inspection apparatus used for carrying out the present invention.
The whole is the lead 2 of the mounting component 23 on the circuit board 21.
4 and the circuit pattern 22 to which the lead 24 is to be connected
And four-terminal measurement probes 13 and 14 that are freely moved and controlled to contact the measured site composed of two points, and measured from the electrical signals taken through these four-terminal measurement probes 13 and 14. A low resistance measuring circuit 12 for obtaining a value, a central processing unit (CPU) 11 for performing necessary arithmetic processing based on the measured value and the like, and C for displaying processed data after the arithmetic and the like.
It is configured to include at least a display device 15 such as an RT.
【００１２】図２は、図１に示す基板検査装置に適用し
て実施される本発明方法の処理手順の概要を示すフロー
チャートであり、測定開始後、まず、今回検査する同一
仕様の回路基板２１中におけるサンプリング用の回路基
板２１の前記被測定部位、例えばＩＣリード列における
各リードとこれに対応する回路パターン（図１において
は実装部品２３の複数本のリード２４と、これらリード
２４との間で接続関係にある対応する各回路パターン２
２）からなる任意に選択される複数Ｎ箇所の各被測定部
位に対し四端子測定用プローブ１３，１４を用いて計Ｎ
回の連続測定が行われ、その計測値を取り込む。FIG. 2 is a flow chart showing an outline of a processing procedure of the method of the present invention applied to the board inspecting apparatus shown in FIG. 1. After the measurement is started, first, the circuit board 21 of the same specification to be inspected this time is firstly tested. Inside the sampled circuit board 21 for measurement, for example, each lead in the IC lead row and the corresponding circuit pattern (in FIG. 1, a plurality of leads 24 of the mounting component 23, and between these leads 24). Corresponding circuit patterns 2 that are connected with each other
2) using four-terminal measurement probes 13 and 14 for each of the plurality of arbitrarily selected N measurement target sites.
One continuous measurement is performed and the measured value is captured.
【００１３】次いで、サンプリング用の回路基板２１の
前記被測定部位のそれぞれから明白な不良値を除いて個
別に得られる複数の計測値（ここでは、不良値がないも
のとして説明する）につきその平均値（計Ｎ回の連続測
定により得られた各計測値についての平均値）を求めた
後、この平均値に対する各計測値の偏差、つまりユーザ
により経験的に把握されているばらつき（σ）を求める
ことにより、リード接続状態の良否を仕分けるための正
規分布範囲を前記平均値との関係に基づいて例えば図３
の基板１についての正規分布図に示すようにして設定す
る。Next, an average of a plurality of measurement values (here, described as having no defective value) individually obtained by excluding an apparent defective value from each of the measured portions of the circuit board 21 for sampling. After obtaining the value (average value for each measurement value obtained by a total of N times of continuous measurement), the deviation of each measurement value from this average value, that is, the variation (σ) empirically grasped by the user is calculated. By obtaining the normal distribution range for sorting the quality of the lead connection state based on the relationship with the average value, for example, FIG.
It is set as shown in the normal distribution chart of the substrate 1.
【００１４】しかる後、サンプリング用の前記回路基板
２１の被測定部位と対応する他の１枚の回路基板２１の
被測定部位から個別に得られる計測値（ｍN ）のそれぞ
れを予め良品範囲として設定されている前記正規分布範
囲との関係で各別に比較する。Thereafter, each of the measured values (m N ) individually obtained from the measured portion of the other circuit board 21 corresponding to the measured portion of the circuit board 21 for sampling is set in advance as a non-defective range. Comparisons are made for each in relation to the set normal distribution range.
【００１５】このとき、計測値（ｍN ）が前記正規分布
範囲に含まれるものであれば接続良、つまり、リード２
４と回路パターン２２とが正しくはんだ付けされた良品
状態にあると判別し、範囲外にあれば接続不良、つま
り、リード２４と回路パターン２２とが完全に離れてい
たり、接続関係は保っているもののはんだ付けが確実で
はない不良品状態にあると判別する。At this time, if the measured value (m N ) is within the normal distribution range, the connection is good, that is, the lead 2
4 and the circuit pattern 22 are correctly soldered and are in good condition, and if they are out of the range, the connection is defective, that is, the lead 24 and the circuit pattern 22 are completely separated, or the connection relationship is maintained. It is determined that the product is in a defective state where soldering is not reliable.
【００１６】かくして、今回検査すべき１枚の前記回路
基板２１の各被測定部位のすべて（Ｎ回）から得られた
計Ｎ個の計測値につき個別に上記判別処理を行い、これ
を終了した後に例えばＣＲＴなどの表示器１５に対し当
該回路基板２１における接続不良リードの有無について
の判別結果を表示する。In this way, the above-described discrimination processing is individually performed for the total N measured values obtained from all the measured portions (N times) of the one circuit board 21 to be inspected this time, and this is completed. After that, the result of determination as to the presence / absence of a defective connection lead on the circuit board 21 is displayed on the display 15 such as a CRT.
【００１７】このような一連の判別処理は、今回検査す
べき回路基板２１に対し個別に順次行われ、最終的にす
べての回路基板２１についてその良否がチェックされる
ことになる。A series of such discrimination processes are individually and sequentially performed on the circuit boards 21 to be inspected this time, and finally, the quality of all the circuit boards 21 is checked.
【００１８】本発明はこのようにして構成されているの
で、今回検査すべき各回路基板２１のすべてにつき接続
不良リードの有無をチェックしてその判別結果を表示器
１５に表示し、各回路基板２１の良否を確実に判別する
ことができる。Since the present invention is constructed in this way, the presence or absence of a connection failure lead is checked for all of the circuit boards 21 to be inspected this time, and the determination result is displayed on the display unit 15, and each circuit board is checked. The quality of 21 can be reliably determined.
【００１９】しかも、この場合、リード接続状態の良否
を仕分けるための前記正規分布範囲は、今回検査すべき
同一仕様の回路基板２１群中におけるサンプリング用の
回路基板２１から取り込まれた計測値に基づいて設定さ
れるものであるため、固定的に定められた基準値に基づ
いて設定される基準範囲値との関係で判別する従来手法
とは異なり、その時々の検査環境条件に柔軟に対応させ
ながら設定することができることになる。Further, in this case, the normal distribution range for sorting the quality of the lead connection state is based on the measurement value taken from the sampling circuit board 21 in the circuit board 21 group of the same specifications to be inspected this time. Since it is set based on a fixed reference value, it differs from the conventional method in which it is determined based on the relationship with the reference range value that is set based on a fixed reference value. It will be possible to set.
【００２０】このため、従来手法のように基準範囲値を
設定し直すという煩雑な作業を経ることなく、その時々
の検査環境条件に対応させた正規分布範囲のもとで接続
不良リードの有無を判別することができる結果、高い信
頼性を得ながら回路基板の良否判別を行うことができる
ことになる。For this reason, it is possible to determine whether or not there is a connection failure lead under the normal distribution range corresponding to the inspection environmental condition at that time, without the complicated work of resetting the reference range value unlike the conventional method. As a result of the determination, it is possible to determine the quality of the circuit board while obtaining high reliability.
【００２１】[0021]
【発明の効果】以上述べたように本発明によれば、今回
検査すべき各回路基板のすべてにつき接続不良リードの
有無をチェックしてその判別結果を表示器に表示し、各
回路基板の良否を確実に判別することができる。As described above, according to the present invention, all the circuit boards to be inspected this time are checked for the presence of defective connection leads, and the discrimination result is displayed on the display unit. Can be reliably determined.
【００２２】しかも、この場合、リード接続状態の良否
を仕分けるための前記正規分布範囲は、今回検査すべき
同一仕様の回路基板群中におけるサンプリング用の回路
基板から取り込まれた計測値に基づいて設定されるもの
であるため、従来手法とは異なり、その時々の検査環境
条件に柔軟に対応させながら設定することができること
になる。Moreover, in this case, the normal distribution range for classifying the quality of the lead connection state is set based on the measurement value taken from the sampling circuit board in the circuit board group of the same specifications to be inspected this time. Therefore, unlike the conventional method, the setting can be performed while flexibly corresponding to the inspection environment condition at each time.
【００２３】このため、従来手法のように基準範囲値を
設定し直すという煩雑な作業を経ることなく、その時々
の検査環境条件に対応させた正規分布範囲のもとで接続
不良リードの有無を判別することができる結果、高い信
頼性を得ながら回路基板の良否判別を行うことができ
る。For this reason, it is possible to determine whether or not there is a defective connection lead under the normal distribution range corresponding to the inspection environment condition at that time, without the complicated work of resetting the reference range value unlike the conventional method. As a result of being able to make the determination, it is possible to perform the quality determination of the circuit board while obtaining high reliability.
【図１】本発明の実施に供される基板検査装置の概略構
成を示す説明図である。FIG. 1 is an explanatory diagram showing a schematic configuration of a substrate inspection apparatus used for implementing the present invention.
【図２】本発明の処理手順を示す概略フローチャートで
ある。FIG. 2 is a schematic flowchart showing a processing procedure of the present invention.
【図３】同一仕様の回路基板であっても回路基板を異に
することにより計測値（抵抗値）の分布状態もその平均
値を中心に変動する様子を示すグラフ図である。FIG. 3 is a graph showing how the distribution state of measured values (resistance values) fluctuates around the average value by changing the circuit boards even if the circuit boards have the same specifications.
１１ 中央処理部 １２ 低抵抗測定回路 １３，１４ 四端子測定用プローブ １５ 表示器 ２１ 回路基板 ２２ 回路パターン ２３ 実装部品 ２４ リード 11 Central Processing Section 12 Low Resistance Measurement Circuit 13, 14 Four-Terminal Measurement Probe 15 Display 21 Circuit Board 22 Circuit Pattern 23 Mounting Component 24 Lead
Claims (1)
ードが接続されるべき回路パターンとの二点間で構成さ
れる被測定部位への接触を自在に移動制御される四端子
測定用プローブと、これら四端子測定用プローブを経て
取り込まれる電気的信号から計測値を得る低抵抗測定回
路と、前記計測値等に基づき必要な演算処理を行う中央
処理部と、演算後の処理データ等を表示する表示器とを
少なくとも備え、 今回検査すべき同一仕様の回路基板群中におけるサンプ
リング用の回路基板の前記被測定部位のそれぞれから明
白な不良値を除いて個別に得られる複数の計測値につき
その平均値をまず求め、リード接続状態の良否を仕分け
るための正規分布範囲を前記平均値との関係に基づいて
設定した後、サンプリング用の前記回路基板の被測定部
位と対応するある１枚の回路基板の被測定部位から個別
に得られる計測値のそれぞれを予め設定されている前記
正規分布範囲との関係で各別に比較し、範囲内にあれば
接続良とし、範囲外にあれば接続不良と判別することに
より当該回路基板における接続不良リードの有無をチェ
ックし、このような判別処理を今回検査すべき各回路基
板のすべてに対し同様にして行うことを特徴とする四端
子測定法による接続不良リードの有無判別方法。1. A four-terminal measuring device in which the contact between a lead of a mounted component on a circuit board and a circuit pattern to which the lead is to be connected is controlled to be freely contacted to a site to be measured. A probe, a low resistance measurement circuit that obtains a measurement value from an electrical signal captured through these four-terminal measurement probes, a central processing unit that performs necessary arithmetic processing based on the measurement value, etc., processing data after the arithmetic operation, etc. A plurality of measured values that are individually obtained from each of the measured parts of the circuit board for sampling in the circuit board group with the same specifications to be inspected this time, except for the apparent defective value. Then, the average value is first obtained, and the normal distribution range for sorting the quality of the lead connection state is set based on the relationship with the average value, and then the measured portion of the circuit board for sampling is measured. The respective measured values individually obtained from the measured portion of one circuit board corresponding to the above are compared with each other in relation to the preset normal distribution range, and if they are within the range, it is determined that the connection is good, If it is out of the range, the presence or absence of a connection failure lead in the circuit board is determined by determining connection failure, and such determination processing is similarly performed for all circuit boards to be inspected this time. A method for determining the presence or absence of poorly connected leads by the four-terminal measurement method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP03136096A JP3717578B2 (en) | 1996-01-25 | 1996-01-25 | Method of determining the presence or absence of poor connection leads by the four-terminal measurement method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP03136096A JP3717578B2 (en) | 1996-01-25 | 1996-01-25 | Method of determining the presence or absence of poor connection leads by the four-terminal measurement method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH09203764A true JPH09203764A (en) | 1997-08-05 |
| JP3717578B2 JP3717578B2 (en) | 2005-11-16 |
Family
ID=12329081
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP03136096A Expired - Fee Related JP3717578B2 (en) | 1996-01-25 | 1996-01-25 | Method of determining the presence or absence of poor connection leads by the four-terminal measurement method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3717578B2 (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006220590A (en) * | 2005-02-14 | 2006-08-24 | Nippon Mektron Ltd | Electrical inspection device for flexible printed board |
| US7564252B2 (en) | 2007-03-29 | 2009-07-21 | Nec Electronics Corporation | Semiconductor inspection apparatus |
| US8188756B2 (en) | 2002-02-14 | 2012-05-29 | Continental Automotive Gmbh | Method for determining the electrical resistance of an electrical supply lead to sensor elements and a sensor arrangement |
| JP2014115252A (en) * | 2012-12-12 | 2014-06-26 | Hioki Ee Corp | Examination apparatus, and examination method |
| CN111351989A (en) * | 2018-12-24 | 2020-06-30 | 北京小米移动软件有限公司 | Measuring method and device |
| CN113777471A (en) * | 2021-09-09 | 2021-12-10 | 杭州广立微电子股份有限公司 | Method for calibrating relative voltage offset error of measurement module |
-
1996
- 1996-01-25 JP JP03136096A patent/JP3717578B2/en not_active Expired - Fee Related
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8188756B2 (en) | 2002-02-14 | 2012-05-29 | Continental Automotive Gmbh | Method for determining the electrical resistance of an electrical supply lead to sensor elements and a sensor arrangement |
| JP2006220590A (en) * | 2005-02-14 | 2006-08-24 | Nippon Mektron Ltd | Electrical inspection device for flexible printed board |
| US7564252B2 (en) | 2007-03-29 | 2009-07-21 | Nec Electronics Corporation | Semiconductor inspection apparatus |
| JP2014115252A (en) * | 2012-12-12 | 2014-06-26 | Hioki Ee Corp | Examination apparatus, and examination method |
| CN111351989A (en) * | 2018-12-24 | 2020-06-30 | 北京小米移动软件有限公司 | Measuring method and device |
| CN111351989B (en) * | 2018-12-24 | 2022-06-03 | 北京小米移动软件有限公司 | Method and device for measuring loss value of machine |
| CN113777471A (en) * | 2021-09-09 | 2021-12-10 | 杭州广立微电子股份有限公司 | Method for calibrating relative voltage offset error of measurement module |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3717578B2 (en) | 2005-11-16 |
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