JPH09148714A - Manufacture of 3-dimensional molded circuit board - Google Patents
Manufacture of 3-dimensional molded circuit boardInfo
- Publication number
- JPH09148714A JPH09148714A JP30489495A JP30489495A JPH09148714A JP H09148714 A JPH09148714 A JP H09148714A JP 30489495 A JP30489495 A JP 30489495A JP 30489495 A JP30489495 A JP 30489495A JP H09148714 A JPH09148714 A JP H09148714A
- Authority
- JP
- Japan
- Prior art keywords
- metal layer
- dimensional molded
- primary
- resist film
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、回路基板の製造方
法に関し、特に樹脂よりなる立体成形体の表面に回路を
形成する立体成形回路基板の製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a circuit board, and more particularly to a method for manufacturing a three-dimensional molded circuit board in which a circuit is formed on the surface of a three-dimensional molded body made of resin.
【０００２】[0002]
【従来の技術】従来から、樹脂よりなる立体成形体の表
面に無電解めっきにより形成した金属膜の上にさらに電
気めっきにより形成した金属膜を形成してなる一次めっ
き金属層を形成し、この一次めっき金属層上に電着レジ
スト皮膜を形成し、次いで露光・現像して電着レジスト
皮膜のパターニングを行い、次いで一次めっき金属層の
露出部に二次めっき金属層を形成して回路部を形成し、
次いで残存する電着レジスト皮膜を除去して非回路部の
一次めっき金属層を露出させ、この非回路部の一次めっ
き金属層をエッチングにより除去して所望回路を形成す
る立体成形回路基板の製造方法が知られている。しか
し、一次めっき金属層と電着レジスト皮膜との密着力が
弱く、剥離する場合があり、その改善がもとめられてい
る。この改善のため、一次めっき金属層の表面を過酸化
水素によりソフトエッチングして粗化することも試みら
れているが、エッチング条件によっては一次めっき金属
層の膜厚が減少し下地が露出する現象が生じることがあ
った。また、このようなエッチング法では、電着レジス
ト皮膜の剥離を防げるほど密着力を向上させることが困
難であった。なお、電着レジスト皮膜の剥離が生じた場
合には、電着レジスト皮膜のパターンが損なわれるた
め、最終的に得られる立体成形回路基板の回路の不良を
引き起こす。2. Description of the Related Art Conventionally, a primary plating metal layer is formed by forming a metal film formed by electroplating on a metal film formed by electroless plating on the surface of a three-dimensional molded body made of resin. Form an electrodeposition resist film on the primary plating metal layer, then expose and develop to pattern the electrodeposition resist film, and then form a secondary plating metal layer on the exposed part of the primary plating metal layer to form a circuit part. Formed,
Then, the remaining electrodeposition resist film is removed to expose the primary plating metal layer of the non-circuit portion, and the primary plating metal layer of the non-circuit portion is removed by etching to form a desired circuit. It has been known. However, the adhesion between the primary plating metal layer and the electrodeposition resist film is weak, and there is a case where they are peeled off, and improvement thereof is desired. In order to improve this, it has been attempted to roughen the surface of the primary plating metal layer by soft etching with hydrogen peroxide, but depending on the etching conditions, the film thickness of the primary plating metal layer decreases and the underlying layer is exposed. May occur. Further, it is difficult for such an etching method to improve the adhesion so as to prevent peeling of the electrodeposition resist film. When the electrodeposition resist film is peeled off, the pattern of the electrodeposition resist film is impaired, causing a circuit defect in the finally obtained three-dimensional molded circuit board.
【０００３】[0003]
【発明が解決しようとする課題】本発明は上記のような
事情に鑑みてなされたものであって、本発明の目的は、
立体成形体の表面に一次めっき金属層を形成し、その上
に電着レジスト皮膜を形成し、次いで露光・現像して電
着レジスト皮膜のパターニングを行い、次いで一次めっ
き金属層の露出部に二次めっき金属層を形成して回路部
を形成し、次いで電着レジスト皮膜を除去して非回路部
の一次めっき金属層を露出させ、次いでこの一次めっき
金属層をエッチングにより除去して所望回路を形成する
立体成形回路基板の製造方法であって、電着レジスト皮
膜と一次めっき金属層の密着力を向上させて、現像後の
電着レジスト皮膜の剥離を防止できる製造方法を提供す
ることである。SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and an object of the present invention is to provide:
A primary plating metal layer is formed on the surface of the three-dimensional molded body, an electrodeposition resist film is formed on the surface, and then exposure / development is performed to pattern the electrodeposition resist film. A secondary plating metal layer is formed to form a circuit part, and then the electrodeposition resist film is removed to expose the primary plating metal layer of the non-circuit part, and then this primary plating metal layer is removed by etching to form a desired circuit. A method of manufacturing a three-dimensional molded circuit board to be formed, which is capable of improving the adhesion between the electrodeposition resist film and the primary plating metal layer and preventing the electrodeposition resist film from peeling after development. .
【０００４】[0004]
【課題を解決するための手段】請求項１に係る発明の立
体成形回路基板の製造方法は、樹脂よりなる立体成形体
の表面に一次めっき金属層を形成し、この一次めっき金
属層上に電着レジスト皮膜を形成し、次いで露光・現像
して電着レジスト皮膜のパターニングを行い、次いで一
次めっき金属層の露出部に二次めっき金属層を形成して
回路部を形成し、次いで残存する電着レジスト皮膜を除
去して非回路部の一次めっき金属層を露出させ、この非
回路部の一次めっき金属層をエッチングにより除去して
所望回路を形成する立体成形回路基板の製造方法におい
て、立体成形体の表面に形成する一次めっき金属層の表
面粗度がＲａで１．０〜５．０μｍであることを特徴と
する。According to a first aspect of the present invention, there is provided a method for manufacturing a three-dimensional molded circuit board, wherein a primary plated metal layer is formed on the surface of a three-dimensional molded body made of resin, and an electric charge is applied on the primary plated metal layer. Forming a coating resist film, then exposing and developing to pattern the electrodeposition resist film, then forming a secondary plating metal layer on the exposed portion of the primary plating metal layer to form a circuit portion, and then remaining electrode In the method for manufacturing a three-dimensional molding circuit board, the primary plating metal layer of the non-circuit portion is exposed by etching to remove the primary coating metal layer of the non-circuit portion and the desired circuit is formed by three-dimensional molding. The surface roughness of the primary plating metal layer formed on the surface of the body is 1.0 to 5.0 μm in Ra.
【０００５】請求項２に係る発明の立体成形回路基板の
製造方法は、請求項１記載の製造方法において、立体成
形体の表面に形成する一次めっき金属層が無電解めっき
により形成した金属膜の上にさらに電気めっきにより形
成した金属膜を形成してなる金属層であり、この電気め
っきに使用するめっき液の光沢剤の添加量を調整して一
次めっき金属層の表面粗度を制御することを特徴とす
る。According to a second aspect of the present invention, there is provided a method for producing a three-dimensional molded circuit board according to the first aspect, wherein the primary plating metal layer formed on the surface of the three-dimensional molded article is a metal film formed by electroless plating. It is a metal layer formed by further forming a metal film formed by electroplating on the surface, and controlling the surface roughness of the primary plating metal layer by adjusting the addition amount of the brightener in the plating solution used for this electroplating. Is characterized by.
【０００６】[0006]
【発明の実施の形態】本発明の立体成形回路基板の製造
方法の実施の形態を図１、図２を参照しながら説明す
る。本発明では図１（ａ）に示すように樹脂よりなる立
体成形体１を準備する。樹脂としては、例えば電気材料
として使用されるエポキシ樹脂、フェノール樹脂、不飽
和ポリエステル樹脂、液晶ポリマー等が使用でき、また
成形は射出成形法等の方法で行うことができる。この立
体成形体１の回路パターン形成面は、形成する回路の密
着力を向上させるために、例えば強アルカリ溶液等を用
いて粗面化することが好ましい。BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of a method for manufacturing a three-dimensional molded circuit board according to the present invention will be described with reference to FIGS. In the present invention, as shown in FIG. 1A, a three-dimensional molded body 1 made of resin is prepared. As the resin, for example, an epoxy resin, a phenol resin, an unsaturated polyester resin, a liquid crystal polymer or the like used as an electric material can be used, and the molding can be performed by a method such as an injection molding method. The circuit pattern forming surface of the three-dimensional molded body 1 is preferably roughened by using, for example, a strong alkaline solution in order to improve the adhesion of the circuit to be formed.
【０００７】次いで、図１（ｂ）に示すように立体成形
体１の回路パターン形成面に、一次めっき金属層４を形
成する。この一次めっき金属層４の形成は、例えば無電
解めっき用の触媒（パラジウム等）を立体成形体１の表
面に付与した後、無電解めっきを施して無電解めっきに
よる金属膜２（一般には１〜２μｍ）を形成し、次いで
電気めっきを施して電気めっきによる金属膜３（一般に
は２０μｍ程度）を形成することにより行うことができ
る。本発明では、このステップで形成する一次めっき金
属層の表面粗度がＲａで１．０〜５．０μｍであること
が重要である。１．０μｍ未満の場合には後工程で形成
する電着レジスト皮膜との密着力を向上させることがで
きず、従って、現像後の電着レジスト皮膜の剥離を防止
することができない。また、５．０μｍを越える場合に
は、密着力のさらなる向上は期待できず、却って一次め
っき金属層の電気性能を損なうという問題が生じる恐れ
がある。Next, as shown in FIG. 1B, a primary plating metal layer 4 is formed on the circuit pattern forming surface of the three-dimensional molded body 1. The primary plating metal layer 4 is formed by, for example, applying a catalyst for electroless plating (palladium or the like) to the surface of the three-dimensional molded body 1, and then performing electroless plating to form the metal film 2 (generally 1 .About.2 .mu.m) and then electroplating to form the metal film 3 (generally about 20 .mu.m) by electroplating. In the present invention, it is important that the surface roughness Ra of the primary plating metal layer formed in this step is 1.0 to 5.0 μm. When the thickness is less than 1.0 μm, the adhesion with the electrodeposition resist film formed in the subsequent step cannot be improved, and therefore the peeling of the electrodeposition resist film after development cannot be prevented. On the other hand, when the thickness exceeds 5.0 μm, further improvement of the adhesive strength cannot be expected, and there is a possibility that the electric performance of the primary plating metal layer may be impaired.
【０００８】そして、一次めっき金属層の表面粗度をＲ
ａで１．０〜５．０μｍとする方法については、特に限
定するものではないが、一次めっき金属層４が無電解め
っきにより形成した金属膜２の上にさらに電気めっきに
より形成した金属膜３を形成してなる金属層であり、こ
の電気めっきに使用するめっき液の光沢剤の添加量を調
整して一次めっき金属層４の表面粗度をＲａで１．０〜
５．０μｍとすることが、容易に表面粗度を所望の範囲
内に制御できるので好ましい。The surface roughness of the primary plated metal layer is R
The method of setting a to 1.0 to 5.0 μm is not particularly limited, but the metal film 3 formed by electroplating on the metal film 2 formed by the electroless plating of the primary plating metal layer 4 is not particularly limited. The surface roughness of the primary plating metal layer 4 is 1.0 to Ra by adjusting the addition amount of the brightening agent of the plating solution used for this electroplating.
The thickness of 5.0 μm is preferable because the surface roughness can be easily controlled within a desired range.
【０００９】次いで、図１（ｃ）に示すように、一次め
っき金属層４上に例えば露光によって不溶化する樹脂を
用いて、電着法により電着レジスト皮膜５を形成する。
そして、図１（ｄ）に示すように、露光・現像して電着
レジスト皮膜５のパターニングを行う。その結果、電着
レジスト皮膜５が除去された部分では、一次めっき金属
層４が露出した状態となる。次いで、図２（ｅ）に示す
ように、この一次めっき金属層４の露出部に二次めっき
金属層６を形成して回路部を形成する。この二次めっき
金属層６の金属については、特に限定するものではない
が、一次めっき金属層のエッチングレジストとして作用
するものが好ましく、例えば一次めっき金属層４が銅で
ある場合には二次めっき金属層６の金属としてはニッケ
ルや金とすることが好ましい。Next, as shown in FIG. 1 (c), an electrodeposition resist film 5 is formed on the primary plating metal layer 4 by an electrodeposition method using a resin which is insolubilized by exposure, for example.
Then, as shown in FIG. 1D, the electrodeposition resist film 5 is patterned by exposure and development. As a result, in the portion where the electrodeposition resist film 5 is removed, the primary plating metal layer 4 is exposed. Next, as shown in FIG. 2E, a secondary plating metal layer 6 is formed on the exposed portion of the primary plating metal layer 4 to form a circuit portion. The metal of the secondary plating metal layer 6 is not particularly limited, but a metal that acts as an etching resist for the primary plating metal layer is preferable. For example, when the primary plating metal layer 4 is copper, the secondary plating is performed. The metal of the metal layer 6 is preferably nickel or gold.
【００１０】次いで、図２（ｆ）に示すように、残存す
る電着レジスト皮膜５を除去して非回路部の一次めっき
金属層４を露出させる。次いで、この非回路部の一次め
っき金属層４をエッチングにより除去して所望の回路７
を形成する。このエッチングに際しては、二次めっき金
属層６をエッチングレジストとしてもよく、また、二次
めっき金属層６の上に適当なエッチングレジストを被覆
するようにしてもよい。Then, as shown in FIG. 2 (f), the remaining electrodeposition resist film 5 is removed to expose the primary plating metal layer 4 of the non-circuit portion. Then, the primary plating metal layer 4 of the non-circuit portion is removed by etching to remove the desired circuit 7
To form In this etching, the secondary plating metal layer 6 may be used as an etching resist, or the secondary plating metal layer 6 may be coated with an appropriate etching resist.
【００１１】[0011]
【実施例】実施例及び比較例では液晶ポリマーを用いて
成形した立体成形体を使用し、回路パターンの形成面に
パラジウムの核付けを施した後、図１（ｂ）に示すよう
に銅をこの回路パターンの形成面全面に無電解めっきに
より析出させて金属膜２（厚み２μｍ）を形成し、次い
でその上に電気めっきにより金属膜３を形成して、一次
めっき金属層４を形成した。なお、実施例と比較例で電
気めっきに使用する電気銅めっき液は異なるものを使用
し、その組成を表１に示した。また、得られた一次めっ
き金属層４の表面粗度（Ｒａ）の測定結果も表１に示し
た。次いで、図１（ｃ）に示すようにネガ型の電着レジ
ストを用いて厚み１０μｍの電着レジスト皮膜５を電着
法で形成し、次いで図１（ｄ）に示すように露光・現像
して電着レジスト皮膜５のパターニング（線幅／線間の
間隔＝０．３ｍｍ／０．３ｍｍ）を行った。以上の加工
を行った後、図１（ｄ）に示すような残存する電着レジ
スト皮膜５についてテープ剥離試験を行い、現像後の電
着レジスト皮膜５の剥離箇所のあり、なしを実施例と比
較例について評価し、その結果を表１に示した。EXAMPLES In Examples and Comparative Examples, a three-dimensional molded body molded from a liquid crystal polymer was used, and after nucleating palladium on the surface on which the circuit pattern was formed, copper was formed as shown in FIG. 1 (b). A metal film 2 (thickness 2 μm) was formed on the entire surface on which the circuit pattern was formed by electroless plating, and then a metal film 3 was formed on the metal film 2 by electroplating to form a primary plated metal layer 4. Note that different electrolytic copper plating solutions were used for electroplating in Examples and Comparative Examples, and their compositions are shown in Table 1. Table 1 also shows the measurement results of the surface roughness (Ra) of the obtained primary plated metal layer 4. Next, as shown in FIG. 1 (c), a negative electrodeposition resist is used to form an electrodeposition resist film 5 having a thickness of 10 μm by an electrodeposition method, and then exposed and developed as shown in FIG. 1 (d). Then, the electrodeposition resist film 5 was patterned (line width / line spacing = 0.3 mm / 0.3 mm). After performing the above processing, a tape peeling test is performed on the remaining electrodeposition resist film 5 as shown in FIG. 1D, and there is a peeled portion of the electrodeposition resist film 5 after development with and without the embodiment. Comparative examples were evaluated, and the results are shown in Table 1.
【００１２】表１の結果から、本発明の実施例は比較例
に比べて、現像後の電着レジスト皮膜の剥離が生じ難く
なっていることが確認された。From the results shown in Table 1, it was confirmed that in the examples of the present invention, peeling of the electrodeposition resist film after development was less likely to occur than in the comparative examples.
【００１３】[0013]
【表１】 [Table 1]
【００１４】[0014]
【発明の効果】本発明では、立体成形体の表面に形成す
る一次めっき金属層の表面粗度がＲａで１．０〜５．０
μｍであるので、本発明によれば、電着レジスト皮膜と
一次めっき金属層の密着力が向上し、現像後の電着レジ
スト皮膜の剥離が防止されるので、最終的に得られる立
体成形回路基板の回路不良の発生率を低減することが可
能となる。According to the present invention, the surface roughness Ra of the primary plated metal layer formed on the surface of the three-dimensional molded body is 1.0 to 5.0.
According to the present invention, the adhesion between the electrodeposition resist film and the primary plating metal layer is improved and peeling of the electrodeposition resist film after development is prevented. It is possible to reduce the occurrence rate of circuit defects on the substrate.
【図１】本発明の実施の形態の前半の工程を説明する断
面図である。FIG. 1 is a cross-sectional view illustrating a first half process of an embodiment of the present invention.
【図２】本発明の実施の形態の後半の工程を説明する断
面図である。FIG. 2 is a cross-sectional view illustrating a latter half of the steps of the embodiment of the present invention.
１ 立体成形体 ２ 無電解めっきによる金属膜 ３ 電気めっきによる金属膜 ４ 一次めっき金属層 ５ 電着レジスト皮膜 ６ 二次めっき金属層 ７ 回路 1 Three-dimensional molded body 2 Metal film by electroless plating 3 Metal film by electroplating 4 Primary plating metal layer 5 Electrodeposition resist film 6 Secondary plating metal layer 7 Circuit
Claims (2)
っき金属層を形成し、この一次めっき金属層上に電着レ
ジスト皮膜を形成し、次いで露光・現像して電着レジス
ト皮膜のパターニングを行い、次いで一次めっき金属層
の露出部に二次めっき金属層を形成して回路部を形成
し、次いで残存する電着レジスト皮膜を除去して非回路
部の一次めっき金属層を露出させ、この非回路部の一次
めっき金属層をエッチングにより除去して所望回路を形
成する立体成形回路基板の製造方法において、立体成形
体の表面に形成する一次めっき金属層の表面粗度がＲａ
で１．０〜５．０μｍであることを特徴とする立体成形
回路基板の製造方法。1. A primary plating metal layer is formed on the surface of a three-dimensional molded body made of resin, an electrodeposition resist film is formed on the primary plating metal layer, and then exposure and development are performed to pattern the electrodeposition resist film. Then, the secondary plating metal layer is formed on the exposed portion of the primary plating metal layer to form the circuit portion, and then the remaining electrodeposition resist film is removed to expose the primary plating metal layer of the non-circuit portion. In a method of manufacturing a three-dimensional molded circuit board, wherein a primary circuit plated metal layer of a non-circuit portion is removed by etching to form a desired circuit, the surface roughness of the primary metal plated layer formed on the surface of the three-dimensional molded body is Ra.
Is 1.0 to 5.0 μm.
金属層が無電解めっきにより形成した金属膜の上にさら
に電気めっきにより形成した金属膜を形成してなる金属
層であり、この電気めっきに使用するめっき液の光沢剤
の添加量を調整して一次めっき金属層の表面粗度を制御
することを特徴とする請求項１記載の立体成形回路基板
の製造方法。2. A metal layer formed by forming a metal film formed by electroplating on a metal film formed by electroless plating, wherein the metal layer formed on the surface of the three-dimensional molded body is a metal layer formed by electroplating. The method for producing a three-dimensional molded circuit board according to claim 1, wherein the surface roughness of the primary plating metal layer is controlled by adjusting the amount of the brightening agent added to the plating solution used for.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP30489495A JPH09148714A (en) | 1995-11-24 | 1995-11-24 | Manufacture of 3-dimensional molded circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP30489495A JPH09148714A (en) | 1995-11-24 | 1995-11-24 | Manufacture of 3-dimensional molded circuit board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH09148714A true JPH09148714A (en) | 1997-06-06 |
Family
ID=17938572
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP30489495A Pending JPH09148714A (en) | 1995-11-24 | 1995-11-24 | Manufacture of 3-dimensional molded circuit board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH09148714A (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20030073919A (en) * | 2002-03-14 | 2003-09-19 | 주식회사 심텍 | The fabrication method of multi-layer printed circuit board using single etching semi-additive process |
| KR20030095758A (en) * | 2002-06-14 | 2003-12-24 | 주식회사 심텍 | Forming method of via stud |
| KR100443736B1 (en) * | 2002-04-22 | 2004-08-09 | 주식회사 코스모텍 | method for producing high-integrated multi-layer printed circuit board using bump |
| KR100709896B1 (en) * | 2006-02-28 | 2007-04-23 | 주식회사 두산 | Multilayer printed circuit board and method of manufacturing the same |
| JP2007335470A (en) * | 2006-06-12 | 2007-12-27 | Hitachi Cable Ltd | Method of forming conductor pattern |
| JP2008219018A (en) * | 2007-03-07 | 2008-09-18 | Samsung Electro Mech Co Ltd | Forming method of photoresist laminated circuit board using aerosol of metal nanoparticles, plating method of insulating substrate, surface treatment method of metal layer of circuit board, and manufacturing method of multilayer ceramic capacitor |
| JP2016213357A (en) * | 2015-05-11 | 2016-12-15 | アルプス電気株式会社 | Manufacturing method of wiring structure, and wiring structure manufactured by the manufacturing method |
-
1995
- 1995-11-24 JP JP30489495A patent/JPH09148714A/en active Pending
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20030073919A (en) * | 2002-03-14 | 2003-09-19 | 주식회사 심텍 | The fabrication method of multi-layer printed circuit board using single etching semi-additive process |
| KR100443736B1 (en) * | 2002-04-22 | 2004-08-09 | 주식회사 코스모텍 | method for producing high-integrated multi-layer printed circuit board using bump |
| KR20030095758A (en) * | 2002-06-14 | 2003-12-24 | 주식회사 심텍 | Forming method of via stud |
| KR100709896B1 (en) * | 2006-02-28 | 2007-04-23 | 주식회사 두산 | Multilayer printed circuit board and method of manufacturing the same |
| JP2007335470A (en) * | 2006-06-12 | 2007-12-27 | Hitachi Cable Ltd | Method of forming conductor pattern |
| JP2008219018A (en) * | 2007-03-07 | 2008-09-18 | Samsung Electro Mech Co Ltd | Forming method of photoresist laminated circuit board using aerosol of metal nanoparticles, plating method of insulating substrate, surface treatment method of metal layer of circuit board, and manufacturing method of multilayer ceramic capacitor |
| JP4741616B2 (en) * | 2007-03-07 | 2011-08-03 | サムソン エレクトロ−メカニックス カンパニーリミテッド． | Method for forming photoresist laminated substrate |
| US8003173B2 (en) | 2007-03-07 | 2011-08-23 | Samsung Electro-Mechanics Co., Ltd. | Method for forming a photoresist-laminated substrate, method for plating an insulating substrate, method for surface treating of a metal layer of a circuit board, and method for manufacturing a multi layer ceramic condenser using metal nanoparticles aerosol |
| JP2016213357A (en) * | 2015-05-11 | 2016-12-15 | アルプス電気株式会社 | Manufacturing method of wiring structure, and wiring structure manufactured by the manufacturing method |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4088544A (en) | Composite and method for making thin copper foil | |
| JPS60147192A (en) | Method of producing printed circuit board | |
| EP0497925A1 (en) | Method for printed circuit board pattern making using selectively etchable metal layers. | |
| JP2009260216A (en) | Method for manufacturing wiring board | |
| JPH09148714A (en) | Manufacture of 3-dimensional molded circuit board | |
| JP2002004077A (en) | Electroforming product and method for manufacturing the same | |
| JPH09279366A (en) | Production of fine structural parts | |
| JP5483658B2 (en) | Wiring board manufacturing method | |
| JP2001111201A (en) | Method of manufacturing wiring board and wiring board using the same | |
| JPH02113591A (en) | Manufacture of printed-wiring board | |
| KR20030044046A (en) | Use of metallic treatment on copper foil to produce fine lines and replace oxide process in printed circuit board production | |
| JP3934558B2 (en) | Stamper manufacturing method | |
| KR100275372B1 (en) | Method of manufacturing circuit board | |
| JP2003072021A (en) | Metal mask for printing | |
| JPH06346271A (en) | Nickel laminate and its production | |
| JPS59198792A (en) | Method of producing thick film fine pattern circuit | |
| JPH0373590A (en) | Manufacture of printed board | |
| JP3828205B2 (en) | Method for manufacturing transfer member and transfer member | |
| JP2531466B2 (en) | Method for manufacturing printed wiring board | |
| JP2002076573A (en) | Printed board and manufacturing method therefor | |
| JP3061206B2 (en) | Manufacturing method of metal mask | |
| JPH06130676A (en) | Production of mask for screen printing | |
| JPH02251195A (en) | Manufacture of printed wiring board | |
| US5210006A (en) | Process for preparing mounting tapes for automatic mounting of electronic components | |
| CN117936604A (en) | Metal grid line, preparation method and photovoltaic cell comprising metal grid line |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A02 | Decision of refusal |
Effective date: 20040525 Free format text: JAPANESE INTERMEDIATE CODE: A02 |