JPH08191110A - Driving and manufacturing method of memory cell capable of electrically writing and erasing - Google Patents
Driving and manufacturing method of memory cell capable of electrically writing and erasingInfo
- Publication number
- JPH08191110A JPH08191110A JP7002253A JP225395A JPH08191110A JP H08191110 A JPH08191110 A JP H08191110A JP 7002253 A JP7002253 A JP 7002253A JP 225395 A JP225395 A JP 225395A JP H08191110 A JPH08191110 A JP H08191110A
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- electrode
- substrate
- region
- floating gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
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- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、電気的に書き込み消去
可能なメモリセル（以下、ＥＥＰＲＯＭともいう）の駆
動方法及び製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving method and a manufacturing method of an electrically writable and erasable memory cell (hereinafter also referred to as an EEPROM).
【０００２】[0002]
【従来の技術】従来のＥＥＰＲＯＭでは、書き込みは、
ドレイン電界で加速した電子を薄いゲート絶縁膜を通し
て浮遊ゲート電極へ注入して行い、消去は、電界印加に
より浮遊ゲート電極からゲート絶縁膜を通じてソース領
域へ電子をトンネルさせて行っている。2. Description of the Related Art In a conventional EEPROM, writing is
The electrons accelerated by the drain electric field are injected into the floating gate electrode through the thin gate insulating film, and the erasing is performed by tunneling the electrons from the floating gate electrode to the source region through the gate insulating film by applying an electric field.
【０００３】[0003]
【発明が解決しようとする課題】上記した加速電子の書
き込み能率は高く、高速化が可能であるが、上記したト
ンネル電流による消去を高速化するにはソース領域に隣
接するゲート絶縁膜に印加する電界を強化せざるを得
ず、ゲート絶縁膜の絶縁劣化などの問題が生じた。本発
明は上記問題点に鑑みなされたものであり、消去時にお
けるゲート絶縁膜の劣化を抑止可能な電気的に書き込み
消去可能なメモリセルの駆動方法及び製造方法を提供す
ることを、その目的としている。The above-mentioned accelerated electron has a high writing efficiency and can be speeded up. However, in order to speed up the erase by the tunnel current, it is applied to the gate insulating film adjacent to the source region. There was no choice but to strengthen the electric field, and problems such as insulation deterioration of the gate insulating film occurred. The present invention has been made in view of the above problems, and an object thereof is to provide a driving method and a manufacturing method of an electrically writable / erasable memory cell capable of suppressing deterioration of a gate insulating film at the time of erasing. There is.
【０００４】[0004]
【課題を解決するための手段】本発明の第１の構成は、
一導電型の基板の表面部にゲート絶縁膜を介して配設さ
れた浮遊ゲート電極と、前記ゲート絶縁膜を挟んで前記
基板の表面部に形成された反対導電型のソース領域及び
ドレイン領域と、フィールド絶縁膜を挟んで前記基板上
に配設されて前記ソース領域又はドレイン領域に接続さ
れるとともに側面が側面絶縁膜を通じて前記浮遊ゲート
電極の側面に接する電極導体と、表面絶縁膜を挟んで前
記浮遊ゲート電極上に形成された制御電極とを備える電
気的に書き込み消去可能なメモリセルの駆動方法におい
て、前記電極導体と前記制御電極との間に所定の消去電
圧を印加することにより前記浮遊ゲート電極の前記電荷
を前記側面絶縁膜を通じて前記電極導体にトンネルさせ
て消去を行うことを特徴とする電気的に書き込み消去可
能なメモリセルの駆動方法である。The first structure of the present invention is as follows.
A floating gate electrode provided on the surface of a substrate of one conductivity type via a gate insulating film, and a source region and a drain region of opposite conductivity type formed on the surface of the substrate with the gate insulating film interposed therebetween. An electrode conductor that is disposed on the substrate with a field insulating film interposed therebetween and is connected to the source region or the drain region and has a side surface in contact with a side surface of the floating gate electrode through a side surface insulating film; In a method of driving an electrically writable and erasable memory cell including a control electrode formed on the floating gate electrode, the floating is performed by applying a predetermined erase voltage between the electrode conductor and the control electrode. In an electrically writable and erasable memory cell, the electric charge of the gate electrode is tunneled to the electrode conductor through the side surface insulating film to perform erasing. It is a dynamic way.
【０００５】本発明の第２の構成は、所定の表面領域に
フィールド酸化膜を形成するとともに残余の表面領域を
露出した一導電型の基板を準備し、前記基板と反対導電
型の高濃度不純物をドープしたポリシリコン層からなる
電極導体にて形成されたソース電極及びドレイン電極を
前記基板の露出表面上に互いに離れて配設し、前記両電
極の間にて露出する前記基板の前記露出表面及び前記両
電極の表面を酸化して前記両電極の側面に消去用トンネ
ル絶縁膜をなす側面絶縁膜を形成しかつ前記基板の前記
露出表面にゲート絶縁膜を形成し、更に堆積されたポリ
シリコン層をエッチバックして前記ゲート絶縁膜及び前
記側面絶縁膜に接して浮遊ゲート電極を形成し、前記ソ
ース電極、ドレイン電極及び浮遊ゲート電極の露出表面
に表面絶縁膜を形成し、前記表面絶縁膜を介して前記浮
遊ゲート電極上に制御電極を形成し、更に、前記各工程
の途中又はその後に加熱して前記ソース電極及びドレイ
ン電極から直下の前記基板の表面部へ前記不純物をドー
プしてソース領域及びドレイン領域を形成することを特
徴とする電気的に書き込み消去可能なメモリセルの駆動
方法である。A second structure of the present invention is to prepare a substrate of one conductivity type in which a field oxide film is formed in a predetermined surface region and the remaining surface region is exposed, and a high concentration impurity of the conductivity type opposite to the substrate is prepared. The exposed surface of the substrate, in which the source electrode and the drain electrode formed of an electrode conductor made of a doped polysilicon layer are spaced apart from each other on the exposed surface of the substrate, and exposed between the electrodes. And oxidizing the surfaces of both electrodes to form a side insulating film that forms an erasing tunnel insulating film on the side surfaces of both electrodes, forming a gate insulating film on the exposed surface of the substrate, and further depositing polysilicon. The layer is etched back to form a floating gate electrode in contact with the gate insulating film and the side insulating film, and a surface insulating film is formed on the exposed surface of the source electrode, the drain electrode and the floating gate electrode. Then, a control electrode is formed on the floating gate electrode via the surface insulating film, and further heated during or after each of the steps to the surface portion of the substrate immediately below from the source electrode and the drain electrode to the surface portion. A method for driving an electrically writable / erasable memory cell is characterized in that a source region and a drain region are formed by doping impurities.
【０００６】本発明の第３の構成は、上記第２の構成に
おいて更に、前記ソース電極及びドレイン電極が、等方
性エッチングで形成されることを特徴としている。本発
明の第４の構成は、上記第２の構成において更に、前記
ソース電極及びドレイン電極の少なくとも一方が、前記
側面絶縁膜に近接して不純物濃度が低濃度である低濃度
ドープ領域を有することを特徴としている。A third structure of the present invention is characterized in that, in the second structure, the source electrode and the drain electrode are formed by isotropic etching. In a fourth structure of the present invention, in addition to the second structure, at least one of the source electrode and the drain electrode has a low-concentration doped region having a low impurity concentration adjacent to the side surface insulating film. Is characterized by.
【０００７】[0007]
【作用及び発明の効果】本発明の第１の構成では、ソー
ス領域又はドレイン領域に接続される電極導体と制御電
極７との間に所定の消去電圧を印加することにより、側
面絶縁膜を通じて浮遊ゲート電極の電荷を電極導体へト
ンネルさせて消去を行う。このようにすれば、浮遊ゲー
ト電極からゲート絶縁膜を通じてトンネルされる電流密
度を削減でき、消去時におけるゲート絶縁膜に印加され
る電界強度を低減できるので、ゲート絶縁膜の劣化、損
傷を抑止することができ、また消去時における電極導体
と制御電極との間の印加電圧（消去電圧）を低減でき、
消去時間を短縮することができる。In the first structure of the present invention, by applying a predetermined erasing voltage between the electrode conductor connected to the source region or the drain region and the control electrode 7, floating through the side surface insulating film is achieved. The charge of the gate electrode is tunneled to the electrode conductor for erasing. By doing so, the current density tunneled from the floating gate electrode through the gate insulating film can be reduced, and the electric field strength applied to the gate insulating film at the time of erasing can be reduced, so that deterioration and damage of the gate insulating film can be suppressed. It is possible to reduce the applied voltage (erase voltage) between the electrode conductor and the control electrode at the time of erasing,
The erasing time can be shortened.
【０００８】なお、書き込みは、基板とドレイン領域と
の間に逆バイアス電圧を印加するとともに制御電極に所
定電圧を印加してことにより、基板（チャンネル）にて
加速された電荷をゲート絶縁膜を突き抜けて浮遊ゲート
電極へ注入して行うことができる他、ソース領域（又は
ドレイン領域）又は電極導体からゲート絶縁膜又は側面
絶縁膜をトンネルして浮遊ゲート電極へ電荷を注入して
もよい。For writing, a reverse bias voltage is applied between the substrate and the drain region and a predetermined voltage is applied to the control electrode so that the charges accelerated in the substrate (channel) are applied to the gate insulating film. Alternatively, the charge may be injected into the floating gate electrode by tunneling through the gate insulating film or the side surface insulating film from the source region (or drain region) or the electrode conductor.
【０００９】本発明の第２の構成では、上述した第１の
構成の電気的に書き込み消去可能なメモリセルを製造す
る際に、上記した製造工程を採用する。このようにすれ
ば、少なくとも消去用のトンネル絶縁膜である側面絶縁
膜を、少なくとも読み出し用のＭＯＳトランジスタのゲ
ート絶縁膜と同一工程で製造するので、製造工程の大幅
な簡単化が実現する。また、ソース領域及びドレイン領
域は、基板と反対導電型の高濃度不純物をドープしたポ
リシリコン層からなるソース電極及びドレイン電極から
基板の表面部への加熱再ドープで形成されるので、ソー
ス領域及びドレイン領域形成工程が簡単となり、それら
の接合容量を低減することができ、動作の高速化を実現
できる。In the second structure of the present invention, the above-mentioned manufacturing process is adopted when manufacturing the electrically writable / erasable memory cell of the above-mentioned first structure. By doing so, at least the side surface insulating film that is the tunnel insulating film for erasing is manufactured in the same process as at least the gate insulating film of the MOS transistor for reading, so that the manufacturing process is greatly simplified. Further, since the source region and the drain region are formed by heat re-doping from the source electrode and the drain electrode made of a polysilicon layer doped with a high-concentration impurity of the opposite conductivity type to the substrate to the surface portion of the substrate, The drain region forming process is simplified, the junction capacitance thereof can be reduced, and the operation speed can be increased.
【００１０】本発明の第３の構成では上記第２の構成に
おいて更に、ソース電極及びドレイン電極が等方性エッ
チングで形成されるので、ソース電極及びドレイン電極
の側面が斜めとなり、そのためにソース電極及びドレイ
ン電極の間に形成される浮遊ゲート電極の縦断面が逆台
形形状となり、その結果、読み出し用のＭＯＳＴのチャ
ンネル長を短縮して動作の高速化を実現できる。In the third structure of the present invention, further, in the second structure, the source electrode and the drain electrode are formed by isotropic etching, so that the side surfaces of the source electrode and the drain electrode are slanted, so that the source electrode is formed. The vertical cross section of the floating gate electrode formed between the drain electrode and the drain electrode has an inverted trapezoidal shape, and as a result, the channel length of the MOST for reading can be shortened and high-speed operation can be realized.
【００１１】本発明の第４の構成では、上記第２の構成
において更に、前記ソース電極及びドレイン電極の少な
くとも一方が、前記側面絶縁膜に近接して不純物濃度が
低濃度である低濃度ドープ領域を有するので、後述する
ようにゲート絶縁膜の劣化を抑止することができる。In a fourth structure of the present invention, in addition to the above-mentioned second structure, at least one of the source electrode and the drain electrode is in the vicinity of the side surface insulating film and has a low impurity concentration with a low impurity concentration. Therefore, the deterioration of the gate insulating film can be suppressed as will be described later.
【００１２】[0012]
【実施例】以下、本発明の一実施例を図１に基づき説明
する。Ｐ- 型のシリコン基板１０の表面にＬＯＣＯＳ法
によりシリコン酸化膜からなるフィールド絶縁膜１１を
形成し、その上に、例えばＣＶＤ法でポリシリコン層１
２を形成し、リンなどのイオン注入によりこのポリシリ
コン層１２をＮ+ 型とする（図１（ａ）参照）。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIG. A field insulating film 11 made of a silicon oxide film is formed on the surface of a P − type silicon substrate 10 by a LOCOS method, and a polysilicon layer 1 is formed on the field insulating film 11 by a CVD method, for example.
2 is formed, and the polysilicon layer 12 is made N + type by ion implantation of phosphorus or the like (see FIG. 1A).
【００１３】次に、ポリシリコン層１２をホトリソ法で
パターニングして本発明でいう電極導体を構成するソー
ス電極１ａ及びドレイン電極１ｂを形成する（図１
（ｂ）参照）。なお、ポリシリコン層１２のエッチング
は等方性ドライエッチング法（又は等方性ウエットエッ
チング法）で行う。これにより、ソース電極１ａ及びド
レイン電極１ｂの側面が所定傾斜角の斜面となる。Next, the polysilicon layer 12 is patterned by the photolithography method to form the source electrode 1a and the drain electrode 1b which constitute the electrode conductor of the present invention (FIG. 1).
(B)). The polysilicon layer 12 is etched by an isotropic dry etching method (or an isotropic wet etching method). As a result, the side surfaces of the source electrode 1a and the drain electrode 1b become slopes with a predetermined inclination angle.
【００１４】次に、例えば熱酸化法で露出する基板１０
の表面及びソース電極１ａ及びドレイン電極１ｂの上面
及び側面を酸化して、基板１０の表面にゲート絶縁膜３
を形成し、ソース電極１ａ及びドレイン電極１ｂの側面
に側面絶縁膜３ａ、３ｂを形成する（図１（ｃ）参
照）。なお、ここで、ゲート絶縁膜３の厚さは電子注入
可能な厚さ例えば１００〜３００オングストロームとさ
れる。Next, the substrate 10 is exposed by, for example, a thermal oxidation method.
Of the gate insulating film 3 on the surface of the substrate 10 by oxidizing the upper surface and the side surfaces of the source electrode 1a and the drain electrode 1b.
And side surface insulating films 3a and 3b are formed on the side surfaces of the source electrode 1a and the drain electrode 1b (see FIG. 1C). Here, the thickness of the gate insulating film 3 is set to a thickness at which electrons can be injected, for example, 100 to 300 angstrom.
【００１５】次に、例えばＣＶＤ法により所定の不純物
濃度にドープされたポリシリコン層を厚く堆積し、その
後、エッチバックしてソース電極１ａとドレイン電極１
ｂとの間においてゲート絶縁膜３上に浮遊ゲート電極５
を形成する（図１（ｄ）参照）。次に、例えば水蒸気酸
化法によりこれらソース電極１ａ及びドレイン電極１ｂ
並びに浮遊ゲート電極５の露出表面を酸化して表面絶縁
膜６を形成し、更にその後、例えばＣＶＤ法により形成
された低抵抗のポリシリコン層をホトリソ法でパターニ
ングして浮遊ゲート電極５の上に表面絶縁膜６を挟んで
制御電極７を形成し、加熱によりソース電極１ａ及びド
レイン電極１ｂから基板１０の表面にリンをオートドー
プしてＮ+ 型のソース領域８ａ及びドレイン領域８ｂを
形成する（図１（ｅ）参照）。Next, a polysilicon layer doped to a predetermined impurity concentration is deposited thickly by, for example, the CVD method, and then etched back to perform source electrode 1a and drain electrode 1
floating gate electrode 5 on the gate insulating film 3 between
Are formed (see FIG. 1D). Next, these source electrode 1a and drain electrode 1b are formed by, for example, a steam oxidation method.
Further, the exposed surface of the floating gate electrode 5 is oxidized to form a surface insulating film 6, and thereafter, a low resistance polysilicon layer formed by, for example, a CVD method is patterned by a photolithography method to form a surface on the floating gate electrode 5. The control electrode 7 is formed with the surface insulating film 6 sandwiched therebetween, and phosphorus is auto-doped from the source electrode 1a and the drain electrode 1b to the surface of the substrate 10 by heating to form the N + type source region 8a and the drain region 8b ( See FIG. 1E).
【００１６】次に、ＣＶＤ法などで層間絶縁膜（図示せ
ず）を堆積後、フィールド絶縁膜１１の上方においてソ
ース電極１ａ及びドレイン電極１ｂ上の絶縁膜６などを
開口してその上にアルミ線からなる電極線９ａ、９ｂを
形成し、電極線９ａ、９ｂとソース電極１ａ及びドレイ
ン電極１ｂとを個別に接続する（図２参照）。なお、本
実施例では、制御電極７は側面絶縁膜３ａ、３ｂを覆う
ように形成される。このようにすれば、側面絶縁膜３
ａ、３ｂへの不純物などの侵入を防止し、絶縁耐圧低下
を防止し、信頼性を向上することができる。Next, after depositing an interlayer insulating film (not shown) by a CVD method or the like, an insulating film 6 on the source electrode 1a and the drain electrode 1b is opened above the field insulating film 11 and an aluminum film is formed thereon. The electrode lines 9a and 9b made of lines are formed, and the electrode lines 9a and 9b are individually connected to the source electrode 1a and the drain electrode 1b (see FIG. 2). In this embodiment, the control electrode 7 is formed so as to cover the side surface insulating films 3a and 3b. In this way, the side surface insulating film 3
It is possible to prevent impurities and the like from penetrating into a and 3b, prevent a decrease in withstand voltage, and improve reliability.
【００１７】以下、このＥＥＰＲＯＭセルの動作を説明
する。１書き込みは、ドレイン領域８ｂ及び制御電極７
を正の高電位として、逆バイアスされたドレイン領域と
基板との間の表面ブレークダウン電圧を低下させて基板
表面部でのアバランシェ降伏でできた高エネルギ電子を
ゲート絶縁膜３を通じて浮遊ゲート電極５に注入する。
又は、ソース領域８ａからドレイン電極８ｂに流すチャ
ンネル電流をピンチオフしてホットエレクトロンを形成
してそれを浮遊ゲート電極５に注入する。又は、ドレイ
ン電極１ｂを低電位、制御電極７を正の高電位として基
板１０又はドレイン電極１ｂから浮遊ゲート電極５に電
子を直接トンネル注入する。The operation of this EEPROM cell will be described below. For one writing, the drain region 8b and the control electrode 7
Is set to a positive high potential, the surface breakdown voltage between the reverse-biased drain region and the substrate is lowered, and high-energy electrons generated by avalanche breakdown at the substrate surface portion are transferred through the gate insulating film 3 to the floating gate electrode 5 Inject.
Alternatively, the channel current flowing from the source region 8a to the drain electrode 8b is pinched off to form hot electrons and the hot electrons are injected into the floating gate electrode 5. Alternatively, electrons are directly tunnel-injected from the substrate 10 or the drain electrode 1b into the floating gate electrode 5 by setting the drain electrode 1b at a low potential and the control electrode 7 at a positive high potential.
【００１８】０書き込みは、制御電極７を低電位とし
て、上記注入を禁止する。読み出しは、選択された制御
電極７に中間電位を与え、ソース領域８ａ、ドレイン領
域８ｂ間に所定の電位差を与えて、チャンネル電流の大
小で１、０を判別する。消去は、ソース電極１ａに正の
高電位を与え、制御電極７に低電位を与えることによ
り、浮遊ゲート電極５から電子をソース電極１ａ及びソ
ース領域８ａへトンネル効果により抜き出して行う。In writing 0, the control electrode 7 is set to a low potential to inhibit the injection. For reading, an intermediate potential is applied to the selected control electrode 7, a predetermined potential difference is applied between the source region 8a and the drain region 8b, and 1 or 0 is discriminated depending on the magnitude of the channel current. Erasing is performed by applying a positive high potential to the source electrode 1a and a low potential to the control electrode 7 to extract electrons from the floating gate electrode 5 to the source electrode 1a and the source region 8a by the tunnel effect.
【００１９】（実施例２）他の実施例を図１を参照して
説明する。この実施例では、図１（ｃ）に示す側面絶縁
膜３ａ、３ｂ及びゲート絶縁膜３を形成するプロセスに
おいて、側面絶縁膜３ａ、３ｂよりゲート絶縁膜３の耐
圧力を相対的に向上させる方法を示す。(Embodiment 2) Another embodiment will be described with reference to FIG. In this embodiment, in the process of forming the side surface insulating films 3a and 3b and the gate insulating film 3 shown in FIG. 1C, a method of relatively improving the pressure resistance of the gate insulating film 3 relative to the side surface insulating films 3a and 3b. Indicates.
【００２０】すなわち、この実施例では、図１（ｃ）と
同様に、例えば熱酸化法で露出する基板１０の表面及び
ソース電極１ａ及びドレイン電極１ｂの上面及び側面を
酸化して、基板１０の表面にゲート絶縁膜３を形成し、
ソース電極１ａ及びドレイン電極１ｂの側面に側面絶縁
膜３ａ、３ｂを形成する。次に、ＣＶＤ法（プラズマＣ
ＶＤ法）にて窒化シリコン膜又は酸化シリコン膜を薄く
（例えば１００オングストローム以下）堆積する。この
時、この窒化シリコン膜又は酸化シリコン膜からなるＣ
ＶＤ膜の厚さはゲート絶縁膜３上では厚く形成されるも
のの、側面絶縁膜３ａ、３ｂ上にはほとんど形成されな
い。That is, in this embodiment, as in the case of FIG. 1C, the surface of the substrate 10 exposed by, for example, a thermal oxidation method and the upper surface and the side surface of the source electrode 1a and the drain electrode 1b are oxidized and the substrate 10 is exposed. Form the gate insulating film 3 on the surface,
Side surface insulating films 3a and 3b are formed on the side surfaces of the source electrode 1a and the drain electrode 1b. Next, the CVD method (plasma C
A silicon nitride film or a silicon oxide film is thinly deposited (for example, 100 angstroms or less) by VD method). At this time, C made of the silicon nitride film or the silicon oxide film is used.
Although the VD film is formed thick on the gate insulating film 3, it is hardly formed on the side surface insulating films 3a and 3b.
【００２１】したがって、このようにすれば選択的にゲ
ート絶縁膜３の電子注入又は抜き取りの能率を低下さ
せ、電子注入（書き込み）又は抜き取り（消去）を側面
絶縁膜３ａ、３ｂを通じて主として行うようにすること
ができる。特に、ゲート絶縁膜３と側面絶縁膜３ａ、３
ｂとを同一工程で形成する場合、ポリシリコンからなる
ソース電極１ａ及びドレイン電極１ｂの表面の酸化速度
が速く、どうしてもゲート絶縁膜３より側面絶縁膜３
ａ、３ｂの方が厚くなってしまうので、上記ＣＶＤ膜の
堆積は好都合である。Therefore, in this way, the efficiency of electron injection or extraction of the gate insulating film 3 is selectively reduced, and electron injection (writing) or extraction (erasing) is mainly performed through the side surface insulating films 3a and 3b. can do. In particular, the gate insulating film 3 and the side surface insulating films 3a, 3
In the case where b and b are formed in the same process, the surface of the source electrode 1a and the drain electrode 1b made of polysilicon has a high oxidation rate, and the side surface insulating film 3 is inevitably inferior to the gate insulating film 3 in that case.
The deposition of the above CVD film is convenient because the thicknesses of a and 3b become thicker.
【００２２】したがって、この実施例では、側面絶縁膜
３ａ又は３ｂを通じての電子のトンネル効果により消去
のみならず書き込みを行うことが好適である。 （実施例３）他の実施例を図３及び図４を参照して説明
する。Ｐ- 型のシリコン基板１０の表面にＬＯＣＯＳ法
によりシリコン酸化膜からなるフィールド絶縁膜１１を
形成し、その上に、例えばＣＶＤ法で所定の不純物濃度
を有するＮ型のポリシリコン層１２を形成し、更に、そ
の上にパターニングされたレジストマスク１００を形成
し、その後、リンなどのイオン注入によりポリシリコン
層１２の露出領域をＮ+ 型とする（図３（ａ）参照）。Therefore, in this embodiment, it is preferable to perform not only erasing but also writing by the tunnel effect of electrons through the side surface insulating film 3a or 3b. (Embodiment 3) Another embodiment will be described with reference to FIGS. A field insulating film 11 made of a silicon oxide film is formed on the surface of a P − type silicon substrate 10 by a LOCOS method, and an N type polysilicon layer 12 having a predetermined impurity concentration is formed thereon by a CVD method, for example. Further, a patterned resist mask 100 is further formed thereon, and then the exposed region of the polysilicon layer 12 is made into N + type by ion implantation of phosphorus or the like (see FIG. 3A).
【００２３】次に、レジストマスク１００を除去後、ポ
リシリコン層１２をホトリソ法でパターニングして本発
明でいう電極導体を構成するソース電極１ａ及びドレイ
ン電極１ｂを形成する（図３（ｂ）参照）。ここで重要
なことは、ソース電極１ａ及びドレイン電極１ｂの先端
部は上記マスキングによりＮ+ 型とはなっていないＮ型
領域部２ａ、２ｂをそれぞれ有することである。Next, after removing the resist mask 100, the polysilicon layer 12 is patterned by the photolithography method to form the source electrode 1a and the drain electrode 1b constituting the electrode conductor in the present invention (see FIG. 3B). ). What is important here is that the tip portions of the source electrode 1a and the drain electrode 1b have N-type region portions 2a and 2b which are not N + -type due to the masking.
【００２４】次に、例えば熱酸化法で露出する基板１０
の表面及びソース電極１ａ及びドレイン電極１ｂの上面
及び側面を酸化して、基板１０の表面にゲート絶縁膜３
を形成し、ソース電極１ａ及びドレイン電極１ｂの側面
に側面絶縁膜３ａ、３ｂを形成する（図３（ｃ）参
照）。なお、ここで、ゲート絶縁膜３の厚さは電子注入
可能な厚さ例えば１００〜３００オングストロームとさ
れる。Next, the substrate 10 exposed by, for example, a thermal oxidation method
Of the gate insulating film 3 on the surface of the substrate 10 by oxidizing the upper surface and the side surfaces of the source electrode 1a and the drain electrode 1b.
And side surface insulating films 3a and 3b are formed on the side surfaces of the source electrode 1a and the drain electrode 1b (see FIG. 3C). Here, the thickness of the gate insulating film 3 is set to a thickness at which electrons can be injected, for example, 100 to 300 angstrom.
【００２５】次に、例えばＣＶＤ法により所定の不純物
濃度にドープされたポリシリコン層を厚く堆積し、その
後、エッチバックしてソース電極１ａとドレイン電極１
ｂとの間においてゲート絶縁膜３上に浮遊ゲート電極５
を形成する（図３（ｄ）参照）。次に、例えば水蒸気酸
化法によりこれらソース電極１ａ及びドレイン電極１ｂ
並びに浮遊ゲート電極５の露出表面を酸化して表面絶縁
膜６を形成し、更にその後、例えばＣＶＤ法により形成
された低抵抗のポリシリコン層をホトリソ法でパターニ
ングして浮遊ゲート電極５の上に表面絶縁膜６を挟んで
制御電極７を形成し、加熱によりソース電極１ａ及びド
レイン電極１ｂから基板１０の表面にリンをオートドー
プしてＮ+ 型のソース領域８ａ及びドレイン領域８ｂを
形成する（図３（ｅ）参照）。Next, a polysilicon layer doped to a predetermined impurity concentration is deposited thickly by, for example, the CVD method, and then etched back to perform the source electrode 1a and the drain electrode 1.
floating gate electrode 5 on the gate insulating film 3 between
Are formed (see FIG. 3D). Next, these source electrode 1a and drain electrode 1b are formed by, for example, a steam oxidation method.
Further, the exposed surface of the floating gate electrode 5 is oxidized to form a surface insulating film 6, and thereafter, a low resistance polysilicon layer formed by, for example, a CVD method is patterned by a photolithography method to form a surface on the floating gate electrode 5. The control electrode 7 is formed with the surface insulating film 6 sandwiched therebetween, and phosphorus is auto-doped from the source electrode 1a and the drain electrode 1b to the surface of the substrate 10 by heating to form the N + type source region 8a and the drain region 8b ( See FIG. 3 (e).
【００２６】次に、ＣＶＤ法などで層間絶縁膜（図示せ
ず）を堆積後、フィールド絶縁膜１１の上方においてソ
ース電極１ａ及びドレイン電極１ｂ上の表面絶縁膜６な
どを開口してその上にアルミ線からなる電極線９ａ、９
ｂを形成し、電極線９ａ、９ｂとソース電極１ａ及びド
レイン電極１ｂとを個別に接続する（図４参照）。この
実施例で重要なことは、上記した図３（ｅ）におけるオ
ートドープにおいて、Ｎ型領域部２ａ、２ｂは他のソー
ス電極１ａ及びドレイン電極１ｂより低濃度であるの
で、Ｎ型領域部２ａ、２ｂの直下の基板表面に形成され
るソース領域８ａ及びドレイン領域８ｂの不純物濃度は
薄く、かつ、ドープ深さ及び横方向寸法は小さくなり、
浮遊ゲート電極５とのオーバーラップも小さくなること
である。したがって、本実施例によれば浮遊ゲート電極
５の寄生容量を低減でき、またソース領域８ａ又はドレ
イン領域８ｂと浮遊ゲート電極５との間のゲート絶縁膜
３にトンネル電流が集中するのを防止することができ
る。更に、本実施例によれば、上記したようにＮ型領域
部２ａ、２ｂ直下のソース領域８ａ及びドレイン領域８
ｂの不純物濃度が薄いので、消去時にソース領域８ａ又
はドレイン領域８ｂに高い正電圧を印加し、基板電位を
低電位とし、制御電極７を低電位とすれば、ソース領域
８ａ又はドレイン領域８ｂと基板との間の接合空乏層に
よりＮ型領域部２ａ、２ｂが空乏化して電圧を負担し、
これにより、ゲート絶縁膜３が薄くても、ゲート絶縁膜
３にてトンネルが生じたり、ゲート絶縁膜近傍にて降伏
が生じる前に側面絶縁膜３ａ又は３ｂを通じて浮遊ゲー
ト電極５からソース電極１ａ又はドレイン電極１ｂに電
子をトンネルさせて消去を安定に行うことができる点に
ある。したがって、本実施例では側面絶縁膜３ａ、３ｂ
がゲート絶縁膜３より多少厚くても、側面絶縁膜３ａ、
３ｂを用いてのトンネル電流による消去動作を確実とす
る。Next, after depositing an interlayer insulating film (not shown) by a CVD method or the like, a surface insulating film 6 on the source electrode 1a and the drain electrode 1b is opened above the field insulating film 11 and is formed thereon. Electrode wires 9a, 9 made of aluminum wire
b is formed, and the electrode lines 9a and 9b are individually connected to the source electrode 1a and the drain electrode 1b (see FIG. 4). What is important in this embodiment is that the N-type region portions 2a and 2b have a lower concentration than the other source electrode 1a and drain electrode 1b in the autodoping in FIG. 2b, the impurity concentration of the source region 8a and the drain region 8b formed on the surface of the substrate immediately below 2b is low, and the doping depth and lateral dimension are small.
The overlap with the floating gate electrode 5 is also small. Therefore, according to this embodiment, the parasitic capacitance of the floating gate electrode 5 can be reduced, and the tunnel current can be prevented from concentrating on the gate insulating film 3 between the source region 8a or the drain region 8b and the floating gate electrode 5. be able to. Further, according to the present embodiment, as described above, the source region 8a and the drain region 8 immediately below the N-type region portions 2a and 2b.
Since the impurity concentration of b is low, if a high positive voltage is applied to the source region 8a or the drain region 8b during erasing, the substrate potential is set to a low potential, and the control electrode 7 is set to a low potential, the source region 8a or the drain region 8b is formed. The N-type regions 2a and 2b are depleted by the junction depletion layer with the substrate and bear the voltage,
Thereby, even if the gate insulating film 3 is thin, before the tunnel occurs in the gate insulating film 3 or the breakdown occurs in the vicinity of the gate insulating film, the floating gate electrode 5 to the source electrode 1a or The point is that electrons can be tunneled to the drain electrode 1b to perform stable erasing. Therefore, in this embodiment, the side surface insulating films 3a and 3b are formed.
Is slightly thicker than the gate insulating film 3, the side surface insulating film 3a,
Ensure erase operation by tunneling current using 3b.
【００２７】なお、本実施例において書き込み動作自体
は、実施例１と同様とすることができる。The write operation itself in this embodiment can be the same as that in the first embodiment.
【図１】本発明のＥＥＰＲＯＭセルの製造工程の一例を
示す図である。FIG. 1 is a diagram showing an example of a manufacturing process of an EEPROM cell of the present invention.
【図２】図１のＥＥＰＲＯＭセルの断面図である。2 is a cross-sectional view of the EEPROM cell of FIG.
【図３】本発明のＥＥＰＲＯＭセルの製造工程の他例を
示す図である。FIG. 3 is a diagram showing another example of the manufacturing process of the EEPROM cell of the present invention.
【図４】図３のＥＥＰＲＯＭセルの断面図である。4 is a cross-sectional view of the EEPROM cell of FIG.
１０は基板、１１はフィールド絶縁膜、１ａはソース電
極（電極導体）、１ｂはドレイン電極（電極導体）、３
はゲート絶縁膜、３ａ、３ｂは側面絶縁膜、５は浮遊ゲ
ート電極、６は表面絶縁膜、７は制御電極。10 is a substrate, 11 is a field insulating film, 1a is a source electrode (electrode conductor), 1b is a drain electrode (electrode conductor), 3
Is a gate insulating film, 3a and 3b are side surface insulating films, 5 is a floating gate electrode, 6 is a surface insulating film, and 7 is a control electrode.
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 ＦＩ 技術表示箇所 Ｈ０１Ｌ 27/115 ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 6 Identification code Office reference number FI technical display location H01L 27/115
Claims (4)
介して配設された浮遊ゲート電極と、前記ゲート絶縁膜
を挟んで前記基板の表面部に形成された反対導電型のソ
ース領域及びドレイン領域と、フィールド絶縁膜を挟ん
で前記基板上に配設されて前記ソース領域又はドレイン
領域に接続されるとともに側面が側面絶縁膜を通じて前
記浮遊ゲート電極の側面に接する電極導体と、表面絶縁
膜を挟んで前記浮遊ゲート電極上に形成された制御電極
とを備える電気的に書き込み消去可能なメモリセルの駆
動方法において、 前記電極導体と前記制御電極との間に所定の消去電圧を
印加することにより前記浮遊ゲート電極の前記電荷を前
記側面絶縁膜を通じて前記電極導体にトンネルさせて消
去を行うことを特徴とする電気的に書き込み消去可能な
メモリセルの駆動方法。1. A floating gate electrode disposed on the surface of a substrate of one conductivity type with a gate insulating film interposed therebetween, and a source of opposite conductivity type formed on the surface of the substrate with the gate insulating film interposed therebetween. A region and a drain region, an electrode conductor disposed on the substrate with a field insulating film interposed therebetween, connected to the source region or the drain region, and having a side surface in contact with a side surface of the floating gate electrode through a side surface insulating film; A method of driving an electrically writable and erasable memory cell comprising a control electrode formed on the floating gate electrode with an insulating film interposed therebetween, wherein a predetermined erase voltage is applied between the electrode conductor and the control electrode. By doing so, the electric charge of the floating gate electrode is tunneled to the electrode conductor through the side surface insulating film to perform erasing, and electrically writing and erasing is possible. Driving method of memory cell.
するとともに残余の表面領域を露出した一導電型の基板
を準備し、 前記基板と反対導電型の高濃度不純物をドープしたポリ
シリコン層からなる電極導体にて形成されたソース電極
及びドレイン電極を前記基板の露出表面上に互いに離れ
て配設し、 前記両電極の間にて露出する前記基板の前記露出表面及
び前記両電極の表面を酸化して前記両電極の側面に消去
用トンネル絶縁膜をなす側面絶縁膜を形成しかつ前記基
板の前記露出表面にゲート絶縁膜を形成し、 更に堆積されたポリシリコン層をエッチバックして前記
ゲート絶縁膜及び前記側面絶縁膜に接して浮遊ゲート電
極を形成し、 前記ソース電極、ドレイン電極及び浮遊ゲート電極の露
出表面に表面絶縁膜を形成し、 前記表面絶縁膜を介して前記浮遊ゲート電極上に制御電
極を形成し、 更に、前記各工程の途中又はその後に加熱して前記ソー
ス電極及びドレイン電極から直下の前記基板の表面部へ
前記不純物をドープしてソース領域及びドレイン領域を
形成することを特徴とする電気的に書き込み消去可能な
メモリセルの製造方法。2. A one-conductivity-type substrate in which a field oxide film is formed on a predetermined surface region and the remaining surface region is exposed is prepared, and a polysilicon layer doped with a high-concentration impurity of a conductivity type opposite to the substrate is prepared. A source electrode and a drain electrode formed of an electrode conductor that are separated from each other on the exposed surface of the substrate, and the exposed surface of the substrate and the surface of the two electrodes exposed between the electrodes. Oxidation forms a side insulating film that forms an erasing tunnel insulating film on the side surfaces of both electrodes, forms a gate insulating film on the exposed surface of the substrate, and etches back the deposited polysilicon layer to form the gate insulating film. A floating gate electrode is formed in contact with the gate insulating film and the side surface insulating film, and a surface insulating film is formed on exposed surfaces of the source electrode, the drain electrode, and the floating gate electrode, and the surface insulating film is formed. A control electrode is formed on the floating gate electrode via the above, and further, during or after each of the steps, heating is performed to dope the impurity to the surface portion of the substrate immediately below the source electrode and the drain electrode to source the impurity. A method of manufacturing an electrically writable and erasable memory cell, which comprises forming a region and a drain region.
性エッチングで形成される請求項２記載の電気的に書き
込み消去可能なメモリセルの製造方法。3. The method for manufacturing an electrically writable / erasable memory cell according to claim 2, wherein the source electrode and the drain electrode are formed by isotropic etching.
とも一方は前記側面絶縁膜に近接して不純物濃度が低濃
度である低濃度ドープ領域を有する請求項２記載の電気
的に書き込み消去可能なメモリセルの製造方法。4. The electrically writable and erasable memory cell according to claim 2, wherein at least one of the source electrode and the drain electrode has a lightly doped region having a low impurity concentration adjacent to the side surface insulating film. Manufacturing method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7002253A JPH08191110A (en) | 1995-01-10 | 1995-01-10 | Driving and manufacturing method of memory cell capable of electrically writing and erasing |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7002253A JPH08191110A (en) | 1995-01-10 | 1995-01-10 | Driving and manufacturing method of memory cell capable of electrically writing and erasing |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH08191110A true JPH08191110A (en) | 1996-07-23 |
Family
ID=11524205
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7002253A Pending JPH08191110A (en) | 1995-01-10 | 1995-01-10 | Driving and manufacturing method of memory cell capable of electrically writing and erasing |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH08191110A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2003044868A1 (en) * | 2001-11-21 | 2003-05-30 | Sharp Kabushiki Kaisha | Semiconductor storage device, its manufacturing method and operating method, and portable electronic apparatus |
-
1995
- 1995-01-10 JP JP7002253A patent/JPH08191110A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2003044868A1 (en) * | 2001-11-21 | 2003-05-30 | Sharp Kabushiki Kaisha | Semiconductor storage device, its manufacturing method and operating method, and portable electronic apparatus |
| US7164167B2 (en) | 2001-11-21 | 2007-01-16 | Sharp Kabushiki Kaisha | Semiconductor storage device, its manufacturing method and operating method, and portable electronic apparatus |
| US7582926B2 (en) | 2001-11-21 | 2009-09-01 | Sharp Kabushiki Kaisha | Semiconductor storage device, its manufacturing method and operating method, and portable electronic apparatus |
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