JPH08153781A - Horizontal semiconductor device having high breakdown voltage and its using method - Google Patents
Horizontal semiconductor device having high breakdown voltage and its using methodInfo
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- JPH08153781A JPH08153781A JP24900995A JP24900995A JPH08153781A JP H08153781 A JPH08153781 A JP H08153781A JP 24900995 A JP24900995 A JP 24900995A JP 24900995 A JP24900995 A JP 24900995A JP H08153781 A JPH08153781 A JP H08153781A
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Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、二つの半導体基板
を酸化膜を介して貼り合わせた形の複合半導体基板にお
いて、半導体基板の主表面に平行な方向にキャリアが主
として流れ、その一方の主表面に設けられた電極から入
力および出力が行われる、いわゆる横型半導体装置およ
びその使用方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a composite semiconductor substrate in which two semiconductor substrates are bonded together via an oxide film, carriers mainly flow in a direction parallel to the main surface of the semiconductor substrate, and one main The present invention relates to a so-called lateral semiconductor device in which input and output are performed from electrodes provided on the surface and a method of using the same.
【０００２】[0002]
【従来の技術】従来、大電力を取り扱いうる半導体装置
の電力を扱う半導体素子部分、いわゆるパワー素子と呼
ばれるものは、キャリアの流れである電流が半導体基板
の主表面に対して垂直方向に流れる、いわゆるたて型半
導体素子とされることが多かった。この最大の理由を耐
圧特性からみると、以下の通りである。すなわち、耐圧
を決める基本式は、次式で与えられる。2. Description of the Related Art Conventionally, in a semiconductor element portion that handles a large amount of power in a semiconductor device that handles power, a so-called power element, a current that is a flow of carriers flows in a direction perpendicular to the main surface of a semiconductor substrate. It was often a so-called vertical semiconductor element. The maximum reason for this is as follows in terms of withstand voltage characteristics. That is, the basic formula for determining the breakdown voltage is given by the following formula.
【０００３】 ＶB ＝（１／２）・ＥCrit・ＬD （１） ここで、ＶB は素子の耐圧、ＬD は接合に電圧が印加さ
れた時にできる空乏層の幅である。ＥCritは接合の臨界
電界強度であって、素子内の電界がこの値を越えると、
降伏が起こる。ＥCritは接合の構造や形成方法、不純物
濃度などにより変化するが、基本的には（１）式から、
耐圧を決定する要因はＬD で決まり、空乏層が延びるこ
とのできる領域をどれだけ長くとれるかにかかってく
る。従って、チップサイズという点からみると、縦型素
子の方が有利であり、高耐圧素子においてたて型素子が
採用されている所以となっている。V B = (1/2) · E Crit · L D (1) Here, V B is the breakdown voltage of the element, and L D is the width of the depletion layer formed when a voltage is applied to the junction. E Crit is the critical electric field strength of the junction, and when the electric field in the device exceeds this value,
Surrender occurs. E Crit changes depending on the structure of the junction, the forming method, the impurity concentration, etc., but basically, from the equation (1),
The factor that determines the breakdown voltage is determined by L D , and depends on how long the region where the depletion layer can extend can be taken. Therefore, the vertical element is more advantageous in terms of chip size, which is the reason why the vertical element is used in the high breakdown voltage element.
【０００４】近年、パワー素子とＩＣとをモノリシツク
に集積化したいわゆる一チップパワーＩＣが注目される
に至って、パワー素子とＩＣとの製造工程のマッチング
という観点から、パワー素子を横型で形成する必要が生
じてきている。図６はｐｎ接合分離型半導体装置の例と
して、パワーＩＣの部分断面および電圧の印加方法を示
した図である。ｐ型基板１の表面にエピタキシャル法に
より素子領域２が形成され、表面から素子領域２を囲ん
でｐ型基板１に達するｐ分離領域３によって、素子領域
２が他の素子領域から分離されている。素子領域２の内
部には、簡単な素子として、バイポーラトランジスタの
ベース領域、コレクタ領域にあたるｐ拡散領域４とｎ拡
散領域５とが形成され、それらの上には、それぞれＢ、
Ｃ端子に接続された電極が設けられ、バイアス電圧ＶBC
が印加されている。ｐ型基板１にはパワーＩＣの電源電
圧の最低電位を印加して使用するのが普通である。例え
ば、電源が±１５Ｖであれば、基板１には−１５Ｖを印
加する。また、電源が＋５Ｖ単一であれば、基板１には
０Ｖ（グラウンド、ＧＮＤ）バイアスを引加する。図６
においては、バイアス電源ＶBCの負端子と基板１のＳ端
子とは、ともに接地され、ｐ型基板１の電位は０Ｖ（Ｇ
ＮＤ）に固定される。これにより、ｐ型基板１とｎ拡散
領域５との間の接合は、常に逆バイアス状態となり、基
板１と素子領域２とは、空乏層により分離される。な
お、このバイアス方式は特公昭４０−１７４１０号公報
に記載されている。In recent years, a so-called one-chip power IC in which a power element and an IC are monolithically integrated has been attracting attention, and it is necessary to form the power element in a horizontal type from the viewpoint of matching the manufacturing process of the power element and the IC. Is happening. FIG. 6 is a diagram showing a partial cross section of a power IC and a voltage application method as an example of a pn junction separation type semiconductor device. An element region 2 is formed on the surface of a p-type substrate 1 by an epitaxial method, and the element region 2 is separated from other element regions by a p isolation region 3 that surrounds the element region 2 from the surface and reaches the p-type substrate 1. . Inside the element region 2, a p-diffusion region 4 and an n-diffusion region 5 corresponding to a base region and a collector region of a bipolar transistor are formed as simple devices, and B and B are respectively formed on them.
An electrode connected to the C terminal is provided, and the bias voltage V BC
Is applied. It is usual to apply the lowest potential of the power supply voltage of the power IC to the p-type substrate 1 for use. For example, if the power source is ± 15V, −15V is applied to the substrate 1. If the power source is a single + 5V, a 0V (ground, GND) bias is applied to the substrate 1. Figure 6
, The negative terminal of the bias power supply V BC and the S terminal of the substrate 1 are both grounded, and the potential of the p-type substrate 1 is 0 V (G
Fixed to ND). As a result, the junction between the p-type substrate 1 and the n diffusion region 5 is always in the reverse bias state, and the substrate 1 and the element region 2 are separated by the depletion layer. This bias method is described in Japanese Patent Publication No. 40-17410.
【０００５】上記の従来のｐｎ接合分離法の問題点は、
大別して次の二つある。 （ａ）寄生素子効果 （ｂ）素子の高耐圧化 ｐ型基板１およびｐ分離領域３を素子領域２の最低電位
に固定しているものの、素子領域２に形成される素子に
対し、ｐｎｐ寄生トランジスタ等を形成し、サイリスタ
動作やＣ−ＭＯＳ素子のラッチアップ動作を招き易くな
る。これが寄生素子効果であって、これを避けるために
は、回路設計に種々の制約を受ける。また、素子の高耐
圧化については、ｐｎ接合分離を用いたＩＣでは、高耐
圧を得るためには、（１）式から分かるように、素子領
域２のｎエピタキシャル層の厚さを厚くする必要があ
り、このため、ｐ分離領域３が深くなり、同時にその横
方向拡散が大きくなって、素子の実効面積が減少する。
このため、実際上高耐圧化には、困難が伴う。The problems of the above-mentioned conventional pn junction isolation method are as follows.
There are two main categories. (A) Parasitic element effect (b) Higher breakdown voltage of the element Although the p-type substrate 1 and the p isolation region 3 are fixed to the lowest potential of the element region 2, a pnp parasitic is applied to the element formed in the element region 2. A transistor or the like is formed so that the thyristor operation and the latch-up operation of the C-MOS element are easily caused. This is a parasitic element effect, and in order to avoid this, various restrictions are imposed on the circuit design. Further, regarding the high breakdown voltage of the element, in the IC using the pn junction isolation, it is necessary to increase the thickness of the n epitaxial layer in the element region 2 in order to obtain the high breakdown voltage, as can be seen from the equation (1). Therefore, the p isolation region 3 becomes deep, and at the same time, its lateral diffusion becomes large, and the effective area of the device decreases.
Therefore, it is difficult to increase the breakdown voltage in practice.
【０００６】一方、素子分離に必要な面積を少なくし
て、素子の実効面積を増加できると共に、高耐圧が得ら
れる技術手段に対する市場のニーズは極めて大きい。こ
のニーズに応える素子分離構造として、近年、酸化膜を
挟んで接着した複合半導体基板と、深いトレンチとを組
み合わせた完全誘電体分離構造が提案されている。最
近、かかる完全誘電体分離構造を採用し、さらに高耐圧
にするための完全誘電体分離素子の使用方法が提案され
た（特開平４−３３６４４６号公報参照）。On the other hand, there is an extremely large market need for a technical means capable of increasing the effective area of an element by reducing the area required for element isolation and increasing the withstand voltage. As an element isolation structure that meets this need, in recent years, a complete dielectric isolation structure has been proposed in which a composite semiconductor substrate bonded with an oxide film sandwiched therebetween and a deep trench are combined. Recently, there has been proposed a method of using the perfect dielectric isolation element for adopting such a perfect dielectric isolation structure and further increasing the withstand voltage (see Japanese Patent Laid-Open No. 4-336446).
【０００７】図７は、完全誘電体分離型半導体装置の部
分断面とその使用方法を示した図である。第一の半導体
基板６と第二の半導体基板７とを酸化膜８を介して接合
した複合半導体基板と、第一半導体基板６の主表面から
酸化膜８に達する絶縁物を埋め込んだ分離溝９によっ
て、他の素子領域から分離された素子領域１０内にｐ拡
散領域１１とｎ拡散領域１２が形成されている半導体素
子において、第二半導体基板７の電位ＶS を第一半導体
基板６の素子領域１０内の最低電位（図７ではｐ拡散領
域１１に接続されたアース電位）より高い電位に固定す
ることにより、素子耐圧ＶB を上昇させる使用方法であ
る。FIG. 7 is a diagram showing a partial cross section of a completely dielectric isolation type semiconductor device and a method of using the same. A composite semiconductor substrate in which a first semiconductor substrate 6 and a second semiconductor substrate 7 are bonded together via an oxide film 8, and a separation groove 9 in which an insulator reaching the oxide film 8 from the main surface of the first semiconductor substrate 6 is embedded. In the semiconductor device in which the p diffusion region 11 and the n diffusion region 12 are formed in the device region 10 separated from other device regions by the above, the potential V S of the second semiconductor substrate 7 is set to the device of the first semiconductor substrate 6. This is a method of use in which the element breakdown voltage V B is increased by fixing the potential higher than the lowest potential in the region 10 (the ground potential connected to the p diffusion region 11 in FIG. 7).
【０００８】[0008]
【発明が解決しようとする課題】上の使用方法は有益で
はあるが、この方法による高耐圧素子の欠点は、下記の
点で浮き彫りにされる。すなわち、耐圧の設計方法が不
明であり、半導体素子を仕様に従って設計製造すること
ができない。この点は、前記の公報の中に開示されてい
る下記のような記述からも明らかである。 上記素子領域１０内の最低電位より高い電位は、試
行により再現性よく一義的に決定できる。 さらに、素子領域内の最低電位より高い電位には素
子耐圧を最大にする最適値があって、半導体装置が特定
されれば再現性よく決定できる電位である。Although the above method of use is beneficial, the drawbacks of the high voltage device by this method are highlighted in the following points. That is, the design method of the breakdown voltage is unknown, and the semiconductor element cannot be designed and manufactured according to the specifications. This point is also apparent from the following description disclosed in the above publication. The potential higher than the lowest potential in the element region 10 can be uniquely determined with good reproducibility by trial. Further, the potential higher than the lowest potential in the element region has an optimum value that maximizes the element breakdown voltage, and is a potential that can be determined with good reproducibility if the semiconductor device is specified.
【０００９】かかる欠点が生ずる原因は、前記の公報で
も述べられているように、素子耐圧に対する基板電位の
作用について、未だ不明であるという点に帰着される。
以上の問題に鑑み、本発明の目的は、基板電位の素子耐
圧に対する作用を明らかにし、高耐圧素子に最適な構造
およびその使用方法を明らかにすることによって、半導
体素子の高耐圧化を図ることにある。The cause of such a defect is attributed to the fact that the effect of the substrate potential on the device breakdown voltage is still unknown, as described in the above publication.
In view of the above problems, an object of the present invention is to increase the breakdown voltage of a semiconductor device by clarifying the action of the substrate potential on the breakdown voltage of the device, and by clarifying the optimum structure for the high breakdown voltage device and the method of using the same. It is in.
【００１０】[0010]
【課題を解決するための手段】上記の課題を解決する手
段としては、第一の半導体基板と第二の半導体基板とを
酸化膜を介して接合した複合半導体基板の第一半導体基
板の主表面から前記酸化膜に達する絶縁膜を埋め込んだ
絶縁膜分離溝と、その分離溝によって他の素子領域から
分離された素子領域と、その素子領域の表面層に形成さ
れた第一導電型拡散領域、第二導電型拡散領域を有する
半導体装置において、前記二つの拡散領域と絶縁物分離
溝との距離ＬG と、第一の半導体基板の厚さｄと、前記
二つの拡散領域間の距離ＬD との間に、ＬG ≧（ＬD −
ｄ）なる関係が成立するものとする。Means for Solving the Problems As a means for solving the above problems, a main surface of a first semiconductor substrate of a composite semiconductor substrate in which a first semiconductor substrate and a second semiconductor substrate are bonded via an oxide film An insulating film isolation groove in which an insulating film reaching the oxide film is buried, an element region separated from other element regions by the isolation groove, and a first conductivity type diffusion region formed in a surface layer of the element region, In a semiconductor device having a second conductivity type diffusion region, the distance L G between the two diffusion regions and the insulating isolation groove, the thickness d of the first semiconductor substrate, and the distance L D between the two diffusion regions. Between L G ≧ (L D −
The relationship d) is established.
【００１１】また、第一の半導体基板と第二の半導体基
板とを酸化膜を介して接合した複合半導体基板の第一半
導体基板の主表面から前記酸化膜に達する絶縁膜を埋め
込んだ絶縁膜分離溝と、その分離溝によって他の素子領
域から分離された厚さが１０μｍを越える素子領域と、
その素子領域の表面層に形成された第一導電型拡散領
域、第二導電型拡散領域を有する半導体装置の、第二半
導体基板の電位を第一半導体基板の素子領域内の最低電
位より高い電位に固定する使用方法として、第二半導体
基板の電位を、素子の最高耐圧のほぼ三分の一の電位に
固定するものとする。In addition, an insulating film separation in which an insulating film reaching the oxide film is buried from the main surface of the first semiconductor substrate of the composite semiconductor substrate in which the first semiconductor substrate and the second semiconductor substrate are bonded together via the oxide film. A groove and an element region having a thickness of more than 10 μm, which is separated from other element regions by the separation groove,
The potential of the second semiconductor substrate of the semiconductor device having the first conductivity type diffusion region and the second conductivity type diffusion region formed in the surface layer of the element region is higher than the lowest potential in the element region of the first semiconductor substrate. As a usage method for fixing the second semiconductor substrate, the potential of the second semiconductor substrate is fixed to a potential of approximately one third of the maximum breakdown voltage of the element.
【００１２】厚さが１０μｍ以下の素子領域と、その素
子領域の表面層に形成された第一導電型拡散領域、第二
導電型拡散領域を有する半導体装置の、使用方法として
は、第二半導体基板の電位を、素子の最高耐圧のほぼ二
分の一の電位に固定するものとする。更に、前記絶縁膜
分離溝内に多結晶シリコンを充填し、その多結晶シリコ
ンに、第一半導体基板の素子領域内の最低電位より高い
電位、例えば、第二半導体基板と同電位をを与えてもよ
い。As a method of using a semiconductor device having an element region having a thickness of 10 μm or less, a first conductivity type diffusion region and a second conductivity type diffusion region formed in a surface layer of the element region, the second semiconductor is used. It is assumed that the potential of the substrate is fixed to a potential that is approximately one half of the maximum breakdown voltage of the device. Further, the insulating film isolation groove is filled with polycrystalline silicon, and the polycrystalline silicon is given a potential higher than the lowest potential in the element region of the first semiconductor substrate, for example, the same potential as the second semiconductor substrate. Good.
【００１３】図７の素子構造における基板電位の影響に
ついて、以下に考察してみる。第一半導体基板６の素子
領域１０内に接合がある場合、酸化膜８からの空乏層の
伸び幅ＸD は次式で表される。The influence of the substrate potential on the device structure of FIG. 7 will be considered below. When there is a junction in the element region 10 of the first semiconductor substrate 6, the extension width X D of the depletion layer from the oxide film 8 is expressed by the following equation.
【００１４】[0014]
【数１】 ＸD ＝［２εSi｛（ＶB −ＶS ）＋２｜φFn｜｝（ｑＮD ）-1］1/2 （２） ここで、ｑは電子の電荷、ＮD は第一半導体基板６の不
純物濃度、εSiはシリコンの誘電率、φFnは素子領域の
フェルミポテンシャル、ＶB は逆バイアス電圧（耐
圧）、ＶS は、第二半導体基板７の基板電位である。 （２）式から明らかなように、ＶS の印加は、酸化膜
８からの空乏層の伸び幅ＸD を減少させる方向に働く。
このことは、ＶS ＝０の時の耐圧（ＶBO）に対してＶS
だけ耐圧を高める方向に作用することを意味する。すな
わち、X D = [2ε Si {(V B −V S ) +2 | φ Fn │} (qN D ) −1 ] 1/2 (2) where q is the electron charge and N D is the The impurity concentration of one semiconductor substrate 6, ε Si is the dielectric constant of silicon, φ Fn is the Fermi potential of the element region, V B is the reverse bias voltage (breakdown voltage), and V S is the substrate potential of the second semiconductor substrate 7. As is clear from the equation (2), the application of V S acts in the direction of decreasing the extension width X D of the depletion layer from the oxide film 8.
This is, V S with respect to the breakdown voltage (V BO) when the V S = 0
It means that it acts only in the direction of increasing the breakdown voltage. That is,
【００１５】[0015]
【数２】 ＶB ＝ＶBo＋ＶS ＝ＥCrit・ｄ−ｑ・ＮD ・ｄ2 ／（２εSi）＋ＶS （３） ここで、ｄは第一半導体基板６の厚さである。 一方、空乏層の電界強度はコーナー部で最大であり、
特に図７のような構造の場合、電界強度は酸化膜８を横
切る電場と関連付けられ、第二半導体基板７に電位ＶS
を与えると、ｎ拡散領域１２の近傍、ｐ拡散領域１１の
近傍では、それぞれ次式で与えられる。[Number 2] V B = V Bo + V S = E Crit · d-q · N D · d 2 / (2ε Si) + V S (3) where, d is the thickness of the first semiconductor substrate 6. On the other hand, the electric field strength of the depletion layer is maximum at the corner,
Particularly in the case of the structure as shown in FIG. 7, the electric field strength is associated with the electric field across the oxide film 8 and the potential V S is applied to the second semiconductor substrate 7.
Then, in the vicinity of the n diffusion region 12 and the p diffusion region 11, they are respectively given by the following equations.
【００１６】 ＥCrit（ｎ）＝α（ＶB * −ＶS ）／ｄox （４） ＥCrit（ｐ）＝α・ＶS ／ｄox （５） ここで、αはある幾何学的な補正因子、ＶB * はの機
構による耐圧、ｄoxは第一の半導体基板６と第二の半導
体基板７の間の酸化膜８の厚さである。（４）、（５）
式から明らかなように、この場合の第二半導体基板の電
位ＶS の効果は耐圧がｎ拡散領域１２の近傍とｐ拡散領
域１１の近傍のどちらで決まるかを決定する作用である
ことを意味する。は、第一半導体基板６の厚さｄで耐
圧が決まる場合であり、は第一半導体基板６の厚さｄ
というよりも酸化膜８の厚さｄoxおよび拡散領域１１ま
たは１２の曲率半径で耐圧が決まる場合である。そこ
で、耐圧設計上決めなければならないことは、耐圧が上
記、のいずれで決められるかを決定することであ
る。E Crit (n) = α (V B * −V S ) / d ox (4) E Crit (p) = α · V S / d ox (5) where α is a geometrical value. The correction factor, V B *, is the breakdown voltage due to the mechanism of, and d ox is the thickness of the oxide film 8 between the first semiconductor substrate 6 and the second semiconductor substrate 7. (4), (5)
As is apparent from the formula, the effect of the potential V S of the second semiconductor substrate in this case means that it is an action that determines whether the breakdown voltage is determined by the vicinity of the n diffusion region 12 or the p diffusion region 11. To do. Is the case where the breakdown voltage is determined by the thickness d of the first semiconductor substrate 6, and is the thickness d of the first semiconductor substrate 6.
Rather, the breakdown voltage is determined by the thickness d ox of the oxide film 8 and the radius of curvature of the diffusion region 11 or 12. Therefore, what must be determined in the breakdown voltage design is to decide which of the above breakdown voltages is used.
【００１７】（３）、（４）式から耐圧がで決まる場
合にはＶB ≦ＶB * であるから、When the breakdown voltage is determined by the equations (3) and (4), V B ≤V B *
【００１８】[0018]
【数３】 ＥCrit（ｎ）ｄox／α−ＥCrit・ｄ＋ｑＮD ｄ2 ／（２εSi）≧０ （６） （６）式を満足する第一半導体基板の厚さｄは一般に、
ｄ≦１０μｍである。その時の最大耐圧は、（３）式で
基板濃度ＮD が低い場合には、一般に高耐圧素子ではＮ
D は低濃度であるから、[ Equation 3] E Crit (n) d ox / α-E Crit · d + qN D d 2 / (2ε Si ) ≧ 0 (6) The thickness d of the first semiconductor substrate that satisfies the formula (6) is generally
d ≦ 10 μm. The maximum breakdown voltage at that time is generally N in the case of a high breakdown voltage element when the substrate concentration N D is low in the formula (3).
Since D is a low concentration,
【００１９】[0019]
【数４】 ＶB ＝ＶBo＋ＶS ＝ＥCrit・ｄ−ｑ・ＮD ・ｄ2 ／（２εSi）＋ＶS ≒ＥCrit・ｄ＋ＶS ＶB ＝ＶB * で最大耐圧を与えるため、（４）式に代入
して ＥCrit（ｎ）ｄox／α＝ＥCrit・ｄ α／ｄox＝ＥCrit（ｎ）／（ＥCrit・ｄ） 特別のことがない限り ＥCrit（ｎ）＝ＥCrit（ｐ） であるから、（５）式より、 ＶS ＝ＥCrit・ｄ よって、（３）式より、 ＶB ＝２ＶS （７） 次に耐圧ができまる場合には、 ＶB ≧ＶB * であるから、Since V B = V Bo + V S = E Crit · d−q · N D · d 2 / (2ε Si ) + V S ≈E Crit · d + V S V B = V B * Substituting into equation (4), E Crit (n) d ox / α = E Crit · d α / d ox = E Crit (n) / (E Crit · d) E Crit (n) unless otherwise specified = because it is E Crit (p), from equation (5), V S = E Crit · d Therefore, (3) from the equation, if circle can V B = 2V S (7) then breakdown voltage, V Since B ≧ V B * ,
【００２０】[0020]
【数５】 ＥCrit（ｎ）ｄox／α−ＥCrit・ｄ＋ｑＮD ｄ2 ／（２εSi）≦０ （８） （８）式を満足するｄは一般に、ｄ≧１０μｍ であ
る。（４）、（５）式から耐圧がで決まる場合には、
ＥCrit（ｎ）＝ＥCrit（ｐ）で最大耐圧がきまり、 ＶB * ＝２ＶS 故に、 ＶS ＝１／２ＶB * その時の最大耐圧ＶB ｍａｘは、次のようになる。Equation 5] E Crit (n) d ox / α-E Crit · d + qN D d 2 / (2ε Si) d which satisfies ≦ 0 (8) (8) Equation is generally a d ≧ 10 [mu] m. When the breakdown voltage is determined by the equations (4) and (5),
Since the maximum withstand voltage is determined by E Crit (n) = E Crit (p) and V B * = 2V S , V S = 1 / 2V B * The maximum withstand voltage V B max at that time is as follows.
【００２１】[0021]
【数６】 ＶB ｍａｘ＝ＥCrit・ｄ−ｑ・ＮD ・ｄ2 ／（２εSi）＋ＶS ＝ＥCrit・ｄ−ｑ・ＮD ・ｄ2 ／（２εSi）＋１／２ＶB * ≒ＥCrit・ｄ＋１／２ＶB * 耐圧がで決まる場合、第一半導体基板６中は完全に空
乏化し、酸化膜８中に密集した電位で決まるので、 ＶB * ＝ＥCrit・ｄ 故に、 ＶB ｍａｘ＝３ＶS （９） 以上、基板電位の作用について検討した。我々は、ここ
で素子の最高耐圧が決まるのがの場合を二倍効果、
の場合を三倍効果と呼ぶことにする。[ Equation 6] V B max = E Crit · d−q · N D · d 2 / (2ε Si ) + V S = E Crit · d−q · N D · d 2 / (2ε Si ) + ½V B * ≈ E Crit · d + 1/2 V B * When the breakdown voltage is determined by, the first semiconductor substrate 6 is completely depleted and is determined by the potential concentrated in the oxide film 8. Therefore, V B * = E Crit · d B max = 3V S (9) Above, the action of the substrate potential was examined. We double the effect that the maximum breakdown voltage of the device is determined here,
The case of is called triple effect.
【００２２】前術の手段を講じ、二つの拡散領域と絶縁
膜分離溝との距離ＬG と、第一の半導体基板の厚さｄ
と、前記二つの拡散領域間の距離ＬD との間に、ＬG ≧
（ＬD−ｄ）とすることによって、誘電体分離型半導体
装置の高耐圧化が図れる。また、厚さが１０μｍを越え
る素子領域を有する半導体装置で、第二半導体基板の電
位を、素子の最高耐圧のほぼ三分の一の電位に固定する
ものとし、 厚さが１０μｍ以下の素子領域を有する半
導体装置で、第二半導体基板の電位を、素子の最高耐圧
のほぼ二分の一の電位に固定することによって、半導体
装置の耐圧が、上記する機構により、最大になる。Taking the means of the previous technique, the distance L G between the two diffusion regions and the insulating film isolation groove and the thickness d of the first semiconductor substrate are set.
And a distance L D between the two diffusion regions, L G ≧
By the (L D -d), attained a high withstand voltage of the dielectric isolation semiconductor device. Further, in a semiconductor device having an element region with a thickness exceeding 10 μm, the potential of the second semiconductor substrate is fixed to a potential of approximately one third of the maximum breakdown voltage of the element, and the element region with a thickness of 10 μm or less is used. In the semiconductor device having the above, by fixing the potential of the second semiconductor substrate to a potential that is approximately one half of the maximum breakdown voltage of the element, the breakdown voltage of the semiconductor device is maximized by the mechanism described above.
【００２３】更に、絶縁膜分離溝内の絶縁膜に多結晶シ
リコンを充填し、その多結晶シリコンに、第一半導体基
板の素子領域内の最低電位より高い電位、例えば、第二
半導体基板と同電位をを与えることによって、誘電体分
離型半導体装置の高耐圧化が図れる。Further, the insulating film in the insulating film isolation groove is filled with polycrystalline silicon, and the polycrystalline silicon has a potential higher than the lowest potential in the element region of the first semiconductor substrate, for example, the same as the second semiconductor substrate. By applying a potential, the dielectric isolation type semiconductor device can have a high breakdown voltage.
【００２４】[0024]
【発明の実施の形態】図１は、本発明の実施例の完全誘
電体分離型半導体装置の実験素子の断面とともに電圧印
加方法を示した図である。第一の半導体基板６と第二の
半導体基板７とを酸化膜８を介して接合した複合半導体
基板に、第一半導体基板６の主表面から酸化膜８に達す
る絶縁物を埋め込んだ分離溝９によって他の素子領域か
ら分離された素子領域１０内にｐ拡散領域１１とｎ拡散
領域１２が形成されている半導体素子において、第二半
導体基板７の電位ＶS を第一半導体基板６の素子領域１
０内の最低電位（図１ではｐ拡散領域１１に接続された
アース電位）より高い電位に固定することにより、素子
耐圧ＶB を向上させることができる。実験素子の変数と
して、第一半導体基板６の厚さｄは１０μｍまたは３０
μｍとした。半導体基板６の不純物濃度は１×１０14ｃ
ｍ-3（ｎ型）、ｐ拡散領域１１およびｎ拡散領域１２の
ドーズ量はそれぞれ１×１０15ｃｍ-2、３．１×１０15
ｃｍ-2である。また、拡散領域の曲率半径の影響を調べ
るために、ｐ拡散領域１１の拡散深さｘj を１．５μｍ
と３．５μｍの二種類を選択した。ｐ拡散領域１１とｎ
拡散領域１２の間の距離（ドリフト長）ＬD は７０μｍ
一定とした。FIG. 1 is a diagram showing a cross section of an experimental element of a complete dielectric isolation type semiconductor device of an embodiment of the present invention and a voltage applying method. A separation groove 9 in which an insulating material reaching the oxide film 8 from the main surface of the first semiconductor substrate 6 is embedded in a composite semiconductor substrate in which the first semiconductor substrate 6 and the second semiconductor substrate 7 are bonded to each other through the oxide film 8. In the semiconductor element in which the p diffusion region 11 and the n diffusion region 12 are formed in the element region 10 separated from other element regions by the element region of the first semiconductor substrate 6, the potential V S of the second semiconductor substrate 7 is 1
By fixing the potential higher than the lowest potential within 0 (the ground potential connected to the p diffusion region 11 in FIG. 1), the element breakdown voltage V B can be improved. As a variable of the experimental element, the thickness d of the first semiconductor substrate 6 is 10 μm or 30
μm. The impurity concentration of the semiconductor substrate 6 is 1 × 10 14 c
The dose amounts of m −3 (n type), p diffusion region 11 and n diffusion region 12 are 1 × 10 15 cm −2 and 3.1 × 10 15 respectively.
cm -2 . Further, in order to investigate the influence of the radius of curvature of the diffusion region, the diffusion depth x j of the p diffusion region 11 is set to 1.5 μm.
And 3.5 μm were selected. p diffusion region 11 and n
The distance (drift length) L D between the diffusion regions 12 is 70 μm.
It was fixed.
【００２５】図３は、その実験結果を示す。横軸は第二
半導体基板の電位ＶS 、たて軸は半導体素子の耐圧ＶB
である。基板の電位ＶS が増す程素子耐圧ＶB も増加し
ているが、或るピーク値を経て再び減少している。そし
て、素子耐圧ＶB のピーク値を与える基板の電位Ｖ
S は、第一半導体基板６の厚さが１０μｍの△の例で
は、素子耐圧ＶB のピーク値の二分の一、第一半導体基
板６の厚さが３０μｍの□、○の例では、素子耐圧ＶB
のピーク値の三分の一の電位の点になっており、先の理
論的な予測と一致している。すなわち、従来のように実
験によって、基板の電圧を決め、素子の耐圧設計をする
のではなく、耐圧設計をしながら素子のディメンション
の設計ができることになる。FIG. 3 shows the experimental results. The horizontal axis represents the potential V S of the second semiconductor substrate, and the vertical axis represents the breakdown voltage V B of the semiconductor element.
Is. The device breakdown voltage V B increases as the substrate potential V S increases, but decreases again after a certain peak value. Then, the substrate potential V that gives the peak value of the element withstand voltage V B
S is half of the peak value of the element breakdown voltage V B in the case of Δ where the thickness of the first semiconductor substrate 6 is 10 μm, and is the element in the case of □ and ◯ where the thickness of the first semiconductor substrate 6 is 30 μm. Withstand voltage V B
It is at the point of one-third of the peak value of, which is in agreement with the previous theoretical prediction. That is, it is possible to design the dimensions of the device while designing the breakdown voltage, instead of designing the breakdown voltage of the device by deciding the voltage of the substrate by experiments as in the conventional case.
【００２６】図４は、図１の半導体装置において、ｎ拡
散領域１２と分離溝９との間の距離ＬG の耐圧に及ぼす
影響について実験した結果である。横軸は距離ＬG 、た
て軸は耐圧である。距離ＬG とともに耐圧は向上し、あ
る値、この場合４０μｍ以上でほぼ飽和している。この
ような実験を重ねた結果、図１の構造で高耐圧を実現す
るための条件として、次式が得られた。FIG. 4 is a result of an experiment conducted on the influence of the distance L G between the n diffusion region 12 and the isolation trench 9 on the breakdown voltage in the semiconductor device of FIG. The horizontal axis represents the distance L G , and the vertical axis represents the pressure resistance. The breakdown voltage increases with the distance L G , and is almost saturated at a certain value, 40 μm or more in this case. As a result of repeating such an experiment, the following equation was obtained as a condition for realizing a high breakdown voltage in the structure of FIG.
【００２７】 ＬG ≧ＬD −ｄ （１０） 図２は、本発明の別の実施例の半導体装置の断面図とと
もに電圧印加方法を示した図である。図１の実施例との
違いは、分離溝９内が絶縁物だけでなく、多結晶シリコ
ン１３が絶縁物で挟まれた構造になっており、多結晶シ
リコン１３に電位ＶG が印加できる点である。電位ＶG
は第二の基板７の電位ＶS と同じにもまた変えることも
できる。図５（ｂ）に、図２の半導体装置において、多
結晶シリコン１３に、第二基板７の電位ＶS と同じ電位
を与えた時の電位分布の様子を示す。図５（ａ）は、多
結晶シリコン１３に電位を与えない時の電位分布の様子
を示す。各曲線は５０Ｖごとの等電位線である。多結晶
シリコン１３に電位ＶG を与えた時の作用は、第二の基
板７に電位ＶS を与えた作用と同等で、電位分布が緩や
かになり、特に（１０）式の条件が満たせない状況での
高耐圧の実現に有効であることがわかる。L G ≧ L D −d (10) FIG. 2 is a diagram showing a voltage application method together with a sectional view of a semiconductor device according to another embodiment of the present invention. The difference from the embodiment of FIG. 1 is that not only an insulator but also a polycrystalline silicon 13 is sandwiched between the insulators in the separation groove 9, and a potential V G can be applied to the polycrystalline silicon 13. Is. Potential V G
Can also be changed to be the same as the potential V S of the second substrate 7. FIG. 5B shows a state of the potential distribution when the same potential as the potential V S of the second substrate 7 is applied to the polycrystalline silicon 13 in the semiconductor device of FIG. FIG. 5A shows a state of potential distribution when no potential is applied to the polycrystalline silicon 13. Each curve is an equipotential line for every 50V. The action when the potential V G is applied to the polycrystalline silicon 13 is equivalent to the action when the potential V S is applied to the second substrate 7, the potential distribution becomes gentle, and the condition of the formula (10) cannot be particularly satisfied. It can be seen that it is effective in realizing a high breakdown voltage in each situation.
【００２８】[0028]
【発明の効果】本発明によれば、完全誘電体分離構造の
半導体装置において、基板電位の耐圧におよぼす作用が
明らかになったため、予め、素子の耐圧設計をすること
が可能になった。また、分離溝内に多結晶シリコンを挟
み、電位を与えることにより、高耐圧が得られる半導体
装置の使用方法を提供できた。According to the present invention, in the semiconductor device having the complete dielectric isolation structure, the action of the substrate potential on the breakdown voltage has been clarified, so that the breakdown voltage of the element can be designed in advance. Further, it was possible to provide a method of using a semiconductor device in which a high breakdown voltage is obtained by sandwiching polycrystalline silicon in the isolation trench and applying a potential.
【図１】本発明の実施例の半導体装置の断面および電圧
印加方法の説明図FIG. 1 is an explanatory view of a cross section of a semiconductor device and a voltage applying method according to an embodiment of the present invention.
【図２】本発明の別の実施例の半導体装置の断面および
電圧印加方法の説明図FIG. 2 is an explanatory view of a cross section of a semiconductor device according to another embodiment of the present invention and a voltage application method.
【図３】図１の実施例における素子耐圧の基板電位依存
性を示す図FIG. 3 is a diagram showing the substrate potential dependency of the device breakdown voltage in the embodiment of FIG.
【図４】図１の実施例における素子耐圧の拡散領域−分
離溝間距離依存性を示す図FIG. 4 is a diagram showing the dependence of the device breakdown voltage on the distance between the diffusion region and the separation groove in the embodiment of FIG.
【図５】図２の実施例における分離溝の電位の影響を示
す電位分布図5 is a potential distribution diagram showing the influence of the potential of the separation groove in the embodiment of FIG.
【図６】従来の半導体装置における接合分離を示す断面
および電圧印加方法の説明図FIG. 6 is a cross-sectional view showing junction separation in a conventional semiconductor device and an explanatory diagram of a voltage application method.
【図７】従来の半導体装置における誘電体分離を示す断
面および電圧印加方法の説明図FIG. 7 is a cross-sectional view showing dielectric isolation in a conventional semiconductor device and an explanatory diagram of a voltage application method.
１ ｐ型基板 ２ 素子領域 ３ 分離領域 ４ ｐ拡散領域 ５ ｎ拡散領域 ６ 第一半導体基板 ７ 第二半導体基板 ８ 酸化膜 ９ 絶縁物分離溝 １０ 素子領域 １１ ｐ拡散領域 １２ ｎ拡散領域 １３ 多結晶シリコン 1 p-type substrate 2 element region 3 isolation region 4 p diffusion region 5 n diffusion region 6 first semiconductor substrate 7 second semiconductor substrate 8 oxide film 9 insulator isolation groove 10 device region 11 p diffusion region 12 n diffusion region 13 polycrystal silicon
Claims (5)
酸化膜を介して接合した複合半導体基板の第一半導体基
板の主表面から前記酸化膜に達する絶縁膜を埋め込んだ
絶縁膜分離溝と、その分離溝によって他の素子領域から
分離された素子領域と、その素子領域の表面層に形成さ
れた第一導電型拡散領域、第二導電型拡散領域を有する
ものにおいて、前記二つの拡散領域と絶縁膜分離溝との
距離Ｌ G と、第一の半導体基板の厚さｄと、前記二つの
拡散領域間の距離ＬD との間に、 ＬG ≧（ＬD −ｄ）
なる関係が成立することを特徴とする高耐圧横型半導
体装置。1. A first semiconductor substrate and a second semiconductor substrate are provided.
First semiconductor substrate of composite semiconductor substrate bonded through an oxide film
An insulating film that reaches the oxide film from the main surface of the plate is embedded
Insulating film isolation groove and other element area
Formed on the separated element area and the surface layer of the element area.
Having a first conductivity type diffusion region and a second conductivity type diffusion region
Of the two diffusion regions and the insulating film isolation groove
Distance L GAnd the thickness d of the first semiconductor substrate and the two
Distance L between diffusion areasDBetween and LG≧ (LD-D)
High-breakdown-voltage lateral semiconductor characterized in that
Body device.
酸化膜を介して接合した複合半導体基板の第一半導体基
板の主表面から前記酸化膜に達する絶縁膜を埋め込んだ
絶縁膜分離溝と、その分離溝によって他の素子領域から
分離された厚さが１０μｍを越える素子領域と、その素
子領域の表面層に形成された第一導電型拡散領域、第二
導電型拡散領域を有する半導体装置の、第二半導体基板
の電位を第一半導体基板の素子領域内の最低電位より高
い電位に固定する使用方法において、第二半導体基板の
電位を、素子の最高耐圧のほぼ三分の一の電位に固定す
ることを特徴とする高耐圧横型半導体装置の使用方法。2. An insulating film separation in which an insulating film reaching the oxide film is embedded from the main surface of the first semiconductor substrate of a composite semiconductor substrate in which a first semiconductor substrate and a second semiconductor substrate are bonded via an oxide film. A groove, an element region having a thickness of more than 10 μm separated from other element regions by the isolation groove, and a first-conductivity-type diffusion region and a second-conductivity-type diffusion region formed in the surface layer of the element region. In a method of using a semiconductor device in which the potential of the second semiconductor substrate is fixed to a potential higher than the lowest potential in the element region of the first semiconductor substrate, the potential of the second semiconductor substrate is set to approximately one third of the maximum breakdown voltage of the element. A method of using a high withstand voltage lateral semiconductor device, which is characterized in that it is fixed at a potential of 1.
酸化膜を介して接合した複合半導体基板の第一半導体基
板の主表面から前記酸化膜に達する絶縁膜を埋め込んだ
絶縁膜分離溝と、その分離溝によって他の素子領域から
分離された厚さが１０μｍ以下の素子領域と、その素子
領域の表面層に形成された第一導電型拡散領域、第二導
電型拡散領域を有する半導体装置の、第二半導体基板の
電位を第一半導体基板の素子領域内の最低電位より高い
電位に固定する使用方法において、第二半導体基板の電
位を、素子の最高耐圧のほぼ二分の一の電位に固定する
ことを特徴とする高耐圧横型半導体装置の使用方法。3. An insulating film separation in which an insulating film reaching the oxide film is embedded from the main surface of the first semiconductor substrate of a composite semiconductor substrate in which a first semiconductor substrate and a second semiconductor substrate are bonded together via an oxide film. A groove, an element region having a thickness of 10 μm or less, which is separated from other element regions by the separation groove, and a first-conductivity-type diffusion region and a second-conductivity-type diffusion region formed in a surface layer of the element region. In a method of using the semiconductor device, wherein the potential of the second semiconductor substrate is fixed to a potential higher than the lowest potential in the element region of the first semiconductor substrate, the potential of the second semiconductor substrate is set to approximately one half of the maximum breakdown voltage of the element. A method of using a high withstand voltage lateral semiconductor device, which is characterized in that it is fixed at a potential.
コンを充填し、その多結晶シリコンに、第一半導体基板
の素子領域内の最低電位より高い電位を与えることを特
徴とする請求項２または３に記載の高耐圧横型半導体装
置の使用方法。4. The insulating film in the insulating film isolation groove is filled with polycrystalline silicon, and the polycrystalline silicon is given a potential higher than the lowest potential in the element region of the first semiconductor substrate. Item 4. A method of using the high breakdown voltage lateral semiconductor device according to Item 2 or 3.
電位を与えることを特徴とする請求項４に記載の高耐圧
横型半導体装置の使用方法。5. The method of using a high breakdown voltage lateral semiconductor device according to claim 4, wherein the same potential as that of the second semiconductor substrate is applied to the polycrystalline silicon.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24900995A JPH08153781A (en) | 1994-09-27 | 1995-09-27 | Horizontal semiconductor device having high breakdown voltage and its using method |
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6-230882 | 1994-09-27 | ||
| JP23088294 | 1994-09-27 | ||
| JP24900995A JPH08153781A (en) | 1994-09-27 | 1995-09-27 | Horizontal semiconductor device having high breakdown voltage and its using method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH08153781A true JPH08153781A (en) | 1996-06-11 |
Family
ID=26529590
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP24900995A Withdrawn JPH08153781A (en) | 1994-09-27 | 1995-09-27 | Horizontal semiconductor device having high breakdown voltage and its using method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH08153781A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6492683B2 (en) | 2000-09-28 | 2002-12-10 | Nec Corporation | Semiconductor device with SOI structure and method of manufacturing the same |
-
1995
- 1995-09-27 JP JP24900995A patent/JPH08153781A/en not_active Withdrawn
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6492683B2 (en) | 2000-09-28 | 2002-12-10 | Nec Corporation | Semiconductor device with SOI structure and method of manufacturing the same |
| US6541314B2 (en) | 2000-09-28 | 2003-04-01 | Nec Corporation | Semiconductor device with SOI structure and method of manufacturing the same |
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