JPH08130263A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH08130263A JPH08130263A JP6288889A JP28888994A JPH08130263A JP H08130263 A JPH08130263 A JP H08130263A JP 6288889 A JP6288889 A JP 6288889A JP 28888994 A JP28888994 A JP 28888994A JP H08130263 A JPH08130263 A JP H08130263A
- Authority
- JP
- Japan
- Prior art keywords
- film
- diffusion layer
- semiconductor device
- diffusion layers
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本願の発明は、半導体基板と同電
位にされるべき拡散層が半導体基板とは逆導電型である
半導体装置に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device in which a diffusion layer which should be at the same potential as the semiconductor substrate has a conductivity type opposite to that of the semiconductor substrate.
【０００２】[0002]
【従来の技術】図４、５は、ＥＴＯＸ型と称されている
フラッシュＥＥＰＲＯＭの一従来例を示している。この
一従来例では、Ｐ型のＳｉ基板１１の表面にＳｉＯ2 膜
１２等の素子分離用の絶縁膜が島状に且つ行列状に配置
されており、ＳｉＯ2 膜１２以外の素子活性領域の表面
にゲート絶縁膜としてのＳｉＯ2 膜１３等が形成されて
いる。2. Description of the Related Art FIGS. 4 and 5 show a conventional example of a flash EEPROM called an ETOX type. In this conventional example, an insulating film for element isolation such as a SiO 2 film 12 is arranged in an island shape and in a matrix on the surface of a P-type Si substrate 11, and the element active regions other than the SiO 2 film 12 are formed. A SiO 2 film 13 or the like as a gate insulating film is formed on the surface.
【０００３】ＳｉＯ2 膜１３上には、各メモリセルに対
応する浮遊ゲートが多結晶Ｓｉ膜１４等で形成されてお
り、この多結晶Ｓｉ膜１４上には、容量結合用の絶縁膜
がＯＮＯ膜１５等で形成されている。また、ＯＮＯ膜１
５上には、行方向に延在して各メモリセルに対する制御
ゲートになるワード線が多結晶Ｓｉ膜１６等で形成され
ている。A floating gate corresponding to each memory cell is formed on the SiO 2 film 13 by a polycrystalline Si film 14 or the like, and an insulating film for capacitive coupling ONO is formed on the polycrystalline Si film 14. It is formed of the film 15 and the like. Also, the ONO film 1
5, a word line extending in the row direction and serving as a control gate for each memory cell is formed of a polycrystalline Si film 16 or the like.
【０００４】多結晶Ｓｉ膜１６の一方の素子活性領域に
は、複数のメモリセルに対する共通ソース線としてのＮ
+ 型の拡散層２１が形成されており、多結晶Ｓｉ膜１６
の他方の素子活性領域には、列方向に並んでいる２個の
メモリセルに共通のドレインとしてのＮ+ 型の拡散層２
２が形成されている。また、多結晶Ｓｉ膜１６や拡散層
２１、２２等を覆う層間絶縁膜（図示せず）には、拡散
層２１、２２に達するコンタクト孔２３、２４が形成さ
れている。In one element active region of the polycrystalline Si film 16, N serving as a common source line for a plurality of memory cells is formed.
The + type diffusion layer 21 is formed, and the polycrystalline Si film 16 is formed.
In the other element active region of the N + type diffusion layer 2 as a drain common to two memory cells arranged in the column direction.
2 is formed. Further, contact holes 23, 24 reaching the diffusion layers 21, 22 are formed in an interlayer insulating film (not shown) covering the polycrystalline Si film 16, the diffusion layers 21, 22 and the like.
【０００５】そして、コンタクト孔２３を介して拡散層
２１に接続されると共に列方向に延在するＡｌ膜２５等
で、ソース電位を与えるための配線が形成されており、
コンタクト孔２４を介して拡散層２２に接続されると共
に列方向に延在するＡｌ膜２６等で、ビット線が形成さ
れている。なお、ソース電位としては、Ｓｉ基板１１と
同じ接地電位が与えられる。A wiring for applying a source potential is formed by the Al film 25 and the like connected to the diffusion layer 21 through the contact hole 23 and extending in the column direction.
A bit line is formed by the Al film 26 and the like which is connected to the diffusion layer 22 through the contact hole 24 and extends in the column direction. The same ground potential as that of the Si substrate 11 is applied as the source potential.
【０００６】[0006]
【発明が解決しようとする課題】ところが、上述の一従
来例では、図５からも明らかな様に、共通ソース線とし
ての拡散層２１に対するコンタクト孔２３やこのコンタ
クト孔２３を介して拡散層２１に接続されるＡｌ膜２５
を設ける必要があるので、これらのコンタクト孔２３や
Ａｌ膜２５のための領域が必要である。However, in the above-mentioned conventional example, as is apparent from FIG. 5, the contact hole 23 for the diffusion layer 21 as the common source line and the diffusion layer 21 via the contact hole 23. Film 25 connected to
Since it is necessary to provide these, areas for these contact holes 23 and Al film 25 are required.
【０００７】しかも、コンタクト孔２３からの距離に依
存して拡散層２１の抵抗が変わるので、拡散層２１の抵
抗が変わることによる特性の変動を許容範囲内に抑制す
るために、コンタクト孔２３は８〜１６個のメモリセル
毎に形成されているのが一般的である。このため、コン
タクト孔２３やＡｌ膜２５のために更に大きな領域が必
要であり、上述の一従来例では、微細化、高密度化が困
難であった。Moreover, since the resistance of the diffusion layer 21 changes depending on the distance from the contact hole 23, in order to suppress the fluctuation of the characteristics due to the change of the resistance of the diffusion layer 21 within the allowable range, the contact hole 23 is formed. Generally, it is formed every 8 to 16 memory cells. Therefore, a larger area is required for the contact hole 23 and the Al film 25, and it has been difficult to miniaturize and increase the density in the above-mentioned conventional example.
【０００８】[0008]
【課題を解決するための手段】請求項１の半導体装置
は、半導体基板１１と同電位にされるべき第１の拡散層
２１が前記半導体基板１１とは逆導電型である半導体装
置において、前記半導体基板１１と同一導電型の第２の
拡散層３２が前記半導体基板１１に設けられており、金
属を含有する導電膜３１が前記第１及び第２の拡散層２
１、３２の表面に接した状態で広がっていることを特徴
としている。According to a first aspect of the present invention, there is provided a semiconductor device, wherein the first diffusion layer 21 to be set to the same potential as the semiconductor substrate 11 has a conductivity type opposite to that of the semiconductor substrate 11. A second diffusion layer 32 having the same conductivity type as that of the semiconductor substrate 11 is provided on the semiconductor substrate 11, and a conductive film 31 containing a metal is provided on the first and second diffusion layers 2.
It is characterized in that it spreads in contact with the surfaces of Nos. 1 and 32.
【０００９】請求項２の半導体装置は、請求項１の半導
体装置において、前記半導体基板１１がシリコン基板で
あり、前記導電膜３１が前記第１及び第２の拡散層２
１、３２の表面に自己整合的に形成されているシリサイ
ド膜であることを特徴としている。A semiconductor device according to a second aspect is the semiconductor device according to the first aspect, wherein the semiconductor substrate 11 is a silicon substrate, and the conductive film 31 is the first and second diffusion layers 2.
It is characterized in that it is a silicide film formed in a self-aligned manner on the surface of Nos. 1 and 32.
【００１０】請求項３の半導体装置は、請求項１または
２の半導体装置において、複数のトランジスタが連続的
に配置されており、前記第１及び第２の拡散層２１、３
２が前記複数のトランジスタの共通ソース線になってい
ることを特徴としている。A semiconductor device according to a third aspect is the semiconductor device according to the first or second aspect, in which a plurality of transistors are continuously arranged, and the first and second diffusion layers 21 and 3 are provided.
2 is a common source line of the plurality of transistors.
【００１１】請求項４の半導体装置は、請求項３の半導
体装置において、前記第２の拡散層３２が前記共通ソー
ス線の延在方向における前記複数のトランジスタ同士の
境界部に配置されていることを特徴としている。A semiconductor device according to a fourth aspect is the semiconductor device according to the third aspect, wherein the second diffusion layer 32 is arranged at a boundary portion between the plurality of transistors in the extending direction of the common source line. Is characterized by.
【００１２】請求項５の半導体装置は、請求項３の半導
体装置において、前記第２の拡散層３２が前記共通ソー
ス線の幅方向の中央部においてこの共通ソース線の延在
方向へ連続していることを特徴としている。A semiconductor device according to a fifth aspect is the semiconductor device according to the third aspect, wherein the second diffusion layer 32 is continuously formed in the central portion of the common source line in the width direction in the extending direction of the common source line. It is characterized by being.
【００１３】[0013]
【作用】請求項１の半導体装置では、第２の拡散層３２
が半導体基板１１と同一導電型であるので、第２の拡散
層３２は半導体基板１１と同電位になり、第１及び第２
の拡散層２１、３２は金属を含有する導電膜３１とオー
ミック接続されているので、金属を含有する導電膜３１
を介して第１の拡散層２１は第２の拡散層３２と同電位
になり、結局、半導体基板１１とは逆導電型の第１の拡
散層２１と半導体基板１１とが同電位になる。In the semiconductor device according to claim 1, the second diffusion layer 32 is provided.
Has the same conductivity type as the semiconductor substrate 11, the second diffusion layer 32 has the same potential as the semiconductor substrate 11, and the first and second diffusion layers 32 have the same potential.
Since the diffusion layers 21 and 32 are ohmic-connected to the conductive film 31 containing a metal, the conductive film 31 containing a metal
Thus, the first diffusion layer 21 has the same potential as the second diffusion layer 32, and eventually the first diffusion layer 21 and the semiconductor substrate 11 having the conductivity type opposite to that of the semiconductor substrate 11 have the same potential.
【００１４】そして、金属を含有する導電膜３１が第１
及び第２の拡散層２１、３２の表面に接した状態で広が
っているので、第１及び第２の拡散層２１、３２に対す
るコンタクト孔やこのコンタクト孔を介して第１及び第
２の拡散層２１、３２に接続される配線を設ける必要が
なく、これらのコンタクト孔や配線のための領域が不要
である。Then, the conductive film 31 containing metal is firstly formed.
And the second diffusion layers 21 and 32 are spread in contact with the surfaces of the first and second diffusion layers 21 and 32, and therefore the first and second diffusion layers are provided through the contact holes for the first and second diffusion layers 21 and 32 and the contact holes. It is not necessary to provide wirings connected to 21 and 32, and these contact holes and areas for wirings are unnecessary.
【００１５】請求項２の半導体装置では、導電膜３１が
第１及び第２の拡散層２１、３２の表面に自己整合的に
形成されているので、第１及び第２の拡散層２１、３２
の表面に接した状態で広がる導電膜３１を形成するため
の領域に余裕領域を設ける必要がない。According to another aspect of the semiconductor device of the present invention, the conductive film 31 is formed on the surfaces of the first and second diffusion layers 21 and 32 in a self-aligned manner, so that the first and second diffusion layers 21 and 32 are formed.
It is not necessary to provide a margin area in the area for forming the conductive film 31 that spreads in contact with the surface of the.
【００１６】請求項３〜５の半導体装置では、任意の位
置で共通ソース線を半導体基板１１と同電位にすること
ができるので、共通ソース線の抵抗を実質的になくすこ
とができる。In the semiconductor device according to claims 3 to 5, the common source line can be made to have the same potential as the semiconductor substrate 11 at an arbitrary position, so that the resistance of the common source line can be substantially eliminated.
【００１７】[0017]
【実施例】以下、ＥＴＯＸ型のフラッシュＥＥＰＲＯＭ
に適用した本願の発明の第１及び第２実施例を、図１〜
３を参照しながら説明する。なお、図１〜３に示す第１
及び第２実施例のうちで、図４、５に示した一従来例と
対応する構成部分には、図４、５と同一の符号を付して
ある。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS ETOX type flash EEPROM
1 and 2 of the present invention applied to FIG.
This will be described with reference to FIG. The first shown in FIGS.
Also, in the second embodiment, the components corresponding to those of the conventional example shown in FIGS.
【００１８】図１、２が、第１実施例を示している。こ
の第１実施例では、Ｐ型のＳｉ基板１１の表面にＳｉＯ
2 膜１２等の素子分離用の絶縁膜が島状に且つ行列状に
配置されており、ＳｉＯ2 膜１２以外の素子活性領域の
表面にゲート絶縁膜としてのＳｉＯ2 膜１３等が形成さ
れている。1 and 2 show a first embodiment. In the first embodiment, SiO 2 is formed on the surface of the P type Si substrate 11.
Insulation films such as 2 films 12 for element isolation are arranged in an island shape and in a matrix, and an SiO 2 film 13 as a gate insulating film is formed on the surface of the element active region other than the SiO 2 film 12. There is.
【００１９】ＳｉＯ2 膜１３上には、各メモリセルに対
応する浮遊ゲートが多結晶Ｓｉ膜１４等で形成されてお
り、この多結晶Ｓｉ膜１４上には、容量結合用の絶縁膜
がＯＮＯ膜１５等で形成されている。また、ＯＮＯ膜１
５上には、行方向に延在して各メモリセルに対する制御
ゲートになるワード線が、多結晶Ｓｉ膜１６及び高融点
金属とＳｉとのシリサイド膜３１で形成されている。A floating gate corresponding to each memory cell is formed on the SiO 2 film 13 by a polycrystalline Si film 14 or the like, and an insulating film for capacitive coupling ONO is formed on the polycrystalline Si film 14. It is formed of the film 15 and the like. Also, the ONO film 1
A word line extending in the row direction and serving as a control gate for each memory cell is formed on the polycrystalline silicon film 16 and a silicide film 31 of a refractory metal and Si.
【００２０】多結晶Ｓｉ膜１６及びシリサイド膜３１の
一方の素子活性領域には、複数のメモリセルに対する共
通ソース線が、平面的に見て多結晶Ｓｉ膜１６及びシリ
サイド膜３１と接しているＮ+ 型の拡散層２１と、行方
向におけるメモリセル同士の境界部に配置されているＰ
+ 型の拡散層３２とで形成されている。In one element active region of the polycrystalline Si film 16 and the silicide film 31, a common source line for a plurality of memory cells is in contact with the polycrystalline Si film 16 and the silicide film 31 in plan view. The P- type diffusion layer 21 and the P arranged at the boundary between the memory cells in the row direction.
And a + type diffusion layer 32.
【００２１】つまり、共通ソース線は、行方向に交互に
配置されているＮ+ 型の拡散層２１とＰ+ 型の拡散層３
２とで形成されている。なお、Ｐ+ 型の拡散層３２は、
Ｓｉ基板１１上の他の領域（図示せず）におけるＰチャ
ネルトランジスタのソース、ドレインとしてのＰ+ 型の
拡散層と同時に形成されたものである。従って、Ｐ+型
の拡散層３２が設けられていても、製造工程は増加して
いない。That is, the common source line has N + type diffusion layers 21 and P + type diffusion layers 3 alternately arranged in the row direction.
It is formed with 2. The P + type diffusion layer 32 is
It is formed at the same time as the P + -type diffusion layer as the source and drain of the P-channel transistor in another region (not shown) on the Si substrate 11. Therefore, even if the P + type diffusion layer 32 is provided, the number of manufacturing steps is not increased.
【００２２】多結晶Ｓｉ膜１６及びシリサイド膜３１の
他方の素子活性領域には、列方向に並んでいる２個のメ
モリセルに共通のドレインとしてのＮ+ 型の拡散層２２
が形成されている。また、多結晶Ｓｉ膜１４、１６等の
側面には、ＳｉＯ2 膜３３から成る側壁が設けられてお
り、ＳｉＯ2 膜３３に覆われている部分を除く拡散層２
１、２２、３２の表面をシリサイド膜３１が覆ってい
る。In the other element active region of the polycrystalline Si film 16 and the silicide film 31, an N + type diffusion layer 22 as a drain common to two memory cells arranged in the column direction is formed.
Are formed. Further, sidewalls made of the SiO 2 film 33 are provided on the side surfaces of the polycrystalline Si films 14, 16 and the like, and the diffusion layer 2 except the portion covered with the SiO 2 film 33 is provided.
The surfaces of 1, 22, 32 are covered with the silicide film 31.
【００２３】上述の様なシリサイド膜３１を形成するた
めには、ＳｉＯ2 膜３３から成る側壁を多結晶Ｓｉ膜１
４、１６等の側面に形成した後、例えばＴｉ膜を１００
ｎｍの膜厚にスパッタリング堆積させ、７００℃程度の
アニールを行う。In order to form the silicide film 31 as described above, the side wall of the SiO 2 film 33 is covered with the polycrystalline Si film 1
After forming on the side surfaces of 4, 16, etc., for example, a Ti film is formed by 100
The film is deposited to a thickness of nm by sputtering and annealed at about 700 ° C.
【００２４】すると、ＳｉＯ2 膜１２、３３から露出し
ている拡散層２１、２２、３２の表面及び多結晶Ｓｉ膜
１６とＴｉ膜とが反応して、チタンシリサイド膜３１が
形成され、ＳｉＯ2 膜１２、３３上のＴｉ膜は金属膜の
ままで残る。従って、金属膜のままで残っているＴｉ膜
を選択的に除去することによって、拡散層２１、２２、
３２上及び多結晶Ｓｉ膜１６上にのみ、シリサイド膜３
１が自己整合的に形成される。Then, the surface of the diffusion layers 21, 22, 32 exposed from the SiO 2 films 12, 33 and the polycrystalline Si film 16 and the Ti film react with each other to form a titanium silicide film 31, and SiO 2 film. The Ti film on the films 12 and 33 remains as a metal film. Therefore, by selectively removing the Ti film remaining as the metal film, the diffusion layers 21, 22,
32 and the polycrystalline Si film 16 only, the silicide film 3
1 is formed in a self-aligned manner.
【００２５】シリサイド膜３１等を覆う層間絶縁膜（図
示せず）には、拡散層２２上のシリサイド膜３１に達す
るコンタクト孔２４が形成されている。そして、コンタ
クト孔２４を介して拡散層２２上のシリサイド膜３１に
接続されると共に列方向に延在するＡｌ膜２６等で、ビ
ット線が形成されている。A contact hole 24 reaching the silicide film 31 on the diffusion layer 22 is formed in an interlayer insulating film (not shown) covering the silicide film 31 and the like. The bit line is formed by the Al film 26 and the like which is connected to the silicide film 31 on the diffusion layer 22 through the contact hole 24 and extends in the column direction.
【００２６】以上の様な第１実施例では、拡散層３２が
Ｓｉ基板１１と同一導電型であるので、拡散層３２はＳ
ｉ基板１１と同電位になり、拡散層２１、３２はシリサ
イド膜３１とオーミック接続されているので、シリサイ
ド膜３１を介して拡散層２１は拡散層３２と同電位にな
り、結局、拡散層２１には、ソース電位として、Ｓｉ基
板１１と同じ接地電位が与えられる。In the first embodiment as described above, since the diffusion layer 32 has the same conductivity type as the Si substrate 11, the diffusion layer 32 is S.
Since it has the same potential as the i substrate 11 and the diffusion layers 21 and 32 are ohmic-connected to the silicide film 31, the diffusion layer 21 has the same potential as the diffusion layer 32 through the silicide film 31, and in the end, the diffusion layer 21. Is given the same ground potential as the Si substrate 11 as the source potential.
【００２７】しかも、以上の様な第１実施例では、図２
からも明らかな様に、図５の一従来例におけるコンタク
ト孔２３及びＡｌ膜２５が設けられていないので、これ
らのコンタクト孔２３やＡｌ膜２５のための領域が不要
であり、微細化、高密度化が可能である。Moreover, in the first embodiment as described above, FIG.
As is apparent from FIG. 5, since the contact hole 23 and the Al film 25 in the conventional example of FIG. 5 are not provided, the regions for the contact hole 23 and the Al film 25 are unnecessary, and the miniaturization and high Densification is possible.
【００２８】図３は、第２実施例を示している。この第
２実施例は、Ｐ+ 型の拡散層３２が、行方向におけるメ
モリセル同士の境界部に島状に配置されているのではな
く、行方向へ連続していることを除いて、図１、２に示
した第１実施例と実質的に同様の構成を有している。そ
して、この様な第２実施例でも、第１実施例と同様の作
用効果を奏することができる。FIG. 3 shows a second embodiment. The second embodiment is different from the first embodiment except that the P + type diffusion layer 32 is not arranged in an island shape at the boundary between memory cells in the row direction but is continuous in the row direction. It has substantially the same structure as the first embodiment shown in FIGS. In addition, also in the second embodiment as described above, it is possible to obtain the same operational effect as that of the first embodiment.
【００２９】なお、以上の第１及び第２実施例は、ＥＴ
ＯＸ型のフラッシュＥＥＰＲＯＭに本願の発明を適用し
たものであるが、ＥＴＯＸ型以外のＮＡＮＤ型やＤＩＮ
ＯＲ型等のフラッシュＥＥＰＲＯＭや、フラッシュＥＥ
ＰＲＯＭ以外のＥＥＰＲＯＭ、ＥＰＲＯＭ、マスクＲＯ
Ｍ等の不揮発性半導体記憶装置や、不揮発性半導体記憶
装置以外の半導体装置にも、本願の発明を適用すること
ができる。The first and second embodiments described above are ET
Although the present invention is applied to an OX type flash EEPROM, a NAND type or DIN other than the ETOX type is used.
OR type flash EEPROM and flash EE
EEPROM other than PROM, EPROM, mask RO
The invention of the present application can be applied to a nonvolatile semiconductor memory device such as M, or a semiconductor device other than the nonvolatile semiconductor memory device.
【００３０】[0030]
【発明の効果】請求項１の半導体装置では、第１及び第
２の拡散層に対するコンタクト孔や配線を設ける必要が
なく、これらのコンタクト孔や配線のための領域が不要
であるので、微細化、高密度化が可能である。According to the semiconductor device of the present invention, it is not necessary to provide contact holes or wirings for the first and second diffusion layers, and regions for these contact holes and wirings are not required. Higher density is possible.
【００３１】請求項２の半導体装置では、第１及び第２
の拡散層の表面に接した状態で広がる導電膜を形成する
ための領域に余裕領域を設ける必要がないので、更なる
微細化、高密度化が可能である。According to another aspect of the semiconductor device of the present invention, the first and second semiconductor devices are provided.
Since it is not necessary to provide a margin area in the area for forming the conductive film which spreads in contact with the surface of the diffusion layer, further miniaturization and higher density are possible.
【００３２】請求項３〜５の半導体装置では、共通ソー
ス線の抵抗を実質的になくすことができるので、共通ソ
ース線の抵抗の変動に起因する特性の変動がなく、信頼
性が高い。In the semiconductor device according to the third to fifth aspects, the resistance of the common source line can be substantially eliminated, so that there is no change in the characteristics due to the change in the resistance of the common source line and the reliability is high.
【図１】本願の発明の第１実施例を示しており、図２の
Ｉ−Ｉ線に沿う位置における拡大側断面図である。FIG. 1 shows a first embodiment of the invention of the present application and is an enlarged side sectional view taken along a line I-I in FIG.
【図２】第１実施例の平面図である。FIG. 2 is a plan view of the first embodiment.
【図３】本願の発明の第２実施例の平面図である。FIG. 3 is a plan view of a second embodiment of the present invention.
【図４】本願の発明の一従来例を示しており、図５のＩ
Ｖ−ＩＶ線に沿う位置における拡大側断面図である。FIG. 4 shows a conventional example of the invention of the present application, which is indicated by I in FIG.
It is an expanded side sectional view in the position which follows the V-IV line.
【図５】一従来例の平面図である。FIG. 5 is a plan view of a conventional example.
１１ Ｓｉ基板 ２１ 拡散層 ３１ シリサイド膜 ３２ 拡散層 11 Si substrate 21 Diffusion layer 31 Silicide film 32 Diffusion layer
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 ＦＩ 技術表示箇所 Ｈ０１Ｌ 27/115 29/78 21/336 Ｈ０１Ｌ 29/78 ３０１ Ｓ ３０１ Ｐ ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 6 Identification code Internal reference number FI Technical indication location H01L 27/115 29/78 21/336 H01L 29/78 301 S 301 P
Claims (5)
拡散層が前記半導体基板とは逆導電型である半導体装置
において、 前記半導体基板と同一導電型の第２の拡散層が前記半導
体基板に設けられており、 金属を含有する導電膜が前記第１及び第２の拡散層の表
面に接した状態で広がっていることを特徴とする半導体
装置。1. A semiconductor device in which a first diffusion layer to be made to have the same potential as a semiconductor substrate has a conductivity type opposite to that of the semiconductor substrate, and a second diffusion layer having the same conductivity type as the semiconductor substrate is the semiconductor. A semiconductor device provided on a substrate, wherein a conductive film containing a metal spreads in a state of being in contact with the surfaces of the first and second diffusion layers.
合的に形成されているシリサイド膜であることを特徴と
する請求項１記載の半導体装置。2. The semiconductor substrate is a silicon substrate, and the conductive film is a silicide film formed on the surfaces of the first and second diffusion layers in a self-aligned manner. The semiconductor device described.
ており、 前記第１及び第２の拡散層が前記複数のトランジスタの
共通ソース線になっていることを特徴とする請求項１ま
たは２記載の半導体装置。3. A plurality of transistors are continuously arranged, and the first and second diffusion layers serve as a common source line of the plurality of transistors. Semiconductor device.
延在方向における前記複数のトランジスタ同士の境界部
に配置されていることを特徴とする請求項３記載の半導
体装置。4. The semiconductor device according to claim 3, wherein the second diffusion layer is arranged at a boundary between the plurality of transistors in the extending direction of the common source line.
幅方向の中央部においてこの共通ソース線の延在方向へ
連続していることを特徴とする請求項３記載の半導体装
置。5. The semiconductor device according to claim 3, wherein the second diffusion layer is continuous in the extending direction of the common source line at the central portion in the width direction of the common source line.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6288889A JPH08130263A (en) | 1994-10-28 | 1994-10-28 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6288889A JPH08130263A (en) | 1994-10-28 | 1994-10-28 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH08130263A true JPH08130263A (en) | 1996-05-21 |
Family
ID=17736094
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6288889A Pending JPH08130263A (en) | 1994-10-28 | 1994-10-28 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH08130263A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20020050115A (en) * | 2000-12-20 | 2002-06-26 | 가네꼬 히사시 | Semiconductor memory device with silicide layer formed selectively |
| WO2002015190A3 (en) * | 2000-08-15 | 2003-02-06 | Motorola Inc | Non-volatile memory, method of manufacture and programming |
| WO2003054965A3 (en) * | 2001-12-19 | 2004-03-04 | Motorola Inc | Non-volatile memory and method of forming thereof |
| JP2009111051A (en) * | 2007-10-29 | 2009-05-21 | Fujitsu Microelectronics Ltd | Semiconductor device and manufacturing method thereof |
| JP2010239147A (en) * | 2010-06-09 | 2010-10-21 | Renesas Electronics Corp | Non-volatile semiconductor memory device |
-
1994
- 1994-10-28 JP JP6288889A patent/JPH08130263A/en active Pending
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2002015190A3 (en) * | 2000-08-15 | 2003-02-06 | Motorola Inc | Non-volatile memory, method of manufacture and programming |
| JP2004507887A (en) * | 2000-08-15 | 2004-03-11 | モトローラ・インコーポレイテッド | Non-volatile memory, method of manufacturing and programming |
| CN1327526C (en) * | 2000-08-15 | 2007-07-18 | 自由度半导体公司 | Programming Method of Electrically Erasable Programmable Read-Only Memory Array |
| KR100762114B1 (en) * | 2000-08-15 | 2007-10-02 | 프리스케일 세미컨덕터, 인크. | Non-volatile memory, method of manufacture and programming |
| KR20020050115A (en) * | 2000-12-20 | 2002-06-26 | 가네꼬 히사시 | Semiconductor memory device with silicide layer formed selectively |
| WO2003054965A3 (en) * | 2001-12-19 | 2004-03-04 | Motorola Inc | Non-volatile memory and method of forming thereof |
| CN1316625C (en) * | 2001-12-19 | 2007-05-16 | 自由度半导体公司 | Nonvolatile memory and method of manufacturing the same |
| JP2009111051A (en) * | 2007-10-29 | 2009-05-21 | Fujitsu Microelectronics Ltd | Semiconductor device and manufacturing method thereof |
| US8741760B2 (en) | 2007-10-29 | 2014-06-03 | Fujitsu Semiconductor Limited | Method of manufacturing semiconductor device including first conductive pattern and second conductive pattern having top surface which decreases in height |
| JP2010239147A (en) * | 2010-06-09 | 2010-10-21 | Renesas Electronics Corp | Non-volatile semiconductor memory device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP2884408B2 (en) | Integrated circuit on semiconductor substrate, integrated memory cell and method of manufacturing the same | |
| JP2889061B2 (en) | Semiconductor storage device and method of manufacturing the same | |
| US5962889A (en) | Nonvolatile semiconductor memory with a floating gate that has a bottom surface that is smaller than the upper surface | |
| JP3175705B2 (en) | Manufacturing method of nonvolatile semiconductor memory device | |
| JPS60231357A (en) | Semiconductor memory device | |
| JP2001044391A (en) | Semiconductor storage device and manufacture thereof | |
| KR920007166A (en) | Method for manufacturing nonvolatile semiconductor memory device having storage cell array and peripheral circuit and its structure | |
| JPH09116119A (en) | Nonvolatile semiconductor storage device | |
| JPH0328832B2 (en) | ||
| US6228714B1 (en) | Method for manufacturing nonvolatile memory device | |
| JP3389112B2 (en) | Nonvolatile semiconductor memory device and method of manufacturing the same | |
| JP3441140B2 (en) | Semiconductor storage device | |
| JPH08241932A (en) | Nonvolatile semiconductor memory device and its manufacture | |
| US5973343A (en) | Semiconductor memory device having bit line directly held in contact through contact with impurity region in self-aligned manner and process of fabrication thereof | |
| JPH09213911A (en) | Semiconductor device and manufacturing method thereof | |
| US5151761A (en) | Nonvolatile semiconductor memory device with isolated gate electrodes | |
| JPH08130263A (en) | Semiconductor device | |
| JP2000223596A (en) | Semiconductor nonvolatile storage device and its manufacture | |
| US6605507B2 (en) | Non-volatile semiconductor memory device and manufacturing method thereof | |
| JP2002313970A (en) | Semiconductor storage | |
| JPH06350059A (en) | Nonvolatile semiconductor memory | |
| JPH07183411A (en) | Laminated-gate type nonvolatile semiconductor memory device | |
| JP2005183763A (en) | Method of manufacturing semiconductor device including non-volatile memory | |
| JP4031178B2 (en) | Manufacturing method of semiconductor high resistance element | |
| JPH03194967A (en) | Manufacture of semiconductor non-volatile memory |