JPH07183411A - Laminated-gate type nonvolatile semiconductor memory device - Google Patents

Laminated-gate type nonvolatile semiconductor memory device

Info

Publication number
JPH07183411A
JPH07183411A JP6032818A JP3281894A JPH07183411A JP H07183411 A JPH07183411 A JP H07183411A JP 6032818 A JP6032818 A JP 6032818A JP 3281894 A JP3281894 A JP 3281894A JP H07183411 A JPH07183411 A JP H07183411A
Authority
JP
Japan
Prior art keywords
film
gate electrode
control gate
polycrystalline
transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6032818A
Other languages
Japanese (ja)
Inventor
Hisanobu Sugiyama
寿伸 杉山
Masaru Miyashita
勝 宮下
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Publication of JPH07183411A publication Critical patent/JPH07183411A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H10B41/42—Simultaneous manufacture of periphery and memory cells
    • H10B41/43—Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor
    • H10B41/48—Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor with a tunnel dielectric layer also being used as part of the peripheral transistor

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)

Abstract

PURPOSE:To increase reliability and achieve high integration by reducing difference in level and to reduce a manufacturing cost by simplifying a manufacturing process and to achieve further high integration by reducing the area of a memory cell. CONSTITUTION:A floating gate electrode and a control gate electrode in a memory transistor 13 are respectively constituted of a conducting film of of the same layer as a polycrystalline Si film 24 and a WSix film 31 constituting a control gate electrode in a peripheral-circuit transistor 19. For this reason, as compared with the constitution in which a control gate electrode or the like is formed of the polycrystalline Si film 24 and the WSix film 31, the difference in level of a memory transistor 13 is smaller and it is easier to make flat and the manufacturing process is simpler.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【産業上の利用分野】本願の発明は、浮遊ゲート電極を
有している第１の絶縁ゲート電界効果トランジスタと浮
遊ゲート電極を有していない第２の絶縁ゲート電界効果
トランジスタとを有する積層ゲート型不揮発性半導体記
憶装置に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a stacked gate having a first insulated gate field effect transistor having a floating gate electrode and a second insulated gate field effect transistor having no floating gate electrode. Type non-volatile semiconductor memory device.

【０００２】[0002]

【従来の技術】図４は、ＮＯＲ型のＥＰＲＯＭやフラッ
シュＥＥＰＲＯＭ等のメモリ部１１を示している。これ
らのＮＯＲ型不揮発性半導体記憶装置では、半導体基板
の表面にフィールド絶縁膜１２が選択的に設けられて素
子分離領域が区画されており、フィールド絶縁膜１２に
囲まれている素子活性領域の表面にゲート絶縁膜（図示
せず）が設けられている。2. Description of the Related Art FIG. 4 shows a memory portion 11 such as a NOR type EPROM or a flash EEPROM. In these NOR type nonvolatile semiconductor memory devices, a field insulating film 12 is selectively provided on the surface of a semiconductor substrate to partition an element isolation region, and a surface of an element active region surrounded by the field insulating film 12 is formed. Is provided with a gate insulating film (not shown).

【０００３】メモリセルに対応する記憶トランジスタ１
３のチャネル領域上には、ゲート絶縁膜を介して浮遊ゲ
ート電極１４が設けられており、この浮遊ゲート電極１
４上には、容量結合用の絶縁膜（図示せず）を介して制
御ゲート電極１５が積層されている。浮遊ゲート電極１
４及び制御ゲート電極１５の両側の素子活性領域には、
記憶トランジスタ１３のソース及びドレインとしての拡
散層１６が設けられている。Storage transistor 1 corresponding to a memory cell
The floating gate electrode 14 is provided on the channel region of No. 3 through the gate insulating film.
A control gate electrode 15 is stacked on the gate electrode 4 via an insulating film (not shown) for capacitive coupling. Floating gate electrode 1
4 and the device active regions on both sides of the control gate electrode 15,
A diffusion layer 16 is provided as a source and a drain of the memory transistor 13.

【０００４】制御ゲート電極１５等は層間絶縁膜（図示
せず）に覆われており、ドレインとしての拡散層１６に
達するコンタクト孔１７が層間絶縁膜等に開孔されてい
る。そして、このコンタクト孔１７を介して、ドレイン
としての拡散層１６にビット線（図示せず）がコンタク
トしている。The control gate electrode 15 and the like are covered with an interlayer insulating film (not shown), and a contact hole 17 reaching the diffusion layer 16 as a drain is opened in the interlayer insulating film and the like. A bit line (not shown) is in contact with the diffusion layer 16 as the drain through the contact hole 17.

【０００５】図５は、図４に示したＮＯＲ型不揮発性半
導体記憶装置である本願の発明の第１従来例を製造する
ための方法を、メモリ部１１の記憶トランジスタ１３と
周辺回路部１８の周辺回路トランジスタ１９とについて
示している。この製造方法では、図５（ａ）に示す様
に、Ｐ型のＳｉ基板２１の表面にフィールド絶縁膜１２
としてのＳｉＯ2 膜２２をＬＯＣＯＳ法で選択的に形成
して素子分離領域を区画し、ＳｉＯ2 膜２２に囲まれて
いる素子活性領域の表面にゲート絶縁膜としてのＳｉＯ
2 膜２３を形成する。FIG. 5 shows a method for manufacturing the first conventional example of the invention of the present application which is the NOR type nonvolatile semiconductor memory device shown in FIG. 4 in the memory transistor 13 of the memory section 11 and the peripheral circuit section 18. The peripheral circuit transistor 19 is shown. In this manufacturing method, as shown in FIG. 5A, the field insulating film 12 is formed on the surface of the P-type Si substrate 21.
SiO 2 film 22 as a film is selectively formed by the LOCOS method to partition the element isolation region, and SiO 2 as a gate insulating film is formed on the surface of the element active region surrounded by the SiO 2 film 22.
2 The film 23 is formed.

【０００６】その後、ＣＶＤ法で多結晶Ｓｉ膜２４を全
面に堆積させ、ＰＯＣｌ3 の蒸気に曝してこの蒸気から
リンを熱拡散させるプレデポジション法で多結晶Ｓｉ膜
２４にリンを添加する。そして、多結晶Ｓｉ膜２４に対
するＲＩＥで、後に形成する制御ゲート電極１４の延在
方向と垂直な方向に延在する縞状の多結晶Ｓｉ膜２４を
メモリ部１１にのみ残す。After that, the polycrystalline Si film 24 is deposited on the entire surface by the CVD method, and phosphorus is added to the polycrystalline Si film 24 by the pre-deposition method of exposing the vapor to POCl 3 vapor to thermally diffuse phosphorus. Then, the striped polycrystalline Si film 24 extending in the direction perpendicular to the extending direction of the control gate electrode 14 to be formed later is left only in the memory portion 11 by RIE on the polycrystalline Si film 24.

【０００７】次に、図５（ｂ）に示す様に、ＯＮＯ膜２
５を全面に形成し、図５（ｃ）に示す様に、メモリ部１
１のみをレジスト２６で覆って、周辺回路部１８のＯＮ
Ｏ膜２５を除去する。但し、この時、周辺回路部１８の
ＳｉＯ2 膜２３も除去される。そこで、図５（ｄ）に示
す様に、周辺回路部１６の素子活性領域の表面にゲート
絶縁膜としてのＳｉＯ2 膜２３を再び形成してから、全
面に多結晶Ｓｉ膜２７を堆積させ且つリンを添加する。Next, as shown in FIG. 5B, the ONO film 2
5 is formed on the entire surface, and as shown in FIG.
Only the 1 is covered with the resist 26, and the peripheral circuit section 18 is turned on.
The O film 25 is removed. However, at this time, the SiO 2 film 23 of the peripheral circuit portion 18 is also removed. Therefore, as shown in FIG. 5D, the SiO 2 film 23 as a gate insulating film is formed again on the surface of the element active region of the peripheral circuit portion 16, and then the polycrystalline Si film 27 is deposited on the entire surface. Add phosphorus.

【０００８】次に、図５（ｅ）に示す様に、ＷＳｉx 膜
３１等のシリサイド膜を全面に堆積させて、多結晶Ｓｉ
膜２７とＷＳｉx 膜３１とでポリサイド膜３２を形成す
る。そして、記憶トランジスタ１３の制御ゲート電極１
５及び周辺回路トランジスタ１９の制御ゲート電極のパ
ターンに、レジスト３３を加工する。Next, as shown in FIG. 5 (e), a silicide film such as the WSi x film 31 is deposited on the entire surface to form polycrystalline Si.
The film 27 and the WSi x film 31 form a polycide film 32. Then, the control gate electrode 1 of the memory transistor 13
5 and the resist 33 is processed into the pattern of the control gate electrode of the peripheral circuit transistor 19.

【０００９】次に、図５（ｆ）に示す様に、レジスト３
３をマスクにしてポリサイド膜３２とＯＮＯ膜２５とを
連続的にエッチングし、レジスト３３を剥離した後、別
のレジスト（図示せず）で周辺回路部１８のみを覆った
状態で、ＷＳｉx 膜３１等ををマスクにしてメモリ部１
１の多結晶Ｓｉ膜２４をエッチングする。そして、ＷＳ
ｉx 膜３１等をマスクにしてＳｉ基板２１中にＮ+ 拡散
層３４を形成して、記憶トランジスタ１３及び周辺回路
トランジスタ１９を完成させる。その後、更に従来公知
の工程を実行する。Next, as shown in FIG.
3 as a mask and a polycide film 32 and the ONO film 25 continuously etched, after removing the resist 33, while covering only the peripheral circuit portion 18 by another resist (not shown), WSi x film Memory part 1 with 31 etc. as a mask
The polycrystalline Si film 24 of No. 1 is etched. And WS
Using the i x film 31 and the like as a mask, the N + diffusion layer 34 is formed in the Si substrate 21 to complete the memory transistor 13 and the peripheral circuit transistor 19. Then, a conventionally known process is further performed.

【００１０】以上の様にして製造した第１従来例におけ
るメモリ部１１の記憶トランジスタ１３では、多結晶Ｓ
ｉ膜２４が浮遊ゲート電極１４になっており、ＯＮＯ膜
２５が容量結合用の絶縁膜になっており、ポリサイド膜
３２が制御ゲート電極１５になっている。また、周辺回
路部１８の周辺回路トランジスタ１９では、ポリサイド
膜３２が制御ゲート電極になっている。In the storage transistor 13 of the memory portion 11 in the first conventional example manufactured as described above, the polycrystalline S
The i film 24 is the floating gate electrode 14, the ONO film 25 is the insulating film for capacitive coupling, and the polycide film 32 is the control gate electrode 15. Further, in the peripheral circuit transistor 19 of the peripheral circuit portion 18, the polycide film 32 serves as a control gate electrode.

【００１１】図６は、８段のＮＡＮＤ型のＥＰＲＯＭや
フラッシュＥＥＰＲＯＭ等のメモリ部１１を示してい
る。これらの８段のＮＡＮＤ型不揮発性半導体記憶装置
では、８個の記憶トランジスタ１３が拡散層１６を順次
に共有して直列に配置されており、８個の記憶トランジ
スタ１３の両側に更に１個ずつの選択トランジスタ３５
が直列に配置されている。FIG. 6 shows a memory section 11 such as an 8-stage NAND type EPROM or flash EEPROM. In these eight-stage NAND type nonvolatile semiconductor memory devices, eight memory transistors 13 are arranged in series with the diffusion layer 16 sequentially shared, and one memory transistor is further provided on each side of the eight memory transistors 13. Selection transistor 35
Are arranged in series.

【００１２】各記憶トランジスタ１３には、上述のＮＯ
Ｒ型不揮発性半導体記憶装置の場合と同様に制御ゲート
電極１５の他に浮遊ゲート電極１４も設けられている
が、選択トランジスタ３５には、制御ゲート電極１５し
か設けられていない。ビット線用のコンタクト孔１７
は、一方の選択トランジスタ３５の記憶トランジスタ１
３とは反対側の拡散層１６上に設けられている。Each memory transistor 13 has a NO
As in the case of the R-type nonvolatile semiconductor memory device, the floating gate electrode 14 is provided in addition to the control gate electrode 15, but the select transistor 35 is provided with only the control gate electrode 15. Contact hole for bit line 17
Is a memory transistor 1 of one selection transistor 35.
It is provided on the diffusion layer 16 on the side opposite to 3.

【００１３】図７は、図６に示したＮＡＮＤ型不揮発性
半導体記憶装置である本願の発明の第２従来例のうち
で、選択トランジスタ３５を示している。この第２従来
例の記憶トランジスタ１３では、ゲート絶縁膜であるＳ
ｉＯ2 膜２３上の多結晶Ｓｉ膜３６、ＳｉＯ2 膜３７及
び多結晶Ｓｉ膜３８が、夫々浮遊ゲート電極１４、容量
結合用の絶縁膜及び制御ゲート電極１５になっている。FIG. 7 shows the selection transistor 35 in the second conventional example of the invention of the present application which is the NAND type nonvolatile semiconductor memory device shown in FIG. In the memory transistor 13 of the second conventional example, the gate insulating film S
The polycrystalline Si film 36, the SiO 2 film 37, and the polycrystalline Si film 38 on the iO 2 film 23 serve as the floating gate electrode 14, the insulating film for capacitive coupling, and the control gate electrode 15, respectively.

【００１４】このため、図７に示す様に、選択トランジ
スタ３５では、多結晶Ｓｉ膜３８を多結晶Ｓｉ膜３６の
分路にして、これら２層の多結晶Ｓｉ膜３６、３８で制
御ゲート電極１５を構成している。即ち、メモリ部１１
の所定位置で多結晶Ｓｉ膜３８及びＳｉＯ2 膜３７にコ
ンタクト孔４１を設け、このコンタクト孔４１を覆って
形成したＡｌ膜４２を介して、多結晶Ｓｉ膜３６、３８
同士を電気的に接続している。Therefore, as shown in FIG. 7, in the select transistor 35, the polycrystalline Si film 38 is shunted to the polycrystalline Si film 36, and the control gate electrode is formed by these two polycrystalline Si films 36 and 38. Make up 15. That is, the memory unit 11
Contact holes 41 are provided in the polycrystalline Si film 38 and the SiO 2 film 37 at predetermined positions, and the polycrystalline Si films 36, 38 are formed through the Al film 42 formed so as to cover the contact holes 41.
They are electrically connected to each other.

【００１５】[0015]

【発明が解決しようとする課題】ところが、図５に示し
た第１従来例では、図５（ｆ）からも明らかな様に、周
辺回路トランジスタ１９における段差に比べて記憶トラ
ンジスタ１３における段差が大きい。このため、コンタ
クト孔１７のアスペクト比が大きくて、信頼性が低い。
また、平坦化が容易ではないので、多層配線化による高
集積化も困難である。しかも、２層の多結晶Ｓｉ膜２
４、２７を形成する必要があるので、通常の絶縁ゲート
電界効果トランジスタに比べて、製造工程が多くて、製
造コストが高い。However, in the first conventional example shown in FIG. 5, the step difference in the memory transistor 13 is larger than the step difference in the peripheral circuit transistor 19, as is apparent from FIG. 5 (f). . Therefore, the aspect ratio of the contact hole 17 is large and the reliability is low.
Further, since flattening is not easy, it is also difficult to achieve high integration due to multi-layer wiring. Moreover, the two-layer polycrystalline Si film 2
Since it is necessary to form Nos. 4 and 27, the number of manufacturing steps is larger and the manufacturing cost is higher than that of a normal insulated gate field effect transistor.

【００１６】また、図７に示した第２従来例では、多結
晶Ｓｉ膜３６、３８同士を電気的に接続するために、コ
ンタクト孔４１及びＡｌ膜４２が必要である。ところ
が、図７（ｂ）からも明らかな様に、多結晶Ｓｉ膜３
６、３８に比べてパターニングの容易でないＡｌ膜４２
では多結晶Ｓｉ膜３６、３８よりもピッチを大きくする
必要があり、また段差被覆性の良くないＡｌ膜４２のた
めにコンタクト孔４１の寸法を大きくする必要がある。
従って、この第２従来例では、メモリセル面積を縮小し
て高集積化を図ることが困難である。Further, in the second conventional example shown in FIG. 7, the contact hole 41 and the Al film 42 are required to electrically connect the polycrystalline Si films 36 and 38 to each other. However, as is clear from FIG. 7B, the polycrystalline Si film 3
Al film 42 which is not easily patterned as compared with 6 and 38
Then, it is necessary to make the pitch larger than that of the polycrystalline Si films 36 and 38, and it is also necessary to increase the size of the contact hole 41 due to the Al film 42 having poor step coverage.
Therefore, in the second conventional example, it is difficult to reduce the memory cell area and achieve high integration.

【００１７】[0017]

【課題を解決するための手段】請求項１の積層ゲート型
不揮発性半導体記憶装置は、チャネル領域上に第１の絶
縁膜２３を介して浮遊ゲート電極１４が設けられてお
り、この浮遊ゲート電極１４上に第２の絶縁膜２５、３
７を介して第１の制御ゲート電極１５が積層されている
第１の絶縁ゲート電界効果トランジスタ１３と、前記第
１の絶縁膜２３と同一層の第３の絶縁膜２３を介してチ
ャネル領域上に第２の制御ゲート電極１５が設けられて
いる第２の絶縁ゲート電界効果トランジスタ１９、３５
とを有する積層ゲート型不揮発性半導体記憶装置におい
て、前記浮遊ゲート電極１４と同一層の第１の導電膜２
４、３６と、前記第１の制御ゲート電極１５と同一層で
前記第１の導電膜２４、３６上に積層されている第２の
導電膜３１、３８とで、前記第２の制御ゲート電極１５
が構成されていることを特徴としている。According to another aspect of the present invention, there is provided a stacked gate type non-volatile semiconductor memory device, wherein a floating gate electrode 14 is provided on a channel region via a first insulating film 23. Second insulating film 25, 3 on
On the channel region via the first insulated gate field effect transistor 13 in which the first control gate electrode 15 is laminated via the third insulating film 23 in the same layer as the first insulating film 23. Second insulated gate field effect transistors 19, 35 having a second control gate electrode 15 provided therein
And a first conductive film 2 in the same layer as the floating gate electrode 14 in a stacked gate non-volatile semiconductor memory device having
The second control gate electrodes 4 and 36 and the second conductive films 31 and 38 that are stacked on the first conductive films 24 and 36 in the same layer as the first control gate electrode 15. 15
Is configured.

【００１８】請求項２の積層ゲート型不揮発性半導体記
憶装置は、請求項１の積層ゲート型不揮発性半導体記憶
装置において、前記第１の制御ゲート電極１５が半導体
膜３８から成っていることを特徴としている。A stacked gate type non-volatile semiconductor memory device according to a second aspect is the stacked gate type non-volatile semiconductor memory device according to the first aspect, wherein the first control gate electrode 15 comprises a semiconductor film 38. I am trying.

【００１９】請求項３の積層ゲート型不揮発性半導体記
憶装置は、請求項１の積層ゲート型不揮発性半導体記憶
装置において、前記第１の制御ゲート電極１５がシリサ
イド膜３１から成っていることを特徴としている。A stacked gate non-volatile semiconductor memory device according to a third aspect is the stacked gate non-volatile semiconductor memory device according to the first aspect, wherein the first control gate electrode 15 is formed of a silicide film 31. I am trying.

【００２０】請求項４の積層ゲート型不揮発性半導体記
憶装置は、請求項２または３の積層ゲート型不揮発性半
導体記憶装置において、前記第２の絶縁膜２５、３７の
うちで前記第１の制御ゲート電極１５との対接面に半導
体窒化膜が設けられていることを特徴としている。A stacked gate type non-volatile semiconductor memory device according to a fourth aspect is the stacked gate type non-volatile semiconductor memory device according to the second or third aspect, in which the first control of the second insulating films 25 and 37 is performed. It is characterized in that a semiconductor nitride film is provided on the surface facing the gate electrode 15.

【００２１】[0021]

【作用】請求項１〜３の積層ゲート型不揮発性半導体記
憶装置では、第１の絶縁ゲート電界効果トランジスタ１
３における浮遊ゲート電極１４及び第１の制御ゲート電
極１５が、第２の絶縁ゲート電界効果トランジスタ１
９、３５における第２の制御ゲート電極１５を構成して
いる第１及び第２の導電膜２４、３６及び３１、３８と
夫々同一層の導電膜２４、３６及び３１、３８から成っ
ている。In the stacked gate nonvolatile semiconductor memory device according to claims 1 to 3, the first insulated gate field effect transistor 1 is used.
The floating gate electrode 14 and the first control gate electrode 15 in FIG.
The first and second conductive films 24, 36 and 31, 38 which form the second control gate electrode 15 in 9, 35 are composed of the same conductive films 24, 36 and 31, 38, respectively.

【００２２】このため、浮遊ゲート電極１４または第１
の制御ゲート電極１５の何れかが第１及び第２の導電膜
２４、３６及び３１、３８の両方から成っている構造に
比べて、第１の絶縁ゲート電界効果トランジスタ１３に
おける段差が小さくて平坦化が容易であり、しかも、第
１及び第２の導電膜２４、３６及び３１、３８以外の導
電膜４２を用いる必要がなくて製造工程が簡略である。Therefore, the floating gate electrode 14 or the first
In comparison with the structure in which any one of the control gate electrodes 15 is composed of both the first and second conductive films 24, 36 and 31, 38, the step difference in the first insulated gate field effect transistor 13 is small and flat. The manufacturing process is simple because there is no need to use a conductive film 42 other than the first and second conductive films 24, 36 and 31, 38.

【００２３】また、第２の絶縁ゲート電界効果トランジ
スタ１９、３５では、第１の導電膜２４、３６とこの第
１の導電膜２４、３６上に積層されている第２の導電膜
３１、３８とで第２の制御ゲート電極１５が構成されて
おり、これら第１及び第２の導電膜２４、３６及び３
１、３８の間には絶縁膜が介在していない。このため、
第１及び第２の導電膜２４、３６及び３１、３８同士を
電気的に接続するためのコンタクト孔４１及び追加の導
電膜４２が不要であり、これらが必要な構造に比べてメ
モリセル面積を縮小することが可能である。In the second insulated gate field effect transistors 19 and 35, the first conductive films 24 and 36 and the second conductive films 31 and 38 laminated on the first conductive films 24 and 36. And the second control gate electrode 15 is composed of the first and second conductive films 24, 36 and 3
There is no insulating film between 1 and 38. For this reason,
The contact hole 41 and the additional conductive film 42 for electrically connecting the first and second conductive films 24, 36 and 31, 38 are unnecessary, and the memory cell area can be reduced as compared with the structure in which they are required. It can be reduced.

【００２４】請求項４の積層ゲート型不揮発性半導体記
憶装置では、第２の制御ゲート電極１９、３５を構成し
ている第１の導電膜２４、３６の表面から自然酸化膜を
除去したりする際に、第１の絶縁ゲート電界効果トラン
ジスタ１３における第２の絶縁膜２５、３７がエッチン
グされるのを半導体窒化膜で防止することが可能であ
る。In the stacked gate non-volatile semiconductor memory device according to the fourth aspect, the natural oxide film is removed from the surfaces of the first conductive films 24 and 36 forming the second control gate electrodes 19 and 35. At this time, the semiconductor nitride film can prevent the second insulating films 25 and 37 in the first insulated gate field effect transistor 13 from being etched.

【００２５】また、第１の制御ゲート電極１５がシリサ
イド膜３１から成っていても、半導体窒化膜のために第
１の制御ゲート電極１５と第２の絶縁膜２５との密着性
が良く、且つ第１の制御ゲート電極１５の組成物が第２
の絶縁膜２５中へ侵入して第２の絶縁膜２５の膜質が劣
化するのを半導体窒化膜で防止することができる。Even if the first control gate electrode 15 is made of the silicide film 31, the adhesion between the first control gate electrode 15 and the second insulating film 25 is good because of the semiconductor nitride film, and The composition of the first control gate electrode 15 is the second
The semiconductor nitride film can prevent the deterioration of the film quality of the second insulating film 25 by penetrating into the insulating film 25.

【００２６】[0026]

【実施例】以下、本願の発明の第１及び第２実施例を、
図１〜３を参照しながら説明する。なお、図５、７に示
した第１及び第２従来例と対応する構成部分には、同一
の符号を付してある。The first and second embodiments of the present invention will be described below.
This will be described with reference to FIGS. The components corresponding to those of the first and second conventional examples shown in FIGS. 5 and 7 are designated by the same reference numerals.

【００２７】図１は、図４に示したＮＯＲ型不揮発性半
導体記憶装置である本願の発明の第１実施例を製造する
ための方法を、メモリ部１１の記憶トランジスタ１３と
周辺回路部１８の周辺回路トランジスタ１９とについて
示している。この製造方法でも、図１（ａ）に示す様
に、全面に堆積させた多結晶Ｓｉ膜２４にリンを添加す
るまでは、図５に示した第１従来例を製造する場合と実
質的に同様の工程を実行する。FIG. 1 shows a method for manufacturing the NOR type nonvolatile semiconductor memory device shown in FIG. 4 according to the first embodiment of the present invention, in which the memory transistor 13 of the memory section 11 and the peripheral circuit section 18 are manufactured. The peripheral circuit transistor 19 is shown. Also in this manufacturing method, as shown in FIG. 1A, until the polycrystalline Si film 24 deposited on the entire surface is doped with phosphorus, it is substantially the same as the case of manufacturing the first conventional example shown in FIG. Perform similar steps.

【００２８】しかし、この第１実施例を製造するために
は、その後、多結晶Ｓｉ膜２４に対するＲＩＥで、後に
形成する制御ゲート電極１５の延在方向と垂直な方向に
延在する縞状の多結晶Ｓｉ膜２４をメモリ部１１に残す
と同時に、周辺回路部１８の全面にも多結晶Ｓｉ膜２４
を残す。However, in order to manufacture this first embodiment, RIE is then performed on the polycrystalline Si film 24 to form a striped pattern extending in a direction perpendicular to the extending direction of the control gate electrode 15 to be formed later. At the same time that the polycrystalline Si film 24 is left in the memory section 11, the polycrystalline Si film 24 is also formed on the entire surface of the peripheral circuit section 18.
Leave.

【００２９】次に、図１（ｂ）に示す様に、多結晶Ｓｉ
膜２４等の表面にＯＮＯ膜２５を形成し、更に、図１
（ｃ）に示す様に、メモリ部１１のみをレジスト２６で
覆って、周辺回路部１８のＯＮＯ膜２５をプラズマエッ
チング等で除去する。Next, as shown in FIG. 1B, polycrystalline Si
An ONO film 25 is formed on the surface of the film 24 and the like.
As shown in (c), only the memory portion 11 is covered with the resist 26, and the ONO film 25 of the peripheral circuit portion 18 is removed by plasma etching or the like.

【００３０】次に、図１（ｄ）に示す様に、レジスト２
６を剥離した後、周辺回路部１８における多結晶Ｓｉ膜
２４上の自然酸化膜（図示せず）をフッ酸水でエッチン
グする。この時、メモリ部１１におけるＯＮＯ膜２５の
うちの上層側のＳｉＯ2 膜も同時にエッチングされるの
で、それを見込んでこのＳｉＯ2 膜の膜厚を厚くしてお
く。Next, as shown in FIG. 1D, the resist 2
After peeling off 6, the natural oxide film (not shown) on the polycrystalline Si film 24 in the peripheral circuit portion 18 is etched with hydrofluoric acid water. At this time, since the upper SiO 2 film of the ONO film 25 in the memory section 11 is also etched at the same time, the thickness of this SiO 2 film is increased in consideration of it.

【００３１】その後、ＷＳｉx 膜３１等のシリサイド膜
を全面に堆積させて、周辺回路部１８のみにおいて、多
結晶Ｓｉ膜２４とＷＳｉx 膜３１とでポリサイド膜４３
を形成する。そして、記憶トランジスタ１３の制御ゲー
ト電極１５及び周辺回路トランジスタ１９の制御ゲート
電極のパターンに、レジスト３３を加工する。Thereafter, a silicide film such as the WSi x film 31 is deposited on the entire surface, and the polycide film 43 is formed by the polycrystalline Si film 24 and the WSi x film 31 only in the peripheral circuit section 18.
To form. Then, the resist 33 is processed into patterns of the control gate electrode 15 of the memory transistor 13 and the control gate electrode of the peripheral circuit transistor 19.

【００３２】次に、図１（ｅ）に示す様に、レジスト３
３をマスクにして、ＷＳｉx 膜３１のみをＲＩＥでエッ
チングする。その後、高選択比酸化膜エッチング装置に
よって、図１（ｆ）に示す様に、メモリ部１１のＯＮＯ
膜２５をエッチングし、引き続いてメモリ部１１及び周
辺回路部１８の多結晶Ｓｉ膜２４をエッチングする。そ
して、ＷＳｉx 膜３１等をマスクにして、Ｓｉ基板２１
中にＮ+ 拡散層３４を形成して、記憶トランジスタ１３
及び周辺回路トランジスタ１９を完成させる。その後、
更に従来公知の工程を実行する。Next, as shown in FIG. 1E, the resist 3
Using W3 as a mask, only the WSi x film 31 is etched by RIE. Then, as shown in FIG. 1F, the ONO of the memory unit 11 is turned on by a high selectivity oxide film etching apparatus.
The film 25 is etched, and then the polycrystalline Si film 24 of the memory section 11 and the peripheral circuit section 18 is etched. Then, using the WSi x film 31 and the like as a mask, the Si substrate 21
An N + diffusion layer 34 is formed in the storage transistor 13
And the peripheral circuit transistor 19 is completed. afterwards,
Further, conventionally known steps are executed.

【００３３】以上の様にして製造した第１実施例におけ
るメモリ部１１の記憶トランジスタ１３では、多結晶Ｓ
ｉ膜２４が浮遊ゲート電極１４になっており、ＯＮＯ膜
２５が容量結合用の絶縁膜になっており、ＷＳｉx 膜３
１が制御ゲート電極１５になっている。また、周辺回路
部１８の周辺回路トランジスタ１９では、ポリサイド膜
４３が制御ゲート電極になっている。In the storage transistor 13 of the memory section 11 in the first embodiment manufactured as described above, the polycrystalline S
The i film 24 serves as the floating gate electrode 14, the ONO film 25 serves as an insulating film for capacitive coupling, and the WSi x film 3 is used.
1 is the control gate electrode 15. Further, in the peripheral circuit transistor 19 of the peripheral circuit portion 18, the polycide film 43 serves as a control gate electrode.

【００３４】そして、図１（ｆ）からも明らかな様に、
記憶トランジスタ１３における段差は周辺回路トランジ
スタ１９における段差に比べてＯＮＯ膜２５のために２
０ｎｍ程度大きいだけであり、記憶トランジスタ１３の
浮遊ゲート電極１４及び制御ゲート電極１５である多結
晶Ｓｉ膜２４及びＷＳｉx 膜３１による段差と周辺回路
トランジスタ１９の制御ゲート電極であるポリサイド膜
４３による段差とは殆ど差がない。Then, as is clear from FIG. 1 (f),
The step difference in the memory transistor 13 is 2 because of the ONO film 25 as compared with the step difference in the peripheral circuit transistor 19.
The difference is only about 0 nm, and the step due to the polycrystalline Si film 24 and the WSi x film 31 which are the floating gate electrode 14 and the control gate electrode 15 of the memory transistor 13 and the step due to the polycide film 43 which is the control gate electrode of the peripheral circuit transistor 19 Is almost no difference.

【００３５】また、図５に示した第１従来例とこの第１
実施例とを比較すると、この第１実施例では、多結晶Ｓ
ｉ膜２７を用いていないので多結晶Ｓｉ膜２７の堆積及
びリンの添加等の工程が不要であると共に、多結晶Ｓｉ
膜２４をエッチングする際に周辺回路部１８を覆うレジ
ストのパターニング等の工程も不要であり、この第１実
施例の方が製造工程が簡略である。Further, the first conventional example shown in FIG. 5 and this first example
In comparison with the embodiment, in this first embodiment, the polycrystalline S
Since the i film 27 is not used, steps such as deposition of the polycrystalline Si film 27 and addition of phosphorus are unnecessary, and the polycrystalline Si film 27 is not used.
When etching the film 24, a step of patterning a resist covering the peripheral circuit portion 18 is not necessary, and the manufacturing process of the first embodiment is simpler.

【００３６】なお、第１実施例では、メモリ部１１の多
結晶Ｓｉ膜２４とＷＳｉx 膜３１との間の容量結合用の
絶縁膜としてＯＮＯ膜２５を用いているが、このＯＮＯ
膜２５上にＳｉＮ膜を設けたＯＮＯＮ膜を容量結合用の
絶縁膜として用いてもよい。このＯＮＯＮ膜を用いる
と、ＯＮＯ膜２５とＷＳｉx 膜３１との密着性が良く、
且つＷＳｉx 膜３１中のＷやＳｉ等がＯＮＯ膜２５のう
ちの上層側のＳｉＯ2 膜中へ侵入してＯＮＯ膜２５の膜
質が劣化するのを防止することができる。In the first embodiment, the ONO film 25 is used as an insulating film for capacitive coupling between the polycrystalline Si film 24 and the WSi x film 31 of the memory section 11. However, this ONO film is used.
An ONON film provided with a SiN film on the film 25 may be used as an insulating film for capacitive coupling. When this ONON film is used, the adhesion between the ONO film 25 and the WSi x film 31 is good,
In addition, it is possible to prevent W and Si in the WSi x film 31 from entering the upper SiO 2 film of the ONO film 25 and degrading the quality of the ONO film 25.

【００３７】また、このＯＮＯＮ膜を用いると、図１
（ｄ）の工程で、周辺回路部１８における多結晶Ｓｉ膜
２４上の自然酸化膜をフッ酸水でエッチングする際に、
メモリ部１１におけるＯＮＯ膜２５のうちの上層側のＳ
ｉＯ2 膜も同時にエッチングされるのを防止することが
できるので、それを見込んでこのＳｉＯ2 膜の膜厚を厚
くしておく必要もなくなる。When this ONON film is used, as shown in FIG.
In the step (d), when etching the natural oxide film on the polycrystalline Si film 24 in the peripheral circuit portion 18 with hydrofluoric acid water,
S on the upper layer side of the ONO film 25 in the memory section 11
Since it is possible to prevent the iO 2 film from being etched at the same time, it is not necessary to increase the thickness of the SiO 2 film in anticipation thereof.

【００３８】図２、３は、図６に示したＮＡＮＤ型不揮
発性半導体記憶装置である本願の発明の第２実施例を製
造するための方法を、メモリ部１１の記憶トランジスタ
１３と選択トランジスタ３５とについて示している。こ
の製造方法でも、素子活性領域の表面にゲート絶縁膜と
してのＳｉＯ2 膜２３を形成するまでは、図５に示した
第１従来例を製造する場合と実質的に同様の工程を実行
する。2 and 3 show a method for manufacturing the NAND type nonvolatile semiconductor memory device shown in FIG. 6 according to the second embodiment of the present invention, the memory transistor 13 and the select transistor 35 of the memory section 11. And about. Also in this manufacturing method, substantially the same steps as in the case of manufacturing the first conventional example shown in FIG. 5 are executed until the SiO 2 film 23 as a gate insulating film is formed on the surface of the element active region.

【００３９】この第２実施例を製造するためには、その
後、図２（ａ）に示す様に、ＣＶＤ法で多結晶Ｓｉ膜３
６を全面に堆積させ、図２（ｂ）に示す様に、直列に配
置すべき記憶トランジスタ１３の浮遊ゲート電極１４の
幅を規定する縞状の部分と選択トランジスタ３５を形成
すべき領域とを覆うパターンに、多結晶Ｓｉ膜３６上で
レジスト４４を加工する。そして、このレジスト４４を
マスクにして、多結晶Ｓｉ膜３６に対するＲＩＥを行
う。In order to manufacture this second embodiment, thereafter, as shown in FIG. 2A, the polycrystalline Si film 3 is formed by the CVD method.
2 is deposited on the entire surface, and as shown in FIG. 2B, a striped portion defining the width of the floating gate electrode 14 of the storage transistor 13 to be arranged in series and a region where the selection transistor 35 is to be formed are formed. A resist 44 is processed on the polycrystalline Si film 36 to cover the pattern. Then, using this resist 44 as a mask, RIE is performed on the polycrystalline Si film 36.

【００４０】次に、図２（ｃ）に示す様に、レジスト４
４を剥離した後、多結晶Ｓｉ膜３６を酸化して、その表
面にＳｉＯ2 膜３７を形成する。その後、図２（ｄ）に
示す様に、記憶トランジスタ１３を形成すべき領域のみ
をレジスト４５で覆って、選択トランジスタ３５を形成
すべき領域のＳｉＯ2 膜３７をエッチングする。そし
て、図２（ｅ）に示す様に、レジスト４５を剥離した
後、ＣＶＤ法で多結晶Ｓｉ膜３８を全面に堆積させる。Next, as shown in FIG. 2C, the resist 4
After peeling off 4, the polycrystalline Si film 36 is oxidized to form a SiO 2 film 37 on its surface. After that, as shown in FIG. 2D, only the region where the memory transistor 13 is to be formed is covered with the resist 45, and the SiO 2 film 37 in the region where the select transistor 35 is to be formed is etched. Then, as shown in FIG. 2E, after removing the resist 45, a polycrystalline Si film 38 is deposited on the entire surface by a CVD method.

【００４１】次に、図３（ａ）に示す様に、記憶トラン
ジスタ１３及び選択トランジスタ３５の制御ゲート電極
１５のパターンに、多結晶Ｓｉ膜３８上でレジスト４６
を加工し、このレジスト４６をマスクにして、多結晶Ｓ
ｉ膜３８に対するＲＩＥを行う。そして、図３（ｂ）に
示す様に、引き続きレジスト４６をマスクにして、この
レジスト４６から露出しているＳｉＯ2 膜３７に対する
ＲＩＥを行う。Next, as shown in FIG. 3A, a resist 46 is formed on the polycrystalline Si film 38 in the pattern of the control gate electrode 15 of the storage transistor 13 and the selection transistor 35.
Is processed, and using this resist 46 as a mask, polycrystalline S
RIE is performed on the i film 38. Then, as shown in FIG. 3B, using the resist 46 as a mask, RIE is performed on the SiO 2 film 37 exposed from the resist 46.

【００４２】次に、図３（ｃ）に示す様に、更に引き続
きレジスト４６をマスクにして、このレジスト４６から
露出している多結晶Ｓｉ膜３６に対するＲＩＥを行う。
そして、レジスト４６を剥離した後、多結晶Ｓｉ膜３８
等をマスクにして、Ｓｉ基板２１中に拡散層１６を形成
して、記憶トランジスタ１３及び選択トランジスタ３５
を完成させる。その後、更に従来公知の工程を実行す
る。Next, as shown in FIG. 3C, the resist 46 is further used as a mask to perform RIE on the polycrystalline Si film 36 exposed from the resist 46.
Then, after removing the resist 46, the polycrystalline Si film 38
Etc. as a mask, the diffusion layer 16 is formed in the Si substrate 21, and the storage transistor 13 and the selection transistor 35 are formed.
To complete. Then, a conventionally known process is further performed.

【００４３】以上の様にして製造した第２実施例の記憶
トランジスタ１３では、図３（ｃ）からも明らかな様
に、多結晶Ｓｉ膜３６、３８が夫々浮遊ゲート電極１４
及び制御ゲート電極１５になっており、ＳｉＯ2 膜３７
がこれらの多結晶Ｓｉ膜３６、３８同士を容量結合する
ための絶縁膜になっている。しかし、選択トランジスタ
３５では、ＳｉＯ2 膜３７が存在しておらず、共に制御
ゲート電極１５になっている多結晶Ｓｉ膜３６の上面と
多結晶Ｓｉ膜３８の下面とが全面的にコンタクトしてい
る。In the memory transistor 13 of the second embodiment manufactured as described above, as is apparent from FIG. 3C, the polycrystalline Si films 36 and 38 have floating gate electrodes 14 respectively.
And the control gate electrode 15 and the SiO 2 film 37.
Is an insulating film for capacitively coupling the polycrystalline Si films 36, 38 with each other. However, in the select transistor 35, the SiO 2 film 37 does not exist, and the upper surface of the polycrystalline Si film 36 and the lower surface of the polycrystalline Si film 38, both of which serve as the control gate electrode 15, are in full contact with each other. There is.

【００４４】従って、この第２実施例では、図７に示し
た第２従来例の様には、多結晶Ｓｉ膜３６、３８同士を
電気的に接続するためのコンタクト孔４１及びＡｌ膜４
２を必要とせず、これらが必要な第２従来例に比べてメ
モリセル面積を縮小することが可能である。Therefore, in the second embodiment, as in the second conventional example shown in FIG. 7, the contact hole 41 and the Al film 4 for electrically connecting the polycrystalline Si films 36 and 38 to each other.
It is possible to reduce the memory cell area as compared with the second conventional example which does not require the number 2 and requires them.

【００４５】なお、この第２実施例では、記憶トランジ
スタ１３の浮遊ゲート電極１４及び制御ゲート電極１５
である多結晶Ｓｉ膜３６、３８同士を容量結合するため
の絶縁膜として、ＳｉＯ2 膜３７を用いているが、この
ＳｉＯ2 膜３７上にＳｉＮ膜を設けてもよく、上述の第
１実施例と同様にＯＮＯ膜２５やＯＮＯＮ膜等を用いて
もよい。In the second embodiment, the floating gate electrode 14 and the control gate electrode 15 of the memory transistor 13 are included.
Although the SiO 2 film 37 is used as an insulating film for capacitively coupling the polycrystalline Si films 36 and 38, which is the above, a SiN film may be provided on the SiO 2 film 37. An ONO film 25, an ONON film, or the like may be used as in the example.

【００４６】[0046]

【発明の効果】請求項１〜３の積層ゲート型不揮発性半
導体記憶装置では、第１の絶縁ゲート電界効果トランジ
スタにおける段差が小さいので、コンタクト孔のアスペ
クト比が小さくて信頼性が高く、また平坦化が容易であ
るので、多層配線化による高集積化も可能である。しか
も、製造工程が簡略であるので、製造コストが低く、ま
たメモリセル面積を縮小することが可能であるので、更
なる高集積化が可能である。In the stacked gate nonvolatile semiconductor memory device according to the first to third aspects, since the step difference in the first insulated gate field effect transistor is small, the aspect ratio of the contact hole is small and the reliability is high, and the flatness is flat. Since it can be easily integrated, high integration can be achieved by using multi-layer wiring. In addition, since the manufacturing process is simple, the manufacturing cost is low, and the memory cell area can be reduced, so that higher integration is possible.

【００４７】請求項４の積層ゲート型不揮発性半導体記
憶装置では、第１の絶縁ゲート電界効果トランジスタに
おける第２の絶縁膜がエッチングされるのを防止するこ
とが可能であり、第１の制御ゲート電極と第２の絶縁膜
との密着性が良く、且つ第１の制御ゲート電極の組成物
が第２の絶縁膜中へ侵入して第２の絶縁膜の膜質が劣化
するのを防止することができるので、信頼性やデータ保
持特性が高い。In the stacked gate non-volatile semiconductor memory device according to the fourth aspect, it is possible to prevent the second insulating film in the first insulated gate field effect transistor from being etched, and the first control gate. Good adhesion between the electrode and the second insulating film, and preventing the composition of the first control gate electrode from penetrating into the second insulating film and deteriorating the film quality of the second insulating film. Therefore, reliability and data retention characteristics are high.

【図面の簡単な説明】[Brief description of drawings]

【図１】本願の発明の第１実施例の製造方法を工程順に
示す側断面図である。FIG. 1 is a side sectional view showing a method of manufacturing a semiconductor device according to a first embodiment of the invention in the order of steps.

【図２】本願の発明の第２実施例の製造方法の前半を工
程順に示しており、図６のＳ−Ｓ線に沿う位置における
側断面図である。FIG. 2 is a side cross-sectional view showing the first half of a manufacturing method of a second embodiment of the invention of the present application in the order of steps and taken along a line S-S in FIG.

【図３】第２実施例の製造方法の後半を工程順に示して
おり、図６のＳ−Ｓ線に沿う位置における側断面図であ
る。FIG. 3 is a side cross-sectional view showing the latter half of the manufacturing method of the second embodiment in process order and taken along the line S-S in FIG.

【図４】本願の発明を適用し得るＮＯＲ型の積層ゲート
型不揮発性半導体記憶装置におけるメモリ部の平面図で
ある。FIG. 4 is a plan view of a memory section in a NOR-type stacked gate nonvolatile semiconductor memory device to which the invention of the present application can be applied.

【図５】本願の発明の第１従来例の製造方法を工程順に
示す側断面図である。FIG. 5 is a side sectional view showing a manufacturing method of a first conventional example of the invention of the present application in the order of steps.

【図６】本願の発明を適用し得るＮＡＮＤ型の積層ゲー
ト型不揮発性半導体記憶装置におけるメモリ部の平面図
である。FIG. 6 is a plan view of a memory unit in a NAND-type stacked gate nonvolatile semiconductor memory device to which the invention of the present application can be applied.

【図７】本願の発明の第２従来例の要部を示しており、
（ａ）は側断面図、（ｂ）は平面図である。FIG. 7 shows a main part of a second conventional example of the invention of the present application,
(A) is a side sectional view and (b) is a plan view.

【符号の説明】[Explanation of symbols]

１３ 記憶トランジスタ １４ 浮遊ゲート電極 １５ 制御ゲート電極 １９ 周辺回路トランジスタ ２３ ＳｉＯ2 膜 ２４ 多結晶Ｓｉ膜 ２５ ＯＮＯ膜 ３１ ＷＳｉx 膜 ３５ 選択トランジスタ ３６ 多結晶Ｓｉ膜 ３７ ＳｉＯ2 膜 ３８ 多結晶Ｓｉ膜13 Storage Transistor 14 Floating Gate Electrode 15 Control Gate Electrode 19 Peripheral Circuit Transistor 23 SiO 2 Film 24 Polycrystalline Si Film 25 ONO Film 31 WSi x Film 35 Select Transistor 36 Polycrystalline Si Film 37 SiO 2 Film 38 Polycrystalline Si Film

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 ＦＩ 技術表示箇所 Ｈ０１Ｌ 27/115 ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 6 Identification code Office reference number FI technical display location H01L 27/115

Claims (4)

【特許請求の範囲】[Claims] 【請求項１】 チャネル領域上に第１の絶縁膜を介して
浮遊ゲート電極が設けられており、この浮遊ゲート電極
上に第２の絶縁膜を介して第１の制御ゲート電極が積層
されている第１の絶縁ゲート電界効果トランジスタと、 前記第１の絶縁膜と同一層の第３の絶縁膜を介してチャ
ネル領域上に第２の制御ゲート電極が設けられている第
２の絶縁ゲート電界効果トランジスタとを有する積層ゲ
ート型不揮発性半導体記憶装置において、 前記浮遊ゲート電極と同一層の第１の導電膜と、前記第
１の制御ゲート電極と同一層で前記第１の導電膜上に積
層されている第２の導電膜とで、前記第２の制御ゲート
電極が構成されていることを特徴とする積層ゲート型不
揮発性半導体記憶装置。1. A floating gate electrode is provided on a channel region via a first insulating film, and a first control gate electrode is laminated on the floating gate electrode via a second insulating film. A first insulated gate field effect transistor, and a second insulated gate electric field in which a second control gate electrode is provided on the channel region through a third insulating film in the same layer as the first insulating film. A stacked gate type non-volatile semiconductor memory device having an effect transistor, wherein a first conductive film in the same layer as the floating gate electrode and a same layer as the first control gate electrode are stacked on the first conductive film. The second control gate electrode is constituted by the second conductive film being formed, and a stacked gate nonvolatile semiconductor memory device. 【請求項２】 前記第１の制御ゲート電極が半導体膜か
ら成っていることを特徴とする請求項１記載の積層ゲー
ト型不揮発性半導体記憶装置。2. The stacked gate type non-volatile semiconductor memory device according to claim 1, wherein the first control gate electrode is made of a semiconductor film. 【請求項３】 前記第１の制御ゲート電極がシリサイド
膜から成っていることを特徴とする請求項１記載の積層
ゲート型不揮発性半導体記憶装置。3. The stacked gate non-volatile semiconductor memory device according to claim 1, wherein the first control gate electrode is made of a silicide film. 【請求項４】 前記第２の絶縁膜のうちで前記第１の制
御ゲート電極との対接面に半導体窒化膜が設けられてい
ることを特徴とする請求項２または３記載の積層ゲート
型不揮発性半導体記憶装置。4. The stacked gate type according to claim 2, wherein a semiconductor nitride film is provided on a surface of the second insulating film which is in contact with the first control gate electrode. Nonvolatile semiconductor memory device.
JP6032818A 1993-11-09 1994-02-04 Laminated-gate type nonvolatile semiconductor memory device Pending JPH07183411A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP5-303321 1993-11-09
JP30332193 1993-11-09

Publications (1)

Publication Number Publication Date
JPH07183411A true JPH07183411A (en) 1995-07-21

Family

ID=17919568

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6032818A Pending JPH07183411A (en) 1993-11-09 1994-02-04 Laminated-gate type nonvolatile semiconductor memory device

Country Status (1)

Country Link
JP (1) JPH07183411A (en)

Cited By (7)

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US5925907A (en) * 1995-09-29 1999-07-20 Nippon Steel Corporaition Semiconductor device including transistor with composite gate structure and transistor with single gate structure
US6787844B2 (en) 1995-09-29 2004-09-07 Nippon Steel Corporation Semiconductor device including transistor with composite gate structure and transistor with single gate structure, and method for manufacturing the same
JP2004274062A (en) * 2003-03-10 2004-09-30 Samsung Electronics Co Ltd Eeprom with selecting transistor and method of manufacturing the same
EP1569274A1 (en) 2004-02-24 2005-08-31 STMicroelectronics S.r.l. Process for manufacturing semiconductor integrated non volatile memory devices
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JP2007207946A (en) * 2006-01-31 2007-08-16 Toshiba Corp Non-volatile semiconductor memory device
US7553724B2 (en) 2001-06-26 2009-06-30 Hynix Semiconductor Inc. Method for manufacturing code address memory cell by which a stack insulating film of an oxide film and a nitride film used as a dielectric film in a flash memory is used as a gate oxide film

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US7683423B2 (en) 1995-09-29 2010-03-23 Katsuki Hazama Semiconductor device including transistor with composite gate structure and transistor with single gate structure, and method for manufacturing the same
US7312496B2 (en) 1995-09-29 2007-12-25 Pegre Semiconductors, Llc Semiconductor device including transistor with composite gate structure and transistor with single gate structure, and method for manufacturing the same
US6913973B2 (en) 1995-09-29 2005-07-05 Nippon Steel Corporation Semiconductor device including transistor with composite gate structure and transistor with single gate structure, and method for manufacturing the same
US7439573B2 (en) 1995-09-29 2008-10-21 Pegre Semiconductors Llc Semiconductor device including transistor with composite gate structure and transistor with single gate structure, and method for manufacturing the same
US6787844B2 (en) 1995-09-29 2004-09-07 Nippon Steel Corporation Semiconductor device including transistor with composite gate structure and transistor with single gate structure, and method for manufacturing the same
US7759195B2 (en) 1995-09-29 2010-07-20 Katsuki Hazama Semiconductor device including transistor with composite gate structure and transistor with single gate structure, and method for manufacturing the same
US7452774B2 (en) 1995-09-29 2008-11-18 Pegre Semiconductors Llc Semiconductor device including transistor with composite gate structure and transistor with single gate structure, and method for manufacturing the same
US5925907A (en) * 1995-09-29 1999-07-20 Nippon Steel Corporaition Semiconductor device including transistor with composite gate structure and transistor with single gate structure
US7553724B2 (en) 2001-06-26 2009-06-30 Hynix Semiconductor Inc. Method for manufacturing code address memory cell by which a stack insulating film of an oxide film and a nitride film used as a dielectric film in a flash memory is used as a gate oxide film
JP2004274062A (en) * 2003-03-10 2004-09-30 Samsung Electronics Co Ltd Eeprom with selecting transistor and method of manufacturing the same
US7192820B2 (en) 2004-02-24 2007-03-20 Stmicroelectronics S.R.L. Method for reducing non-uniformity or topography variation between an array and circuitry in a process for manufacturing semiconductor integrated non-volatile memory devices
EP1569274A1 (en) 2004-02-24 2005-08-31 STMicroelectronics S.r.l. Process for manufacturing semiconductor integrated non volatile memory devices
JP2007207946A (en) * 2006-01-31 2007-08-16 Toshiba Corp Non-volatile semiconductor memory device
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US8153487B2 (en) 2006-01-31 2012-04-10 Kabushiki Kaisha Toshiba Semiconductor device and method for manufacturing the same
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