JPH08111395A - Formation of flattened insulating film - Google Patents
Formation of flattened insulating filmInfo
- Publication number
- JPH08111395A JPH08111395A JP6246051A JP24605194A JPH08111395A JP H08111395 A JPH08111395 A JP H08111395A JP 6246051 A JP6246051 A JP 6246051A JP 24605194 A JP24605194 A JP 24605194A JP H08111395 A JPH08111395 A JP H08111395A
- Authority
- JP
- Japan
- Prior art keywords
- silicon oxide
- polishing
- oxide film
- containing fluorine
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- Mechanical Treatment Of Semiconductor (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体装置の製造工程
において、凹凸形状を有するウエハの上面に平坦化絶縁
膜を形成する方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a flattening insulating film on the upper surface of a wafer having an uneven shape in a semiconductor device manufacturing process.
【０００２】[0002]
【従来の技術】半導体装置の製造工程で、配線パターン
や素子分離領域等によって凹凸形状が形成されたウエハ
の上面に平坦化絶縁膜を形成する場合には、例えば以下
のようにしている。先ず、凹凸形状を埋め込む状態で上
記ウエハの上面に酸化シリコン膜を成膜する。次に、化
学的機械研磨法（Chemical Mechanical Polishing ：Ｃ
ＭＰ）によって、上記酸化シリコン膜を研磨し当該酸化
シリコン膜の表面を平坦化する。この際、ｐＨ１０程度
に保たれた研磨液を研磨面に供給して研磨面上の研磨液
のｐＨを１０程度に保って研磨を行う。2. Description of the Related Art In the process of manufacturing a semiconductor device, a flattening insulating film is formed on the upper surface of a wafer having a concavo-convex shape formed by wiring patterns, element isolation regions, etc. First, a silicon oxide film is formed on the upper surface of the wafer in a state where the uneven shape is embedded. Next, chemical mechanical polishing (C)
The silicon oxide film is polished by MP) to flatten the surface of the silicon oxide film. At this time, the polishing liquid whose pH is maintained at about 10 is supplied to the polishing surface to perform polishing while maintaining the pH of the polishing liquid on the polishing surface at about 10.
【０００３】上記平坦化絶縁膜の形成方法では、研磨面
上の研磨液のｐＨを所定の値に保つことで、研磨速度を
確保した研磨が行われる。In the above-described method of forming the planarizing insulating film, the pH of the polishing liquid on the polishing surface is maintained at a predetermined value to perform polishing while ensuring the polishing rate.
【０００４】一方、素子構造の微細化の進展に伴い、今
後配線間容量が素子の動作速度を律速する要因になるこ
とが予測される。そこで、さらに素子構造の微細化を進
めていく上で半導体装置の高機能化を保つためには、配
線間に配置される平坦化絶縁膜として酸化シリコン膜よ
りも低誘電率の絶縁性材料を適用することによって上記
配線間容量を抑制する必要がある。このような絶縁性材
料として、フッ素を含む酸化シリコン膜が注目されてい
る。On the other hand, it is expected that the inter-wiring capacitance will become a factor that determines the operating speed of the device in the future with the progress of miniaturization of the device structure. Therefore, in order to maintain the high functionality of the semiconductor device in further miniaturization of the element structure, an insulating material having a dielectric constant lower than that of the silicon oxide film is used as the planarization insulating film arranged between the wirings. It is necessary to suppress the inter-wiring capacitance by applying it. As such an insulating material, attention has been paid to a silicon oxide film containing fluorine.
【０００５】[0005]
【発明が解決しようとする課題】しかし、上記平坦化絶
縁膜の形成方法には、以下のような課題があった。すな
わち、フッ素を含む酸化シリコン膜からなる平坦化絶縁
膜を上記の方法によって形成しようとすると、ＣＭＰに
よる研磨の際にフッ素を含む酸化シリコン膜から遊離し
たフッ素が研磨液中の水と反応してフッ酸が生成され
る。しかし、上記平坦化方法では、一定のｐＨの研磨液
を研磨面に供給してＣＭＰを行うため、上記のようにし
て研磨面でフッ酸が生成された場合には、研磨面上の研
磨液のｐＨが低下して研磨速度が低下する。However, the method for forming the planarizing insulating film has the following problems. That is, when an attempt is made to form a planarization insulating film made of a silicon oxide film containing fluorine by the above method, the fluorine released from the silicon oxide film containing fluorine reacts with water in the polishing liquid during polishing by CMP. Hydrofluoric acid is produced. However, in the above flattening method, since the polishing liquid having a constant pH is supplied to the polishing surface to perform CMP, when hydrofluoric acid is generated on the polishing surface as described above, the polishing liquid on the polishing surface is And the polishing rate decreases.
【０００６】そこで、本発明は、ＣＭＰの際に研磨速度
を確保しながらフッ素を含む酸化シリコン膜で構成され
る平坦化絶縁膜を形成する方法を提供し、これによっ
て、低誘電性材料からなる平坦化絶縁膜の形成を実現す
ることを目的とする。Therefore, the present invention provides a method for forming a planarizing insulating film composed of a silicon oxide film containing fluorine while securing a polishing rate during CMP, and thereby a low dielectric material is used. The purpose is to realize formation of a planarization insulating film.
【０００７】[0007]
【課題を解決するための手段】上記目的を達成するため
の本発明の平坦化絶縁膜の形成方法は、以下のように行
う。先ず、第１の平坦化絶縁膜の形成方法では、第１工
程で、凹凸形状を有するウエハの上面にフッ素を含む酸
化シリコン膜を成膜し、さらにこの上面に酸化シリコン
膜を成膜してフッ素を含む酸化シリコン膜上の凹凸形状
を埋め込む。次の第２工程で、化学的機械研磨法によっ
て上記酸化シリコン膜を研磨してその表面を平坦化す
る。The method for forming a planarization insulating film of the present invention for achieving the above object is performed as follows. First, in the first method for forming a planarization insulating film, in the first step, a silicon oxide film containing fluorine is formed on the upper surface of a wafer having an uneven shape, and a silicon oxide film is further formed on this upper surface. The uneven shape on the silicon oxide film containing fluorine is embedded. In the next second step, the silicon oxide film is polished by a chemical mechanical polishing method to flatten its surface.
【０００８】第２の平坦化絶縁膜の形成方法では、第２
工程の化学的機械研磨法によって、酸化シリコン膜と前
記フッ素を含む酸化シリコン膜とを研磨する。この際、
フッ素を含む酸化シリコン膜の削れ量に対応させながら
ｐＨを変化させた研磨液を供給することによって研磨面
上の研磨液のｐＨを所定の値に保って研磨を行う。In the second method of forming the planarizing insulating film, the second method is used.
The silicon oxide film and the silicon oxide film containing fluorine are polished by the chemical mechanical polishing method in the step. On this occasion,
By supplying the polishing liquid whose pH is changed in accordance with the scraped amount of the silicon oxide film containing fluorine, polishing is performed while keeping the pH of the polishing liquid on the polishing surface at a predetermined value.
【０００９】第３の平坦化絶縁膜の形成方法では、第１
工程で、凹凸形状を有するウエハの上面にフッ素を含む
酸化シリコン膜を成膜して上記凹凸形状を埋め込む。次
の第２工程では、上記第２の方法と同様の化学的機械研
磨法によって、上記フッ素を含む酸化シリコン膜を研磨
する。In the third method for forming the planarizing insulating film, the first method is used.
In the step, a silicon oxide film containing fluorine is formed on the upper surface of the uneven wafer to fill the uneven shape. In the next second step, the fluorine-containing silicon oxide film is polished by the chemical mechanical polishing method similar to the second method.
【００１０】[0010]
【作用】上記第１の方法では、フッ素を含む酸化シリコ
ン膜上の酸化シリコン膜を化学的機械研磨法によって研
磨することから、研磨の際には研磨面上の研磨液のｐＨ
は変化しない。このため、所定の研磨速度を保って研磨
が行われ、これによって、フッ素を含む酸化シリコン膜
の上面を酸化シリコン膜で覆った状態の平坦化絶縁膜が
ウエハ上に形成される。In the first method, the silicon oxide film on the silicon oxide film containing fluorine is polished by the chemical mechanical polishing method. Therefore, during polishing, the pH of the polishing liquid on the polishing surface is increased.
Does not change. Therefore, the polishing is performed at a predetermined polishing rate, whereby a planarization insulating film in which the upper surface of the silicon oxide film containing fluorine is covered with the silicon oxide film is formed on the wafer.
【００１１】上記第２の方法では、フッ素を含む酸化シ
リコン膜の削れ量に対応させてｐＨを変化させた研磨液
を研磨面に供給することによって研磨面上の研磨液のｐ
Ｈを所定の値に保ちながら酸化シリコン膜とフッ素を含
む酸化シリコン膜とを化学的機械研磨する。このことか
ら、所定の研磨速度を保って酸化シリコン膜とフッ素を
含む酸化シリコン膜との研磨が行われ、これによって、
ウエハ上には少なくともフッ素を含む酸化シリコン膜か
らなる平坦化絶縁膜が形成される。In the second method, the polishing liquid whose pH is changed according to the amount of abrasion of the silicon oxide film containing fluorine is supplied to the polishing surface so that the polishing liquid p on the polishing surface is p.
The silicon oxide film and the silicon oxide film containing fluorine are chemically mechanically polished while H is kept at a predetermined value. From this, polishing of the silicon oxide film and the silicon oxide film containing fluorine is performed while maintaining a predetermined polishing rate, and thereby,
A flattening insulating film made of a silicon oxide film containing at least fluorine is formed on the wafer.
【００１２】上記第３の方法では、ウエハ上に成膜した
フッ素を含む酸化シリコン膜を上記第２の方法と同様に
研磨する。このことから、所定の研磨速度を保ってフッ
素を含む酸化シリコン膜の研磨が行われ、これによっ
て、ウエハ上にはフッ素を含む酸化シリコン膜からなる
平坦化絶縁膜が形成される。In the third method, the silicon oxide film containing fluorine formed on the wafer is polished as in the second method. From this, the silicon oxide film containing fluorine is polished at a predetermined polishing rate, whereby a flattening insulating film made of a silicon oxide film containing fluorine is formed on the wafer.
【００１３】[0013]
【実施例】本発明の第１実施例を図１の断面模式図によ
り説明する。図１（１）に示すように、平坦化絶縁膜を
形成するウエハ１０は、例えば以下のように構成された
ものである。すなわち、Ｓｉ基板１１の上面には、酸化
シリコン膜１２が成膜されている。この酸化シリコン膜
１２の上面にはアルミニウムからなる配線１３がパター
ン形成されている。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described with reference to the schematic sectional view of FIG. As shown in FIG. 1A, the wafer 10 on which the planarizing insulating film is formed is configured as follows, for example. That is, the silicon oxide film 12 is formed on the upper surface of the Si substrate 11. A wiring 13 made of aluminum is patterned on the upper surface of the silicon oxide film 12.
【００１４】上記のように配線１３による凹凸形状が形
成されているウエハ１０の上面に平坦化絶縁膜を形成す
る場合には、以下のように行う。先ず、第１工程では、
ウエハ１０の上面にフッ素を含む酸化シリコン膜（以
下、ＳｉＯＦと記す）膜１５を成膜する。このＳｉＯＦ
膜１５は、例えば、バイアスＥＣＲ−ＣＶＤ装置を用い
て、配線１３間を埋め込みながら形成する。成膜条件
は、例えば以下のように設定する。成膜ガス及び流量：
シラン／酸素／６フッ化エタン＝４０／２０／１０ｓｃ
ｃｍ，成膜圧力：１Ｐａ，マイクロ波パワー：２．５ｋ
Ｗ，ＲＦバイアス（２ＭＨｚ）：１００Ｗ。When the flattening insulating film is formed on the upper surface of the wafer 10 on which the concavo-convex shape is formed by the wiring 13 as described above, the procedure is as follows. First, in the first step,
A silicon oxide film containing fluorine (hereinafter referred to as SiOF) film 15 is formed on the upper surface of the wafer 10. This SiOF
The film 15 is formed, for example, by using a bias ECR-CVD device while filling the space between the wirings 13. The film forming conditions are set as follows, for example. Deposition gas and flow rate:
Silane / oxygen / 6-ethane fluor = 40/20 / 10sc
cm, film forming pressure: 1 Pa, microwave power: 2.5 k
W, RF bias (2 MHz): 100 W.
【００１５】その後、上記ＳｉＯＦ膜１５の上面に、当
該ＳｉＯＦ膜１５上面の凹凸を埋め込む状態で酸化シリ
コン膜（以下、ＳｉＯ2 と記す）膜１６を成膜する。成
膜条件は例えば以下のように設定する。成膜ガス及び流
量：シラン／酸素＝４０／２０／１０ｓｃｃｍ，成膜圧
力：１Ｐａ，マイクロ波パワー：２．５ｋＷ。After that, a silicon oxide film (hereinafter referred to as SiO 2 ) film 16 is formed on the upper surface of the SiOF film 15 in a state where the unevenness on the upper surface of the SiOF film 15 is buried. The film forming conditions are set as follows, for example. Deposition gas and flow rate: silane / oxygen = 40/20/10 sccm, deposition pressure: 1 Pa, microwave power: 2.5 kW.
【００１６】次に、図１（２）に示す第２工程では、Ｃ
ＭＰ法によってＳｉＯ2 膜１６を研磨する。上記研磨液
は、コロイダルシリカと水酸化カリウムや水酸化アンモ
ニウム等のアルカリ溶液とを混合した研磨剤と水とで構
成する。そして、研磨条件は、例えば以下のように設定
する。加工圧力：１２０ｇ／ｃｍ2 ，テーブル回転数：
９０ｒｐｍ，砥粒：コロイダルシリカ，供給する研磨液
のｐＨ：１０，研磨液供給量：３ｍｌ／ｍｉｎ。ここで
は、ＳｉＯ2 膜１６の表面が平坦になるまで当該ＳｉＯ
2 膜１６を研磨する。これによって、ＳｉＯＦ膜１５と
その上面を覆うＳｉＯ2 膜１６とからなる平坦化絶縁膜
１７をウエハ１０上に形成する。Next, in the second step shown in FIG. 1B, C
The SiO 2 film 16 is polished by the MP method. The polishing liquid is composed of a polishing agent obtained by mixing colloidal silica with an alkaline solution such as potassium hydroxide or ammonium hydroxide, and water. Then, the polishing conditions are set as follows, for example. Processing pressure: 120 g / cm 2 , table rotation speed:
90 rpm, abrasive grains: colloidal silica, pH of polishing liquid to be supplied: 10, polishing liquid supply rate: 3 ml / min. Here, until the surface of the SiO 2 film 16 becomes flat,
2 The film 16 is polished. As a result, the flattening insulating film 17 including the SiOF film 15 and the SiO 2 film 16 covering the upper surface thereof is formed on the wafer 10.
【００１７】上記第１実施例では、ＳｉＯ2 膜１６のみ
を化学的機械研磨法によって研磨することから、研磨の
際には研磨面上の研磨液のｐＨの変化が防止されて所定
の研磨速度を保った研磨が行われる。このため、ＣＭＰ
の際には、良好な研磨特性が保たれ、平坦な研磨面が得
られる。In the first embodiment described above, since only the SiO 2 film 16 is polished by the chemical mechanical polishing method, the pH of the polishing liquid on the polishing surface is prevented from changing during polishing, and the polishing rate is set to a predetermined value. Is maintained. Therefore, CMP
In this case, good polishing characteristics are maintained and a flat polished surface is obtained.
【００１８】次に、第２実施例の平坦化絶縁膜の形成方
法を図２に基づいて説明する。平坦化絶縁膜を形成する
ウエハは、上記第１実施例で示したウエハ１０と同様に
構成されたものとする。Next, a method of forming the planarization insulating film of the second embodiment will be described with reference to FIG. The wafer on which the planarizing insulating film is formed is assumed to have the same structure as the wafer 10 shown in the first embodiment.
【００１９】先ず、図２（１）に示す第１工程では、ウ
エハ１０の上面に、ＳｉＯＦ膜２１を成膜し、この上面
にＳｉＯ2 膜２２を成膜する。これらのＳｉＯＦ膜２１
とＳｉＯ膜２２とは、ウエハ１０表面の凹凸形状よりも
ＳｉＯ膜２２の上面の方が高い位置になるように成膜す
る。それぞれの膜の成膜は、例えば上記第１実施例と同
様に行う。First, in a first step shown in FIG. 2A, a SiOF film 21 is formed on the upper surface of the wafer 10 and a SiO 2 film 22 is formed on the upper surface. These SiOF films 21
The SiO film 22 and the SiO film 22 are formed so that the upper surface of the SiO film 22 is higher than the uneven shape of the surface of the wafer 10. The respective films are formed, for example, in the same manner as in the first embodiment.
【００２０】次に、図２（２）に示す第２工程では、Ｃ
ＭＰ法によってＳｉＯ2 膜２２の上面から当該ＳｉＯ2
膜２２とＳｉＯＦ膜２１とを研磨面が平坦になるまで研
磨していく。この際、研磨面に供給する研磨液のｐＨ以
外の研磨条件は、上記第１実施例と同様に設定して研磨
を行う。Next, in the second step shown in FIG. 2B, C
MP method the SiO 2 from the upper surface of the SiO 2 film 22 by
The film 22 and the SiOF film 21 are polished until the polished surface becomes flat. At this time, the polishing conditions other than the pH of the polishing liquid supplied to the polishing surface are set in the same manner as in the first embodiment, and the polishing is performed.
【００２１】上記研磨液のｐＨは以下のように設定す
る。先ず、図３に示すように、研磨面がＳｉＯＦ膜（２
１）に達するまでは、研磨面に供給する研磨液のｐＨを
１０に保つ。その後、研磨面がＳｉＯＦ膜（２１）に達
して当該ＳｉＯＦ膜（２１）の研磨が始まってからは、
研磨面に供給する研磨液のｐＨをＳｉＯＦ膜（２１）の
削れ量に対応させて上昇させる。これによって、ＳｉＯ
Ｆ膜（２１）の研磨の際に当該ＳｉＯＦ膜（２１）から
遊離したフッ素と研磨液中の水とで生成されるフッ酸に
よって研磨面上の研磨液のｐＨが低下することを防止し
て、研磨面上の研磨液を例えばｐＨ１０に保ちながらＳ
ｉＯ2 膜（２２）及びＳｉＯＦ膜（２１）の研磨を行
う。The pH of the polishing liquid is set as follows. First, as shown in FIG. 3, the polished surface has a SiOF film (2
Until reaching 1), the pH of the polishing liquid supplied to the polishing surface is maintained at 10. After that, after the polished surface reaches the SiOF film (21) and polishing of the SiOF film (21) is started,
The pH of the polishing liquid supplied to the polishing surface is raised in accordance with the amount of abrasion of the SiOF film (21). This makes SiO
Preventing the pH of the polishing liquid on the polishing surface from being lowered by the hydrofluoric acid generated by the fluorine released from the SiOF film (21) and the water in the polishing liquid when the F film (21) is polished. , While keeping the polishing liquid on the polishing surface at pH 10, for example, S
The iO 2 film (22) and the SiOF film (21) are polished.
【００２２】ここでは、研磨面が平坦になるまでＳｉＯ
2 膜（２２）とＳｉＯＦ膜（２１）とを研磨する。これ
によって、ＳｉＯＦ膜（２１）とその上面のＳｉＯ2 膜
（２２）とからなる平坦化絶縁膜（２３）をウエハ（１
０）上に形成する。Here, SiO is used until the polished surface becomes flat.
The 2 film (22) and the SiOF film (21) are polished. As a result, the flattening insulating film (23) composed of the SiOF film (21) and the SiO 2 film (22) on the upper surface of the wafer (1
0) Form on top.
【００２３】上記第２実施例の平坦化絶縁膜の形成方法
では、研磨面上の研磨液を所定のｐＨに保って化学的機
械研磨を行うことから、所定の研磨速度を保った研磨が
行われる。このため、ＣＭＰの際には、良好な研磨特性
が保たれ、平坦な研磨面が得られる。In the method of forming the planarizing insulating film of the second embodiment, the chemical mechanical polishing is carried out while the polishing liquid on the polishing surface is kept at a predetermined pH, so that polishing is performed at a predetermined polishing rate. Be seen. Therefore, during CMP, good polishing characteristics are maintained and a flat polished surface is obtained.
【００２４】次に、第３実施例の平坦化絶縁膜の形成方
法を図４に基づいて説明する。平坦化絶縁膜を形成する
ウエハは、上記第１及び第２実施例で示したウエハ１０
と同様に構成されたものとする。Next, a method of forming the flattening insulating film of the third embodiment will be described with reference to FIG. The wafer on which the planarization insulating film is formed is the wafer 10 shown in the first and second embodiments.
It is assumed that it is configured in the same manner as.
【００２５】先ず、図４（１）に示す第１工程では、ウ
エハ１０の上面に、当該ウエハ１０表面の凹凸形状を埋
め込む状態でＳｉＯＦ膜４１を成膜する。ＳｉＯＦ膜４
１の成膜は、例えば上記第１実施例と同様に行う。First, in the first step shown in FIG. 4A, the SiOF film 41 is formed on the upper surface of the wafer 10 in a state where the uneven shape of the surface of the wafer 10 is embedded. SiOF film 4
The film formation of No. 1 is performed, for example, in the same manner as in the first embodiment.
【００２６】次に、図４（２）に示す第２工程では、Ｃ
ＭＰ法によってＳｉＯＦ膜４１をその表面が平坦になる
まで研磨していく。この際、研磨面に供給する研磨液の
ｐＨ以外の研磨条件は、上記第１実施例と同様に設定し
て研磨を行う。上記研磨面に供給する研磨液は、研磨面
上の研磨液のｐＨを１０に保つように、ＳｉＯＦ膜４１
の削れ量に対応させてｐＨを上昇させたものを供給す
る。Next, in the second step shown in FIG. 4B, C
The SiOF film 41 is polished by the MP method until its surface becomes flat. At this time, the polishing conditions other than the pH of the polishing liquid supplied to the polishing surface are set in the same manner as in the first embodiment, and the polishing is performed. The polishing liquid supplied to the polishing surface is the SiOF film 41 so that the pH of the polishing liquid on the polishing surface is maintained at 10.
The one whose pH is raised according to the scraped amount of is supplied.
【００２７】上記第３実施例の平坦化絶縁膜の形成方法
では、研磨面上の研磨液を所定のｐＨに保って化学的機
械研磨を行うことから、所定の研磨速度を保った研磨が
行われる。このため、ＣＭＰの際には、良好な研磨特性
が保たれ、平坦な研磨面が得られる。In the method of forming the planarization insulating film of the third embodiment, the chemical polishing is performed while keeping the polishing liquid on the polishing surface at a predetermined pH, so that polishing is performed at a predetermined polishing rate. Be seen. Therefore, during CMP, good polishing characteristics are maintained and a flat polished surface is obtained.
【００２８】[0028]
【発明の効果】以上、説明したように本発明の第１の平
坦化絶縁膜の形成方法によれば、フッ素を含む酸化シリ
コン膜上に成膜した酸化シリコン膜のみをＣＭＰ法によ
って研磨することで、所定の研磨速度を保った研磨を行
うことができるため、ウエハ上に低誘電性材料であるフ
ッ素を含む酸化シリコン膜からなる平坦化絶縁膜を形成
することが可能になる。また、本発明の第２及び第３の
平坦化絶縁膜の形成方法によれば、ＣＭＰの際にフッ素
を含む酸化シリコン膜の削れ量に対応させてｐＨを変化
させた研磨液を研磨面に供給して研磨面上の研磨液のｐ
Ｈを所定の値に保つことで、所定の研磨速度を保った研
磨を行うことができる。このため、ウエハ上に低誘電性
材料であるフッ素を含む酸化シリコン膜からなる平坦化
絶縁膜を形成することが可能になる。As described above, according to the first flattening insulating film forming method of the present invention, only the silicon oxide film formed on the silicon oxide film containing fluorine is polished by the CMP method. Since polishing can be performed at a predetermined polishing rate, it becomes possible to form a planarization insulating film made of a silicon oxide film containing fluorine, which is a low dielectric material, on the wafer. Further, according to the second and third methods of forming a planarization insulating film of the present invention, a polishing liquid whose pH is changed according to the amount of abrasion of the silicon oxide film containing fluorine during CMP is applied to the polishing surface. P of the polishing liquid supplied to the polishing surface
By maintaining H at a predetermined value, polishing can be performed at a predetermined polishing rate. Therefore, it becomes possible to form a flattening insulating film made of a silicon oxide film containing fluorine, which is a low dielectric material, on the wafer.
【図１】第１実施例を示す断面模式図である。FIG. 1 is a schematic sectional view showing a first embodiment.
【図２】第２実施例を示す断面模式図である。FIG. 2 is a schematic sectional view showing a second embodiment.
【図３】第２実施例を説明するグラフである。FIG. 3 is a graph illustrating a second example.
【図４】第３実施例を示す断面模式図である。FIG. 4 is a schematic sectional view showing a third embodiment.
１０ ウエハ １５，２１，４１ フッ素を含む酸化シリコン（ＳｉＯ
Ｆ）膜 １６，２２ 酸化シリコン（ＳｉＯ2 ）膜 １７，２３，４２ 平坦化絶縁膜10 Wafers 15, 21, 41 Silicon oxide containing fluorine (SiO 2
F) film 16,22 silicon oxide (SiO 2 ) film 17,23,42 flattening insulating film
Claims (3)
を含む酸化シリコン膜を成膜し、さらに当該フッ素を含
む酸化シリコン膜上に形成された凹凸形状を埋め込む状
態で酸化シリコン膜を成膜する第１工程と、 化学的機械研磨法によって前記酸化シリコン膜を研磨
し、当該酸化シリコン膜の表面を平坦化する第２工程と
を行うことを特徴とする平坦化絶縁膜の形成方法。1. A silicon oxide film containing fluorine is formed on an upper surface of a wafer having an uneven shape, and a silicon oxide film is further formed in a state where the uneven shape formed on the silicon oxide film containing fluorine is embedded. A method of forming a planarization insulating film, which comprises performing a first step and a second step of polishing the silicon oxide film by a chemical mechanical polishing method to planarize the surface of the silicon oxide film.
を含む酸化シリコン膜で覆い、さらに当該フッ素を含む
酸化シリコン膜上に少なくとも前記ウエハの凹凸形状よ
りも高く酸化シリコン膜を成膜する第１工程と、 前記フッ素を含む酸化シリコン膜の削れ量に対応させな
がらｐＨを変化させた研磨液を供給することによって研
磨面上の研磨液のｐＨを所定の値に保って前記酸化シリ
コン膜と前記フッ素を含む酸化シリコン膜とを化学的機
械研磨し、前記研磨面を平坦化する第２工程とを行うこ
とを特徴とする平坦化絶縁膜の形成方法。2. A first step of covering the upper surface of a wafer having an uneven shape with a silicon oxide film containing fluorine, and forming a silicon oxide film on the silicon oxide film containing fluorine at least higher than the uneven shape of the wafer. And a step of supplying a polishing liquid whose pH is changed in accordance with the scraped amount of the silicon oxide film containing fluorine to keep the pH of the polishing liquid on the polishing surface at a predetermined value. A method of forming a planarization insulating film, which comprises performing a chemical mechanical polishing on a silicon oxide film containing fluorine and planarizing the polished surface.
凸形状を埋め込む状態でフッ素を含む酸化シリコン膜を
成膜する第１工程と、 前記フッ素を含む酸化シリコン膜の削れ量に対応させな
がらｐＨを変化させた研磨液を供給することによって研
磨面上の研磨液のｐＨを所定の値に保って前記フッ素を
含む酸化シリコン膜を化学的機械研磨し、当該フッ素を
含む酸化シリコン膜の表面を平坦化する第２工程とを行
うことを特徴とする平坦化絶縁膜の形成方法。3. A first step of forming a silicon oxide film containing fluorine in a state of embedding the uneven shape on an upper surface of a wafer having an uneven shape, and a pH corresponding to a scraped amount of the silicon oxide film containing fluorine. Is supplied to the surface of the silicon oxide film containing fluorine to chemically and mechanically polish the surface of the silicon oxide film containing fluorine while maintaining the pH of the polishing liquid on the polishing surface at a predetermined value. A method of forming a planarizing insulating film, which comprises performing a second step of planarizing.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24605194A JP3297787B2 (en) | 1994-10-12 | 1994-10-12 | Method for forming planarizing insulating film |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24605194A JP3297787B2 (en) | 1994-10-12 | 1994-10-12 | Method for forming planarizing insulating film |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH08111395A true JPH08111395A (en) | 1996-04-30 |
| JP3297787B2 JP3297787B2 (en) | 2002-07-02 |
Family
ID=17142739
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP24605194A Expired - Fee Related JP3297787B2 (en) | 1994-10-12 | 1994-10-12 | Method for forming planarizing insulating film |
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| Country | Link |
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| JP (1) | JP3297787B2 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1024526A1 (en) * | 1999-01-26 | 2000-08-02 | Lucent Technologies Inc. | An integrated circuit device having a planar interlevel dielectric layer |
| JP2002252280A (en) * | 2001-02-26 | 2002-09-06 | Mitsubishi Electric Corp | Semiconductor device and manufacturing method thereof |
| JP2014183221A (en) * | 2013-03-19 | 2014-09-29 | Toshiba Corp | Method of manufacturing semiconductor device |
-
1994
- 1994-10-12 JP JP24605194A patent/JP3297787B2/en not_active Expired - Fee Related
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1024526A1 (en) * | 1999-01-26 | 2000-08-02 | Lucent Technologies Inc. | An integrated circuit device having a planar interlevel dielectric layer |
| US6274933B1 (en) | 1999-01-26 | 2001-08-14 | Agere Systems Guardian Corp. | Integrated circuit device having a planar interlevel dielectric layer |
| JP2002252280A (en) * | 2001-02-26 | 2002-09-06 | Mitsubishi Electric Corp | Semiconductor device and manufacturing method thereof |
| JP2014183221A (en) * | 2013-03-19 | 2014-09-29 | Toshiba Corp | Method of manufacturing semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3297787B2 (en) | 2002-07-02 |
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