JPH0792977B2 - Playback device - Google Patents
Playback deviceInfo
- Publication number
- JPH0792977B2 JPH0792977B2 JP62199874A JP19987487A JPH0792977B2 JP H0792977 B2 JPH0792977 B2 JP H0792977B2 JP 62199874 A JP62199874 A JP 62199874A JP 19987487 A JP19987487 A JP 19987487A JP H0792977 B2 JPH0792977 B2 JP H0792977B2
- Authority
- JP
- Japan
- Prior art keywords
- transistor
- switch
- capacitor
- recording
- time
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B19/00—Driving, starting, stopping record carriers not specifically of filamentary or web form, or of supports therefor; Control thereof; Control of operating function ; Driving both disc and head
- G11B19/02—Control of operating function, e.g. switching from recording to reproducing
Landscapes
- Signal Processing For Digital Recording And Reproducing (AREA)
- Signal Processing Not Specific To The Method Of Recording And Reproducing (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は再生装置に係り、特に記録と再生とを切換える
再生装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a reproducing apparatus, and more particularly to a reproducing apparatus that switches between recording and reproducing.
従来の装置は、例えば特開昭61-9807号に記載されてい
るような装置がある。A conventional device is, for example, a device described in JP-A-61-9807.
この従来装置を例示する第２図において、Ｑ1〜Ｑ7はNP
Nトランジスタ、Ｒ1〜Ｒ6は抵抗、Ｃ1は容量、Ｔ1は正
側電源端子、Ｔ2は負側電源端子、Ｔ3は入力端子、Ｔ4
は出力端子、Ｓ1はスイッチである。In FIG. 2 illustrating this conventional device, Q 1 to Q 7 are NPs.
N transistors, R 1 to R 6 are resistors, C 1 is a capacitor, T 1 is a positive power supply terminal, T 2 is a negative power supply terminal, T 3 is an input terminal, T 4
Is an output terminal, and S 1 is a switch.
第２図において、スイッチＳ1は再生時には閉じ、記録
時には開く。再生時には、入力信号は入力端子Ｔ3より
トランジスタＱ5のベースに供給される。トランジスタ
Ｑ4とＱ5はカスコード接続であり、トランジスタＱ4の
ベースにはトランジスタＱ1,Q2,Q3および抵抗Ｒ1により
構成されるバイアス回路からバイアスが与えられる。ト
ランジスタＱ6,Q7，抵抗Ｒ3〜Ｒ5はレベルシフト回路を
構成する。トランジスタＱ4のコレクタには抵抗Ｒ2およ
びトランジスタＱ6のベースが接続され、出力信号はト
ランジスタＱ6のエミッタから出力端子Ｔ4に出力され
る。また、トランジスタＱ6のエミッタには抵抗Ｒ3およ
びＲ4が接続されており、さらにＲ4を経てトランジスタ
Ｑ7のベースが接続されている。トランジスタＱ7のエミ
ッタから出力される出力信号は抵抗Ｒ6を経てトランジ
スタＱ5のベースに供給されフィードバックダンピング
を行う。In FIG. 2, the switch S 1 is closed during reproduction and opened during recording. During reproduction, the input signal is supplied from the input terminal T 3 to the base of the transistor Q 5 . The transistors Q 4 and Q 5 are cascode-connected, and the base of the transistor Q 4 is biased by a bias circuit composed of the transistors Q 1 , Q 2 , Q 3 and the resistor R 1 . Transistors Q 6, Q 7, the resistor R 3 to R 5 constitute a level shift circuit. The resistor R 2 and the base of the transistor Q 6 are connected to the collector of the transistor Q 4 , and the output signal is output from the emitter of the transistor Q 6 to the output terminal T 4 . Further, the resistors R 3 and R 4 are connected to the emitter of the transistor Q 6 , and the base of the transistor Q 7 is further connected via R 4 . The output signal output from the emitter of the transistor Q 7 is supplied to the base of the transistor Q 5 via the resistor R 6 to perform feedback damping.
このような再生装置によれば、ヘッドからの微弱な再生
信号を増幅できるという特徴がある。According to such a reproducing apparatus, a weak reproducing signal from the head can be amplified.
上記従来技術は、記録再生切換時の整定時間について配
慮がされていなかった。すなわち、第２図において、記
録時にはスイッチＳ1は開いており、トランジスタＱ5に
は電流は流れない。このため、トランジスタＱ6のベー
ス電位は上がるのでトランジスタＱ7のエミッタ電位は
上がり、容量Ｃ1は充電される。The above-mentioned prior art does not consider the settling time when switching between recording and reproduction. That is, in FIG. 2, the switch S 1 is open during recording and no current flows through the transistor Q 5 . Therefore, the base potential of the transistor Q 6 rises, the emitter potential of the transistor Q 7 rises, and the capacitance C 1 is charged.
スイッチＳ1を閉じて記録から再生に切換えた場合に
は、トランジスタＱ5に電流が流れ、トランジスタＱ6の
ベース電位は下がるために、トランジスタＱ7のエミッ
タ電位は下がり、容量Ｃ1は放電し、定常状態へ至る。When the switch S 1 is closed to switch from recording to reproduction, a current flows through the transistor Q 5 and the base potential of the transistor Q 6 drops, so that the emitter potential of the transistor Q 7 drops and the capacitance C 1 is discharged. , To a steady state.
このような記録から再生に切換えた場合の容量Ｃ1の放
電に伴う出力端子に現われる過渡応答ｖ0は と表わされる。ただし、Ａは定数、τは時定数、ｔは時
間である。このため、過渡応答ｖ0が再生信号の出力レ
ベルに対して十分小さくなるまでの期間再生信号が得ら
れないという問題があった。The transient response v 0 appearing at the output terminal due to discharge of the capacitance C 1 when switching from recording to reproduction is Is represented. However, A is a constant, τ is a time constant, and t is time. Therefore, there is a problem that the reproduced signal cannot be obtained during the period until the transient response v 0 becomes sufficiently smaller than the output level of the reproduced signal.
本発明の目的は、記録から再生に切換えた場合の容量Ｃ
1の放電に伴う過渡応答時間を短縮した再生装置を提供
することにある。An object of the present invention is to provide a capacity C when switching from recording to reproduction.
An object of the present invention is to provide a reproducing device in which the transient response time associated with discharge of 1 is shortened.
上記目的は、抵抗Ｒ6と容量Ｃ1との間にスイッチを設
け、再生時には上記スイッチにより抵抗Ｒ6と容量Ｃ1を
接続し、記録時には上記スイッチにより第２のバイアス
回路と容量Ｃ1を接続することにより達成される。For the above purpose, a switch is provided between the resistor R 6 and the capacitor C 1 , the resistor R 6 and the capacitor C 1 are connected by the switch at the time of reproduction, and the second bias circuit and the capacitor C 1 are connected by the switch at the time of recording. It is achieved by connecting.
上記バイアス回路は、記録時に容量Ｃ1の両端間の電圧
が再生時とほぼ同電圧になるようなバイアスを上記スイ
ッチを経て容量Ｃ1に与える。それによって記録再生切
換時の容量Ｃ1の充放電を小さくすることができるの
で、再生アンプの整定時間を短縮することができる。The bias circuit gives a bias to the capacitor C 1 via the switch so that the voltage across the capacitor C 1 at the time of recording becomes substantially the same as the voltage at the time of reproducing. As a result, the charging / discharging of the capacity C 1 at the time of recording / reproducing switching can be reduced, so that the settling time of the reproducing amplifier can be shortened.
以下、本発明の一実施例を第１図により説明する。第１
図においてＱ1〜Ｑ7はNPNトランジスタ、Ｒ1〜Ｒ7は抵
抗、Ｃ1は容量、Ｔ1は正側電源端子、Ｔ2は負側電源端
子、Ｔ3は入力端子、Ｔ4は出力端子、Ｓ1およびＳ2はス
イッチである。An embodiment of the present invention will be described below with reference to FIG. First
Q 1 to Q 7 are NPN transistors in FIG, R 1 to R 7 are resistors, C 1 is the capacitance, T 1 is the positive power supply terminal, T 2 is the negative power supply terminal, T 3 denotes an input terminal, T 4 output The terminals, S 1 and S 2, are switches.
本実施例は、上述した第２図に示す従来回路に電圧源Ｖ
1と抵抗Ｒ7とから成る第２のバイアス回路と、スイッチ
Ｓ2を設けたものである。In this embodiment, the voltage source V is added to the conventional circuit shown in FIG.
A second bias circuit composed of 1 and a resistor R 7 and a switch S 2 are provided.
本実施例では、再生時にはスイッチＳ1を閉じ、さらに
スイッチＳ2を抵抗Ｒ6側へ接続する。再生時の動作は、
上述した第２図に示す従来回路の動作と同様である。In this embodiment, the switch S 1 is closed during reproduction, and the switch S 2 is connected to the resistor R 6 side. The operation during playback is
The operation is similar to that of the conventional circuit shown in FIG.
記録時には、スイッチＳ1を開き、さらにスイッチＳ2を
抵抗Ｒ7へ接続する。この場合、トランジスタＱ7エミッ
タ電位は再生時の電位より上がるが、容量Ｃ1には電圧
源Ｖ1より抵抗Ｒ7、スイッチＳ2を経て再生時とほぼ同
一なバイアスが与えられるので、容量Ｃ1への充電を軽
減できる。During recording, the switch S 1 is opened and the switch S 2 is connected to the resistor R 7 . In this case, the potential of the emitter of the transistor Q 7 rises above the potential at the time of reproduction, but the capacitance C 1 is given a bias almost the same as that at the time of reproduction via the resistor R 7 and the switch S 2 from the voltage source V 1. The charge to 1 can be reduced.
このように本実施例では、記録再生切換時の容量Ｃ1の
充放電を軽減できるので、記録再生切換時の再生装置の
整定時間を短縮できるという効果がある。As described above, in the present embodiment, since the charging / discharging of the capacity C 1 at the time of switching the recording / reproducing can be reduced, there is an effect that the settling time of the reproducing device at the time of switching the recording / reproducing can be shortened.
次に本発明の他の実施例を第３図により説明する。第３
図においてＱ8〜Ｑ12はNPNトランジスタ、Ｒ7は抵抗を
示し、他の第１図と同一符号のものは同一機能を示す。Next, another embodiment of the present invention will be described with reference to FIG. Third
In the figure, Q 8 to Q 12 are NPN transistors, R 7 is a resistor, and the same symbols as those in FIG. 1 indicate the same functions.
本実施例では、記録時にはスイッチＳ1は開き、再生時
にはスイッチＳ1は閉じる。トランジスタＱ8のベースは
トランジスタＱ1のベースおよびコレクタに接続されて
いるので、スイッチＳ1が閉じたときにはトランジスタ
Ｑ8不活性状態にあり電流は流れない。スイッチＳ1を開
いたときにはトランジスタＱ1には電流は流れず、抵抗
Ｒ1によりトランジスタＱ8のベースにバイアスが与えら
れるので、トランジスタＱ8は活性状態となり電流が流
れ、トランジスタＱ5のベース電位をスイッチＳ1を閉じ
た場合と同電位にできる。In this embodiment, the switch S 1 is opened during recording and the switch S 1 is closed during reproduction. Since the base of the transistor Q 8 is connected to the base and collector of the transistor Q 1 , when the switch S 1 is closed, the transistor Q 8 is inactive and no current flows. When you open the switch S 1 is no current flows through the transistor Q 1, the bias is applied to the base of the transistor Q 8 by the resistance R 1, the transistor Q 8 flows a current becomes active, the base potential of the transistor Q 5 Can be made to have the same potential as when the switch S 1 is closed.
このように本実施例では、記録再生切換時の容量Ｃ1の
充放電を軽減できるので、記録再生切換時の再生装置の
整定時間を短縮できるという効果がある。As described above, in the present embodiment, since the charging / discharging of the capacity C 1 at the time of switching the recording / reproducing can be reduced, there is an effect that the settling time of the reproducing device at the time of switching the recording / reproducing can be shortened.
本発明によれば、記録時にもロータリトランスに接続す
る容量の両端の電圧を再生時とほぼ同電位にすることが
できるので記録再生切換時の再生装置の整定時間を短縮
できるという効果がある。According to the present invention, the voltage across the capacitor connected to the rotary transformer can be made to have substantially the same potential as that at the time of recording even at the time of recording, so that there is an effect that the settling time of the reproducing device at the time of recording / reproducing switching can be shortened.
第１図は本発明一実施例を示す再生装置の回路図、第２
図は従来の再生装置の回路図、第３図は本発明の他の実
施例を示す再生装置の回路図である。 Ｑ1〜Ｑ12……トランジスタ、Ｒ1〜Ｒ7……抵抗、Ｃ1…
…容量、Ｓ1,S2……スイッチ、Ｖ1……電圧源、Ｔ1……
正側電源端子、Ｔ2……負側電源端子、Ｔ3……入力端
子、Ｔ4……出力端子。FIG. 1 is a circuit diagram of a reproducing apparatus showing an embodiment of the present invention, and FIG.
FIG. 3 is a circuit diagram of a conventional reproducing apparatus, and FIG. 3 is a circuit diagram of a reproducing apparatus showing another embodiment of the present invention. Q 1 ~Q 12 ...... transistor, R 1 ~R 7 ...... resistance, C 1 ...
… Capacity, S 1 , S 2 …… Switch, V 1 …… Voltage source, T 1 ……
Positive side power supply terminal, T 2 ... Negative side power supply terminal, T 3 ... input terminal, T 4 ... output terminal.
───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 昭59−114676（ＪＰ，Ａ) 特開 平３−5255（ＪＰ，Ａ) 特開 昭59−203203（ＪＰ，Ａ) ─────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP 59-114676 (JP, A) JP 3-5255 (JP, A) JP 59-203203 (JP, A)
Claims (1)
ランジスタと、この第１のトランジスタ（Q5）と負側電
源端子間に接続された第１のスイッチと、上記第１のト
ランジスタと入力端子間に接続された第１の容量と、上
記第２のトランジスタ（Q4）のベースに接続された第１
のバイアス回路と、上記第２のトランジスタのコレクタ
と正側電源端子間に接続された負荷抵抗と、上記第２の
トランジスタのコレクタに接続されたレベルシフト回路
と、上記レベルシフト回路の出力端子と上記第１のトラ
ンジスタ間に接続されたフィードバック抵抗とを有する
再生装置において、上記第２のトランジスタのコレクタ
と上記負側電源端子間に第２のバイアス回路を設け、上
記第１のスイッチが閉じた場合には上記第１のバイアス
回路により上記第1,第２のトランジスタをオンして上記
負荷抵抗に電流を流し、上記第１スイッチが開いた場合
には上記第1,第２のトランジスタをオフし上記第２のバ
イアス回路を起動して上記負荷抵抗に電流を流し、上記
第１のスイッチが閉じた場合の上記負荷抵抗の電圧降下
と等しくして、上記第１の容量の両端に加わる電圧を制
御することを特徴とする再生装置。1. A cascode-connected first and second transistor, a first switch connected between the first transistor (Q5) and a negative power supply terminal, the first transistor and an input terminal. A first capacitor connected between the first capacitor and a first capacitor connected to the base of the second transistor (Q4).
A bias circuit, a load resistor connected between the collector of the second transistor and the positive power supply terminal, a level shift circuit connected to the collector of the second transistor, and an output terminal of the level shift circuit. In a reproducing device having a feedback resistor connected between the first transistors, a second bias circuit is provided between the collector of the second transistor and the negative power supply terminal, and the first switch is closed. In this case, the first bias circuit turns on the first and second transistors to allow a current to flow through the load resistor, and when the first switch opens, the first and second transistors are turned off. Then, the second bias circuit is started to cause a current to flow through the load resistor, and the voltage drop of the load resistor when the first switch is closed is made equal to A reproducing device characterized by controlling a voltage applied to both ends of the first capacitor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62199874A JPH0792977B2 (en) | 1987-08-12 | 1987-08-12 | Playback device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62199874A JPH0792977B2 (en) | 1987-08-12 | 1987-08-12 | Playback device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6443866A JPS6443866A (en) | 1989-02-16 |
| JPH0792977B2 true JPH0792977B2 (en) | 1995-10-09 |
Family
ID=16415060
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62199874A Expired - Fee Related JPH0792977B2 (en) | 1987-08-12 | 1987-08-12 | Playback device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0792977B2 (en) |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59203203A (en) * | 1983-05-06 | 1984-11-17 | Nippon Kogaku Kk <Nikon> | Signal processing circuit capable of saving electric power |
-
1987
- 1987-08-12 JP JP62199874A patent/JPH0792977B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6443866A (en) | 1989-02-16 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |