JPH0783163B2 - Element wiring electrode and manufacturing method thereof - Google Patents

Element wiring electrode and manufacturing method thereof

Info

Publication number
JPH0783163B2
JPH0783163B2 JP62118395A JP11839587A JPH0783163B2 JP H0783163 B2 JPH0783163 B2 JP H0783163B2 JP 62118395 A JP62118395 A JP 62118395A JP 11839587 A JP11839587 A JP 11839587A JP H0783163 B2 JPH0783163 B2 JP H0783163B2
Authority
JP
Japan
Prior art keywords
layer
wiring electrode
element wiring
manufacturing
glass substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP62118395A
Other languages
Japanese (ja)
Other versions
JPS63282780A (en
Inventor
扶美江 山中
隆 榎本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Canon Inc
Original Assignee
Canon Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Canon Inc filed Critical Canon Inc
Priority to JP62118395A priority Critical patent/JPH0783163B2/en
Priority to US07/193,060 priority patent/US4859036A/en
Publication of JPS63282780A publication Critical patent/JPS63282780A/en
Publication of JPH0783163B2 publication Critical patent/JPH0783163B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

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  • Electrochromic Elements, Electrophoresis, Or Variable Reflection Or Absorption Elements (AREA)
  • Parts Printed On Printed Circuit Boards (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Manufacturing Of Printed Circuit Boards (AREA)

Description

【発明の詳細な説明】 [産業上の利用分野] 本発明は、ホトリソグラフィー技術を用いて製造される
2層構造の素子配線電極及びその製造方法に関する。
TECHNICAL FIELD The present invention relates to a device wiring electrode having a two-layer structure manufactured by using a photolithography technique and a manufacturing method thereof.

[従来の技術] 従来、素子配線電極はAl,Cr,Mo,Ta等の単体金属を形成
させたガラスまたはウェハー基板上に、レジストを塗布
し、露光、現像、エッチングすることにより形成されて
いた。
[Prior Art] Conventionally, element wiring electrodes have been formed by coating a resist on a glass or wafer substrate on which a single metal such as Al, Cr, Mo, and Ta has been formed, and exposing, developing, and etching. .

しかしながら、単体金属、例えば、Alを用いると電極下
地基板と形成された配線電極との密着性が問題となった
り、あるいは電極を形成するために使用する単体金属、
例えば、Moとレジストとの密着性が悪く、良好なパター
ンニングを行うことができない場合があった。
However, when a single metal, for example, Al is used, the adhesion between the electrode base substrate and the formed wiring electrode becomes a problem, or a single metal used to form the electrode,
For example, the adhesion between Mo and the resist was poor, and good patterning could not be performed in some cases.

また、両者の問題を解決する単体金属種がある場合で
も、所望の抵抗値を満足するものが得られない欠点があ
った。
Further, even if there is a simple metal species that solves both problems, there is a drawback that a material satisfying a desired resistance value cannot be obtained.

[発明が解決しようとする問題点] 本発明は、この様な従来技術の欠点を改良するためにな
されたものであり、電極を形成する金属と下地のガラス
基板との密着性を良好にし、さらにレジストと電極を形
成する金属との密着性を向上させた金属の2層構造の素
子配線電極及びその製造方法を提供することを目的とす
るものである。
[Problems to be Solved by the Invention] The present invention has been made in order to improve such drawbacks of the prior art, and improves the adhesion between the metal forming the electrode and the underlying glass substrate, Further, it is an object of the present invention to provide an element wiring electrode having a two-layer structure of metal, in which the adhesion between the resist and the metal forming the electrode is improved, and a manufacturing method thereof.

[問題点が解決するための手段] 即ち、本発明の第一の発明は、ガラス基板上に積層され
た金属の2層構造からなる配線電極であって、前記2層
構造のうち前記ガラス基板と直接接する層がMoを材料と
し、前記Mo材料層の上に形成された、ガラス基板と直接
接しない層がAlを材料とすることを特徴とする素子配線
電極である。
[Means for Solving the Problems] That is, the first invention of the present invention is a wiring electrode having a two-layer structure of a metal laminated on a glass substrate, wherein the glass substrate is one of the two-layer structure. The element wiring electrode is characterized in that the layer in direct contact with is made of Mo, and the layer formed on the Mo material layer and not in direct contact with the glass substrate is made of Al.

また、第二の発明は、素子配線電極の製造方法であっ
て、ガラス基板上にMo層を形成する第1の工程と、前記
Mo層上にAlの層を積層する第2の工程と、前記Al層およ
びMo層を同一のエッチング液を用いて同時にパターニン
グ処理する第三の工程を有することを特徴とする素子配
線電極の製造方法である。
A second invention is a method for manufacturing an element wiring electrode, which comprises a first step of forming a Mo layer on a glass substrate, and
Manufacture of an element wiring electrode, characterized by having a second step of laminating an Al layer on a Mo layer and a third step of simultaneously patterning the Al layer and the Mo layer using the same etching solution. Is the way.

〔作用〕[Action]

本発明の素子配線電極は、ガラス基板上に第1層目のMo
層を形成し、その上に第2層目のAlの層を積層し、次い
で第1層目および第2層目の各層を同じエッチング液を
使用して同時にパターニングすることにより製造される
ので、レジストとの密着性が良好なAlを上層の第2層に
用いているので、パターニング中にレジストが剥離する
ことがなく、また第1層と第2層を同時にエッチングす
るので工程を簡略化できると共に正確なパターンを有す
るAlを第2層とした金属の2層構造からなる素子配線電
極を得ることができる。
The element wiring electrode of the present invention comprises a glass substrate on which Mo of the first layer is formed.
Since it is manufactured by forming a layer, laminating a second layer of Al on the layer, and then simultaneously patterning the first layer and the second layer using the same etching solution, Since Al, which has good adhesiveness to the resist, is used for the second upper layer, the resist does not peel off during patterning, and the first and second layers are simultaneously etched, which simplifies the process. At the same time, it is possible to obtain an element wiring electrode having a two-layer structure of metal having an accurate pattern of Al as the second layer.

[実施例] 以下、前記の目的を達成する一実施例として、液晶表示
装置に関して、第1図を用いて本発明をさらに具体的に
説明する。
[Embodiment] As one embodiment for achieving the above-mentioned object, the present invention will be described in more detail below with reference to FIG. 1 for a liquid crystal display device.

第1図(a)〜(e)は本発明に係る液晶表示装置の素
子配線電極の製造方法を示す工程図である。同第1図に
おいて、本発明の素子配線電極の製造方法は、まずガラ
ス基板1上に、第1層目の金属であるMo単体のMo薄膜2
を厚さ3000Åに形成させる。(第1図(a)参照) 次いで、第2層目のAl単体のAl薄膜3を厚さ300Åに形
成させる。(第1図(b)参照 この上にフォトレジスト4を塗布し、露光、現像を行っ
て電極配線パターンをパターニングする。(第1図
(c)参照) 次に、この基板を酢酸・リン酸・硝酸の混合液(38H3PO
4:15HNO3:3OCH3COOH:75H2O)のエッチング液5に浸漬
し、MoおよびAlを一度に同時にエッチングする。(第1
図(d)参照) その後、水洗、レジスト剥離を行って素子配線電極を得
る。(第1図(e)参照) この様にして素子配線電極を製造することにより、Mo単
体のみを用いて配線電極を形成するときに生ずる現像お
よびエッチング中におけるレジストのはがれを、Alがレ
ジストと接触することにより防止することができる。
1 (a) to 1 (e) are process diagrams showing a method for manufacturing an element wiring electrode of a liquid crystal display device according to the present invention. Referring to FIG. 1, a method for manufacturing an element wiring electrode according to the present invention is as follows.
Is formed to a thickness of 3000Å. (See FIG. 1 (a)) Next, an Al thin film 3 of a simple second layer of Al is formed to a thickness of 300Å. (See FIG. 1 (b)) A photoresist 4 is applied on this, and exposure and development are performed to pattern an electrode wiring pattern. (See FIG. 1 (c)) Next, this substrate is subjected to acetic acid / phosphoric acid.・ Nitric acid mixture (38H 3 PO
4 : 15HNO 3 : 3OCH 3 COOH: 75H 2 O), and Mo and Al are simultaneously etched at the same time. (First
After that, the device wiring electrode is obtained by washing with water and removing the resist. (Refer to FIG. 1 (e)) By manufacturing the element wiring electrode in this manner, the peeling of the resist during the development and etching that occurs when the wiring electrode is formed using only Mo alone, and the Al It can be prevented by contact.

また、Mo単体はガラス基板との密着性が良好で、所望の
抵抗値を満足することができる。
Further, Mo alone has good adhesion to the glass substrate and can satisfy a desired resistance value.

本発明において、エッチング液としては38H3PO4:15HN
O3:3OCH3COOH:75H2Oを用いることが好ましい。
In the present invention, the etching liquid is 38H 3 PO 4 : 15HN
It is preferable to use O 3 : 3OCH 3 COOH: 75H 2 O.

また、第1層目の金属としては、ガラス基板との密着性
が良好な金属が用いられ、例えばMoの単体金属が挙げら
れる。
Further, as the metal of the first layer, a metal having good adhesion to the glass substrate is used, and for example, a single metal of Mo can be mentioned.

[発明の効果] 本発明により、Mo単体のみを用いて素子配線電極を形成
するときに発生する現象およびエッチング中のレジスト
のはがれを、Alがレジストと接触することにより防止す
ることができ、製品の歩留りが大きく向上する。
[Effects of the Invention] According to the present invention, it is possible to prevent the phenomenon that occurs when forming a device wiring electrode using only Mo and peeling of the resist during etching by contacting Al with the product. The yield will be greatly improved.

さらに、2種の異った金属を用いているにもかかわら
ず、エッチング工程は一工程で行うことができ、工程の
簡略化を計ることができる。
Furthermore, the etching process can be performed in one step, even though two different metals are used, and the process can be simplified.

【図面の簡単な説明】[Brief description of drawings]

第1図(a)〜(e)は本発明に係る液晶表示装置の素
子配線電極の製造方法を示す工程図である。 1……ガラス基板、2……Mo薄膜 3……Al薄膜、4……フォトレジスト 5……エッチング液
1 (a) to 1 (e) are process diagrams showing a method for manufacturing an element wiring electrode of a liquid crystal display device according to the present invention. 1 ... Glass substrate, 2 ... Mo thin film 3 ... Al thin film, 4 ... Photoresist 5 ... Etching liquid

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】ガラス基板上に積層された金属の2層構造
からなる配線電極であって、前記2層構造のうち前記ガ
ラス基板と直接接する層がMoを材料とし、前記Mo材料層
の上に形成された、ガラス基板と直接接しない層がAlを
材料とすることを特徴とする素子配線電極。
1. A wiring electrode having a two-layer structure of metal laminated on a glass substrate, wherein a layer of the two-layer structure that is in direct contact with the glass substrate is made of Mo, and is on the Mo material layer. An element wiring electrode, characterized in that the layer formed on the substrate which is not in direct contact with the glass substrate is made of Al.
【請求項2】素子配線電極の製造方法であって、ガラス
基板上にMo層を形成する第1の工程と、前記Mo層上にAl
の層を積層する第2の工程と、前記Al層およびMo層を同
一のエッチング液を用いて同時にパターニング処理する
第三の工程を有することを特徴とする素子配線電極の製
造方法。
2. A method for manufacturing an element wiring electrode, comprising a first step of forming a Mo layer on a glass substrate and Al on the Mo layer.
And a third step of patterning the Al layer and the Mo layer at the same time by using the same etching solution.
JP62118395A 1987-05-15 1987-05-15 Element wiring electrode and manufacturing method thereof Expired - Lifetime JPH0783163B2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP62118395A JPH0783163B2 (en) 1987-05-15 1987-05-15 Element wiring electrode and manufacturing method thereof
US07/193,060 US4859036A (en) 1987-05-15 1988-05-12 Device plate having conductive films selected to prevent pin-holes

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62118395A JPH0783163B2 (en) 1987-05-15 1987-05-15 Element wiring electrode and manufacturing method thereof

Publications (2)

Publication Number Publication Date
JPS63282780A JPS63282780A (en) 1988-11-18
JPH0783163B2 true JPH0783163B2 (en) 1995-09-06

Family

ID=14735610

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62118395A Expired - Lifetime JPH0783163B2 (en) 1987-05-15 1987-05-15 Element wiring electrode and manufacturing method thereof

Country Status (1)

Country Link
JP (1) JPH0783163B2 (en)

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56114220A (en) * 1980-02-14 1981-09-08 Fujitsu Ltd Conductive metal material
JPS6055961B2 (en) * 1980-04-14 1985-12-07 松下電器産業株式会社 Method for manufacturing alumina circuit board with glaze low antibody
JPS57184295A (en) * 1981-05-08 1982-11-12 Furukawa Circuit Foil Copper foil for printed circuit and method of producing same
JPS5848432A (en) * 1981-09-17 1983-03-22 Denki Kagaku Kogyo Kk Manufacture of hybrid integrated circuit
JPS6017988A (en) * 1983-07-11 1985-01-29 三井金属鉱業株式会社 Printed circuit material
JPS6143449A (en) * 1984-08-08 1986-03-03 Hitachi Ltd Forming process of wiring pattern
JPS61284991A (en) * 1985-06-11 1986-12-15 電気化学工業株式会社 Circuit formation for aluminum/copper composite lined board

Also Published As

Publication number Publication date
JPS63282780A (en) 1988-11-18

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