JPH0778844A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH0778844A
JPH0778844A JP22298193A JP22298193A JPH0778844A JP H0778844 A JPH0778844 A JP H0778844A JP 22298193 A JP22298193 A JP 22298193A JP 22298193 A JP22298193 A JP 22298193A JP H0778844 A JPH0778844 A JP H0778844A
Authority
JP
Japan
Prior art keywords
parts
insulating film
pad
etching
thickness
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP22298193A
Other languages
Japanese (ja)
Inventor
Hirosuke Yagi
裕輔 八木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Miyazaki Oki Electric Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Miyazaki Oki Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd, Miyazaki Oki Electric Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP22298193A priority Critical patent/JPH0778844A/en
Publication of JPH0778844A publication Critical patent/JPH0778844A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165—Reinforcing structures
    • H01L2224/02166—Collar structures

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To make an insulating film on bonding pad electrode parts provided on a semiconductor substrate flat and its thickness uniform by making the bonding pad electrode parts rugged. CONSTITUTION:A plurality of removed parts 13 are juxtaposed in the longitudinal and lateral directions at specific intervals on pad parts 7. When the pad parts 7 are made fine fugged, the insulating film 4 thereon can be formed as if falling into the removed parts 13 so that the thickness of the insulating film 4 on a flat wiring part 3 and the one on the pad parts 7 may be make almost equal and uniform. Accordingly, the etching time for making are aperture parts 2 in the insulating film 4 on the pad parts 7 can be almost equalized with the etching time required for simultaneously etching the insulating film 4 on the other parts thereby enabling the excessive etching in the other parts to be avoided.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【産業上の利用分野】この発明は、半導体装置における
ボンディングパッド電極部の構造に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of a bonding pad electrode portion in a semiconductor device.

【０００２】[0002]

【従来の技術】半導体装置におけるボンディングパッド
電極（以下、単にパッドと称す）部の構造を図２に示
し、以下に説明する。図２の（ａ）は上面図、（ｂ）は
そのＡ−Ａ断面図である。2. Description of the Related Art The structure of a bonding pad electrode (hereinafter, simply referred to as a pad) portion in a semiconductor device is shown in FIG. 2 and will be described below. 2A is a top view and FIG. 2B is a sectional view taken along line AA.

【０００３】図２において、６は半導体基板（以下、単
に基板と称す）であり、その上に絶縁膜（例えば酸化
膜）５が形成されている。そして、その上の所定部分に
電極配線（例えばＡｌあるいはその合金や高融点金属な
ど。以下、単に配線と称す）３が形成されており、その
配線３の一部が外部と電気的接続（一般に金線によるボ
ンディング）をするボンディングパッド電極（パッド）
部１になっている。その上に、該パッド部１の上部に開
口部２を有する絶縁膜４が設けられている。In FIG. 2, reference numeral 6 denotes a semiconductor substrate (hereinafter, simply referred to as a substrate), on which an insulating film (for example, an oxide film) 5 is formed. Electrode wiring (for example, Al or its alloy, refractory metal, etc .; hereinafter simply referred to as wiring) 3 is formed on a predetermined portion on the wiring 3, and a part of the wiring 3 is electrically connected to the outside (generally, Bonding pad electrode (pad) for bonding with gold wire)
It is Part 1. An insulating film 4 having an opening 2 is provided on the pad portion 1 on the insulating film 4.

【０００４】このような構造の製法は改めて説明するま
でもないが、以下に簡単に述べておく。The manufacturing method of such a structure need not be explained again, but will be briefly described below.

【０００５】まず、基板６上に絶縁膜５として例えば熱
酸化法で酸化膜を形成し、その上に配線４として例えば
Ａｌあるいはその合金または高融点金属（Ｗあるいはそ
の合金など）を公知の真空蒸着法やスパッタ法などで形
成し、ホトリソ（ホトリソグラフィ）・エッチング技術
で、フォトレジストパターンをマスクにして所定形状
（図２に示すようにパッド部１を有する配線３の形状）
にパターニングする。次いで、前記フォトレジストを除
去して、配線３上に絶縁膜４として、例えば、プラズマ
ＣＶＤ窒化膜あるいは該窒化膜とＣＶＤ酸化膜との積層
膜などをＣＶＤ法（化学気相成長法、プラズマＣＶＤ法
も含む）により形成し、パッド部１の上をホトリソ・エ
ッチング技術で開口してパッド部の開口部２を形成す
る。First, an oxide film is formed as an insulating film 5 on the substrate 6 by, for example, a thermal oxidation method, and Al or an alloy thereof or a refractory metal (W or an alloy thereof) is formed as a wiring 4 on the oxide film by a known vacuum. It is formed by a vapor deposition method or a sputtering method, and the photoresist pattern is used as a mask by a photolithography (etching) / etching technique to form a predetermined shape (the shape of the wiring 3 having the pad portion 1 as shown in FIG. 2).
Pattern. Then, the photoresist is removed, and as the insulating film 4 on the wiring 3, for example, a plasma CVD nitride film or a laminated film of the nitride film and a CVD oxide film is formed by a CVD method (chemical vapor deposition method, plasma CVD method). (Including the method), and the opening 2 of the pad portion is formed by opening the upper portion of the pad portion 1 by the photolithographic etching technique.

【０００６】[0006]

【発明が解決しようとする課題】しかしながら、前述し
た従来の構造ではパッド部において、その上の絶縁膜の
膜厚が均一でないという問題があった。つまり、図２で
示すように、一般に平面的に見て四角形のパッド部１の
各辺端部上でその他の部分（ロ）より高く（イ）なって
いた。これは、絶縁膜、例えばプラズマ窒化膜生成のと
き、膜生成レートが下地の凹凸の度合いにより異なるこ
とに起因する。例えば、プラズマＣＶＤ装置にてパッド
部１の各辺端部上に生成されるプラズマ窒化膜４は、パ
ッド部１に続く配線部３の平坦な部分の上に生成される
窒化膜４の厚さ（ロ）の１．５倍の厚さ（イ）となる。
これは前述したように、パッド部１まで配線３の続きと
して平坦な構造をしていて、パッド部１の各辺端部のみ
角のある形状になっていることに起因している。つま
り、凹凸の度合いが前記パッド部の辺のみでいわば疎で
あるからである。However, the above-described conventional structure has a problem that the film thickness of the insulating film on the pad portion is not uniform. That is, as shown in FIG. 2, it is higher (a) than the other part (b) on each side end part of the pad part 1 which is generally rectangular in plan view. This is because, when an insulating film such as a plasma nitride film is formed, the film formation rate varies depending on the degree of unevenness of the base. For example, the plasma nitride film 4 formed on each end of the pad portion 1 by the plasma CVD apparatus has a thickness of the nitride film 4 formed on a flat portion of the wiring portion 3 following the pad portion 1. The thickness (a) is 1.5 times that of (b).
This is because, as described above, the pad 3 has a flat structure as a continuation of the wiring 3 up to the pad 1, and each side of the pad 1 has an angular shape. In other words, the degree of unevenness is, so to speak, sparse only on the sides of the pad portion.

【０００７】このため、前記絶縁膜生成後の工程である
パッド部上の開口におけるエッチングでは、前述した厚
さの分の時間がかかる。従って、その部分以外の前記絶
縁膜のエッチングを同時にする場合、その部分のエッチ
ングは過剰となり、技術的に満足できなかった。For this reason, the etching of the opening on the pad portion, which is the step after the insulating film is formed, requires time corresponding to the above-mentioned thickness. Therefore, when the insulating film other than that portion is etched at the same time, the etching of that portion becomes excessive, which is not technically satisfactory.

【０００８】本発明は、以上述べた不満足な点を除去す
るため、パッド部の構造を密な凹凸形状にすることによ
り、その上の絶縁膜の厚さをより平坦に均一化すること
を目的とする。In order to eliminate the above-mentioned unsatisfactory points, the present invention aims to make the thickness of the insulating film on the pad portion uniform by making the structure of the pad portion dense and uneven. And

【０００９】[0009]

【課題を解決するための手段】前記目的達成のために本
発明は、半導体装置におけるボンディングパッド部の構
造を凹凸形状（パッド部に複数の開口部（削除部）を設
ける）にして、平坦な部分の面積を少なくした、つま
り、凹凸の度合いを密にしたものである。In order to achieve the above object, the present invention provides a semiconductor device having a bonding pad structure having a concavo-convex shape (providing a plurality of openings (removed parts) in the pad part) and a flat structure. The area of the part is reduced, that is, the degree of unevenness is increased.

【００１０】[0010]

【作用】前述したように、本発明はパッド部の構造を凹
凸状にしたので、その部分において平坦な部分の面積が
少なくなり、つまり凹凸の度合いが密になり、その上に
生成される絶縁膜の膜厚は凹凸が少なくなり均一化され
る。従って、パッド部上の絶縁膜に開口部を形成するた
めのエッチングの時間が短くなり、前述した他の部分に
対する過剰なエッチングを行なわずにすむ。As described above, according to the present invention, since the structure of the pad portion is made uneven, the area of the flat portion is reduced in that portion, that is, the degree of unevenness becomes dense, and the insulation formed on it is reduced. The film thickness of the film is uniform with less irregularities. Therefore, the etching time for forming the opening in the insulating film on the pad portion is shortened, and it is not necessary to excessively etch the other portion described above.

【００１１】ただ、以上述べたような凹凸が疎である場
合、そこの部分で前記絶縁膜（窒化膜）がなぜ盛り上が
るかは完全に解明されていない。おそらく窒化膜形成時
のＳｉＨ4 ラジカルとＮＨ3 ラジカルの発生量に起因す
るものと考えられている。However, when the unevenness as described above is sparse, it is not completely understood why the insulating film (nitride film) rises at that portion. Probably due to the amount of SiH 4 radicals and NH 3 radicals generated during the formation of the nitride film.

【００１２】[0012]

【実施例】図１に本発明の実施例の構造を、従来例と同
様図１（ａ）に上面図、（ｂ）にそのＢ−Ｂ断面図で示
し、以下に説明する。なお、従来例と同じ部分には同じ
符号を付してある。DESCRIPTION OF THE PREFERRED EMBODIMENTS The structure of an embodiment of the present invention is shown in FIG. 1 as a top view in FIG. 1 (a) and as a sectional view taken along line BB in FIG. The same parts as those in the conventional example are designated by the same reference numerals.

【００１３】図１において、６は半導体基板（以下、単
に基板と称す）であり、従来同様その上に絶縁膜（例え
ば酸化膜）５が形成されている。そして、その上の所定
部分に電極配線（例えばＡｌあるいはその合金や高融点
金属など）３が従来同様形成されており、その配線３の
一部が後述する形状のボンディングパッド電極（パッ
ド）部７になっている。その上に、該パッド部７の上部
に開口部２を有する絶縁膜（従来同様窒化膜など）４が
従来同様設けられている。In FIG. 1, reference numeral 6 denotes a semiconductor substrate (hereinafter simply referred to as a substrate), on which an insulating film (for example, an oxide film) 5 is formed as in the conventional case. An electrode wiring (for example, Al or an alloy thereof or a high melting point metal) 3 is formed on a predetermined portion on the bonding pad electrode (pad) portion 7 having a shape described later. It has become. On top of that, an insulating film (such as a nitride film) 4 having an opening 2 is provided on the pad 7 as in the conventional case.

【００１４】本実施例では、前記パッド部７の形状を凹
凸状、つまり、図１に示すようにパッド部に複数の削除
部（いわばパッド部の複数箇所を開口削除して中抜き状
にした開口部分）１３が所定の間隔をおいて縦、横に並
べた形状としてある。なお、この削除部１３の平面的に
見た形は本実施例では図１（ａ）に示すように四角形に
しているが円形でもよい。言い換えれば、このパッド部
７は前記削除部１３が格子状に複数設けられているの
で、全体として凹凸形状となっている。このように凹凸
を特に規則正しく格子状にする必要もないが、その上に
形成する絶縁膜４の厚さをできるだけ均一化するにはこ
のようにバランスをとった形状がよい。In the present embodiment, the shape of the pad portion 7 is uneven, that is, as shown in FIG. 1, the pad portion has a plurality of deletion portions (so to speak, a plurality of portions of the pad portion are opened to have a hollow shape). The opening portion 13 has a shape in which the openings 13 are arranged vertically and horizontally at a predetermined interval. Although the shape of the deleting portion 13 viewed in plan is a quadrangle as shown in FIG. 1A in this embodiment, it may be a circle. In other words, since the pad portion 7 is provided with a plurality of the deletion portions 13 in a grid pattern, the pad portion 7 has an uneven shape as a whole. Thus, it is not necessary to form the irregularities in a regular grid pattern, but in order to make the thickness of the insulating film 4 formed thereon as uniform as possible, such a balanced shape is preferable.

【００１５】このようなパッド部７の削除部１３の形成
は、公知のホトリソ・エッチング技術でパターニングす
れば容易にできることは説明するまでもない。It goes without saying that the formation of the deleted portion 13 of the pad portion 7 can be easily performed by patterning by a known photolithographic etching technique.

【００１６】以上のようにパッド部７を密な凹凸状にす
ると、その上に形成する絶縁膜４はパッド部７の前記削
除部１３に落ち込むように形成されるので、従来例のよ
うにパッド部７の外辺端部で極端に厚く盛り上がるよう
なことはなくなり、絶縁膜４は平坦な配線部３上の厚さ
（ニ）とパッド部７上の厚さ（ハ）とはほぼ等しくな
る。つまり均一化される。従って、パッド部７上に絶縁
膜４の開口部２を形成する際のエッチングも、同時にエ
ッチングする他の部分の絶縁膜４に必要なエッチング時
間とほぼ同じでよく、前記他の部分が過剰エッチングに
なるようなことはない。As described above, when the pad portion 7 is formed into a dense concavo-convex shape, the insulating film 4 formed on the pad portion 7 is formed so as to fall into the deleted portion 13 of the pad portion 7. The outer edge of the portion 7 does not rise extremely thickly, and the insulating film 4 has a flat thickness (d) on the wiring portion 3 and a thickness (c) on the pad portion 7 substantially equal to each other. . That is, it is made uniform. Therefore, the etching for forming the opening 2 of the insulating film 4 on the pad portion 7 may be almost the same as the etching time required for the insulating film 4 of the other portion to be etched at the same time, and the other portion is over-etched. There is no such thing as.

【００１７】[0017]

【発明の効果】以上説明したように、本発明によれば、
ボンディングパッド電極部の形状を凹凸状にしたので、
その上に形成する絶縁膜の厚さが前述したように均一化
され、従来例のように他の部分が過剰エッチングされる
不具合が解消される。As described above, according to the present invention,
Since the shape of the bonding pad electrode part is made uneven,
The thickness of the insulating film formed thereon is made uniform as described above, and the problem of excessive etching of other portions as in the conventional example is eliminated.

【００１８】また、従来例のようにパッド部上の絶縁膜
が異常に厚く形成されているために引き起こされる絶縁
膜ストレスによる悪影響も防止できる。Further, it is possible to prevent an adverse effect due to the insulating film stress caused by the insulating film on the pad portion being formed to be abnormally thick as in the conventional example.

【図面の簡単な説明】[Brief description of drawings]

【図１】本発明の実施例によるボンディングパッド部構
造図FIG. 1 is a structural diagram of a bonding pad portion according to an embodiment of the present invention.

【図２】従来例のボンディングパッド部構造図FIG. 2 is a structural diagram of a conventional bonding pad section.

【符号の説明】[Explanation of symbols]

２ ボンディングパッド部開口部 ３ 配線 ４、５ 絶縁膜 ６ 半導体基板 ７ ボンディングパッド部 2 Bonding pad opening 3 Wiring 4, 5 Insulating film 6 Semiconductor substrate 7 Bonding pad

Claims (2)

【特許請求の範囲】[Claims] 【請求項１】 半導体基板上に設けられているボンディ
ングパッド電極部を凹凸形状にしたことを特徴とする半
導体装置。1. A semiconductor device characterized in that a bonding pad electrode portion provided on a semiconductor substrate has an uneven shape. 【請求項２】 前記ボンディングパッド電極部の凹凸形
状として、該ボンディングパッド電極部の複数箇所に開
口部（削除部）を設けてあることを特徴とする請求項１
記載の半導体装置。2. The unevenness shape of the bonding pad electrode portion is such that openings (removal portions) are provided at a plurality of portions of the bonding pad electrode portion.
The semiconductor device described.
JP22298193A 1993-09-08 1993-09-08 Semiconductor device Pending JPH0778844A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP22298193A JPH0778844A (en) 1993-09-08 1993-09-08 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP22298193A JPH0778844A (en) 1993-09-08 1993-09-08 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH0778844A true JPH0778844A (en) 1995-03-20

Family

ID=16790932

Family Applications (1)

Application Number Title Priority Date Filing Date
JP22298193A Pending JPH0778844A (en) 1993-09-08 1993-09-08 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH0778844A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010507022A (en) * 2006-10-20 2010-03-04 スリーエム イノベイティブ プロパティズ カンパニー Method for easy cleaning substrate and article thereby

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010507022A (en) * 2006-10-20 2010-03-04 スリーエム イノベイティブ プロパティズ カンパニー Method for easy cleaning substrate and article thereby

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