JPH07297224A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH07297224A JPH07297224A JP8423294A JP8423294A JPH07297224A JP H07297224 A JPH07297224 A JP H07297224A JP 8423294 A JP8423294 A JP 8423294A JP 8423294 A JP8423294 A JP 8423294A JP H07297224 A JPH07297224 A JP H07297224A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- lead bonding
- plate
- bonding window
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Wire Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体装置に関し、特に
ＴＣＰ（Ｔａｐｅ Ｃａｒｒｉｅｒ Ｐａｃｋａｇｅ）
に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to TCP (Tape Carrier Package).
Regarding
【０００２】[0002]
【従来の技術】従来のＴＣＰについて図面を参照して説
明する。2. Description of the Related Art A conventional TCP will be described with reference to the drawings.
【０００３】図２（ａ）は従来のＴＣＰを示す平面図、
図２（ｂ）は図２（ａ）のＢ−Ｂ′線断面図、図２
（ｃ）は図２（ａ）の底面図である。FIG. 2A is a plan view showing a conventional TCP,
2B is a sectional view taken along the line BB ′ of FIG.
FIG. 2C is a bottom view of FIG.
【０００４】図２（ａ）〜（ｃ）に示すように、スプロ
ケットホール２，インナーリードボンディング用窓７，
アウターリードボンディング用窓６の夫々を形成した絶
縁フィルム１の表面に接着剤で接着したＣｕ箔をパター
ニングしてリード３を形成したＴＡＢテープのリード３
と、半導体チップ４に形成したバンプ８とを超音波接合
でインナーリードボンディングし、半導体チップ４の表
面とリード３の先端にエポキシ系の樹脂５で薄くコーテ
ィングする。As shown in FIGS. 2A to 2C, the sprocket hole 2, the inner lead bonding window 7,
Lead 3 of the TAB tape in which a lead 3 is formed by patterning a Cu foil adhered with an adhesive to the surface of the insulating film 1 in which the windows 6 for outer lead bonding are formed.
And the bumps 8 formed on the semiconductor chip 4 are subjected to inner lead bonding by ultrasonic bonding, and the surface of the semiconductor chip 4 and the tips of the leads 3 are thinly coated with an epoxy resin 5.
【０００５】次に、半導体チップ４の裏面に製品名や製
造ロット番号をインク又はレーザにより捺印してＴＣＰ
を構成する。Next, the product name and manufacturing lot number are imprinted on the back surface of the semiconductor chip 4 with ink or laser to form a TCP.
Make up.
【０００６】このように、ＴＣＰは外形が小型で且つ非
常に薄くできるという特徴を有している。As described above, the TCP has a feature that its outer shape is small and can be made very thin.
【０００７】[0007]
【発明が解決しようとする課題】この従来のＴＣＰで
は、半導体チップの裏面に製品名や製造ロット番号を捺
印するため、他の種類のパッケージに比べて捺印可能な
範囲が非常に狭いうえに搭載する半導体チップの外形に
より捺印可能な文字の大きさや、文字数が異なってく
る。例えば、ＣＭＯＳ Ｇ／Ａでは同じピン数でも半導
体チップの外形の種類が２０〜３０種類もあり、その種
類ごとに製品外形、捺印指定を管理することは非常に困
難であるという問題があった。In this conventional TCP, since the product name and the manufacturing lot number are imprinted on the back surface of the semiconductor chip, the imprintable range is very narrow compared to other types of packages, and it is mounted. The size and number of characters that can be imprinted differ depending on the outer shape of the semiconductor chip. For example, in CMOS G / A, there are 20 to 30 types of outer shapes of semiconductor chips even with the same number of pins, and it is very difficult to manage the product outer shape and marking designation for each type.
【０００８】[0008]
【課題を解決するための手段】本発明の半導体装置は、
インナーリードボンディング用窓およびアウターリード
ボンディング用窓を設けた絶縁フィルム上に形成して前
記インナーリードボンディング用窓内に先端を突出した
リードを有するＴＡＢテープと、前記リードの先端に電
極を接合して前記ＴＡＢテープ上に搭載した半導体チッ
プと、前記リードの先端を含む前記半導体チップの表面
を樹脂でコーティングした半導体装置において、前記半
導体チップの裏面に接着して設け且つ前記半導体チップ
よりも大きく前記アウターリードボンディング用窓の内
枠よりも小さい面積を有する捺印用の薄板を備えてい
る。The semiconductor device of the present invention comprises:
A TAB tape formed on an insulating film provided with an inner lead bonding window and an outer lead bonding window and having a lead protruding at the inner lead bonding window, and an electrode bonded to the leading end of the lead In a semiconductor device in which a semiconductor chip mounted on the TAB tape and a surface of the semiconductor chip including tips of the leads are coated with a resin, the semiconductor chip is provided by being adhered to the back surface of the semiconductor chip and is larger than the semiconductor chip. A thin stamping plate having an area smaller than the inner frame of the lead bonding window is provided.
【０００９】[0009]
【実施例】次に、本発明について図面を参照して説明す
る。DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.
【００１０】図１（ａ）は本発明の一実施例を示す平面
図、図１（ｂ）は図１（ａ）のＡ−Ａ′線断面図であ
る。FIG. 1 (a) is a plan view showing an embodiment of the present invention, and FIG. 1 (b) is a sectional view taken along the line AA 'in FIG. 1 (a).
【００１１】図１（ａ），（ｂ）に示すように、スプロ
ケットホール２，インナーリードボンディング用窓（又
はデバイス開口部）７，アウターリードボンディング用
窓６の夫々を形成した絶縁フィルム１の表面に接着剤に
より接着したＣｕ箔をパターニングしてインナーリード
ボンディング用窓７内に先端を突出したリード３を有す
るＴＡＢテープを形成する。As shown in FIGS. 1 (a) and 1 (b), the surface of the insulating film 1 on which the sprocket hole 2, the inner lead bonding window (or device opening) 7 and the outer lead bonding window 6 are formed, respectively. The Cu foil adhered by an adhesive is patterned to form a TAB tape having the lead 3 with the tip protruding in the inner lead bonding window 7.
【００１２】ここで、インナーリードボンディング用窓
７は同じピン数でも機種の異なる半導体チップ４の寸法
の大小に応じて大きさが異なるが、アウターリードボン
ディング用窓６の寸法、位置は変らず一定である。Although the inner lead bonding window 7 has different sizes depending on the size of the semiconductor chips 4 of different models even with the same number of pins, the outer lead bonding window 6 remains constant in size and position. Is.
【００１３】次に、半導体チップ４の電極パッドに設け
たバンプ８とリード３の先端とを位置合わせし超音波接
合でインナーリードボンディングして半導体チップ４を
ＴＡＢテープ上に搭載し、半導体チップの裏面にＡｇペ
ースト等の接着剤９によりアルミニウムやステンレスあ
るいはチタン等の金属板からなる厚さ０．１〜１．０ｍ
ｍの捺印用の薄板１０を接着する。Next, the bumps 8 provided on the electrode pads of the semiconductor chip 4 are aligned with the tips of the leads 3 and inner lead bonding is performed by ultrasonic bonding to mount the semiconductor chip 4 on the TAB tape. The back surface is made of a metal plate such as aluminum, stainless steel, or titanium with an adhesive 9 such as Ag paste and has a thickness of 0.1 to 1.0 m.
The m thin stamping plate 10 is bonded.
【００１４】ここで、薄板１０は搭載された半導体チッ
プ４の寸法よりも大きく、且つアウタリードボンディン
グ用窓６の内枠（各辺に存在するアウターリードボンデ
ィング用窓６のインナーリードボンディング用窓７側の
枠で囲まれた領域）よりも小さい面積を有している。Here, the thin plate 10 is larger than the size of the mounted semiconductor chip 4 and the inner frame of the outer lead bonding window 6 (the inner lead bonding window 7 of the outer lead bonding window 6 existing on each side). Area smaller than the area surrounded by the side frame).
【００１５】また、薄板１０はＣｕや４２合金等の金属
板を使用しても良く、腐食し易いものについてはＮｉめ
っきや半田めっきを施すかあるいは塗料を塗布して用い
る。また、これらの金属板以外にエポキシ系等の樹脂板
や各種のセラミクス板を用いても良く、腐食の問題を解
決できる利点がある。Further, the thin plate 10 may be made of a metal plate such as Cu or 42 alloy, and if it is easily corroded, Ni plating or solder plating is applied or a coating is applied. In addition to these metal plates, epoxy-based resin plates and various ceramics plates may be used, which has the advantage of solving the problem of corrosion.
【００１６】なお、薄板１０を半導体チップ４の裏面に
接着する工程はインナーリードボンディングの前又は後
で行っても良いし、インナーリードボンディングと同時
に行うことも可能である。The step of adhering the thin plate 10 to the back surface of the semiconductor chip 4 may be performed before or after the inner lead bonding, or may be performed simultaneously with the inner lead bonding.
【００１７】次に、半導体チップ４の表面およびリード
３の先端を含む部分にエポキシ樹脂５をコーティング
し、薄板１０の表面にインク又はレーザで製品名や製造
ロット番号を捺印する。Next, the surface of the semiconductor chip 4 and the portion including the tips of the leads 3 are coated with an epoxy resin 5, and the surface of the thin plate 10 is marked with a product name and a manufacturing lot number with ink or laser.
【００１８】[0018]
【発明の効果】以上説明したように本発明は、半導体チ
ップ４の裏面に捺印用の薄板を接着して、この薄板の表
面に捺印することにより、同じピン数のＴＣＰにおける
捺印寸法を搭載する半導体チップの寸法の大小にかかわ
らず捺印寸法を統一することができ、生産工程の簡略化
を実現できるという効果を有する。As described above, according to the present invention, a thin stamping plate is adhered to the back surface of the semiconductor chip 4 and is stamped on the surface of this thin plate, so that the stamping size of the TCP having the same number of pins is mounted. The marking size can be unified regardless of the size of the semiconductor chip, and the production process can be simplified.
【図１】本発明の一実施例を示す平面図およびＡ−Ａ′
線断面図。FIG. 1 is a plan view showing an embodiment of the present invention and AA ′.
FIG.
【図２】従来の半導体装置の一例を示す平面図およびＢ
−Ｂ′線断面図および底面図。FIG. 2 is a plan view showing an example of a conventional semiconductor device and FIG.
-B 'line sectional view and a bottom view.
１ ＴＡＢテープ ２ スプロケットホール ３ リード ４ 半導体チップ ５ 樹脂 ６ アウターリードボンディング用窓 ７ インナーリードボンディング用窓 ８ バンプ ９ 接着剤 １０ 薄板 1 TAB Tape 2 Sprocket Hole 3 Lead 4 Semiconductor Chip 5 Resin 6 Outer Lead Bonding Window 7 Inner Lead Bonding Window 8 Bump 9 Adhesive 10 Thin Plate
Claims (4)
アウターリードボンディング用窓を設けた絶縁フィルム
上に形成して前記インナーリードボンディング用窓内に
先端を突出したリードを有するＴＡＢテープと、前記リ
ードの先端に電極を接合して前記ＴＡＢテープ上に搭載
した半導体チップと、前記リードの先端を含む前記半導
体チップの表面を樹脂でコーティングした半導体装置に
おいて、前記半導体チップの裏面に接着して設け且つ前
記半導体チップよりも大きく前記アウターリードボンデ
ィング用窓の内枠よりも小さい面積を有する捺印用の薄
板を備えたことを特徴とする半導体装置。1. A TAB tape having a lead formed on an insulating film provided with an inner lead bonding window and an outer lead bonding window, the tip protruding into the inner lead bonding window, and the tip of the lead. In a semiconductor device having electrodes bonded to each other and mounted on the TAB tape, and a semiconductor device in which the surface of the semiconductor chip including the tips of the leads is coated with resin, the semiconductor chip is provided by being bonded to the back surface of the semiconductor chip. A semiconductor device comprising a stamping thin plate having an area larger than that of the inner frame of the outer lead bonding window.
ン，銅，４２合金のいずれか１種の金属板である請求項
１記載の半導体装置。2. The semiconductor device according to claim 1, wherein the thin plate is a metal plate selected from the group consisting of aluminum, stainless steel, titanium, copper and 42 alloy.
１記載の半導体装置。3. The semiconductor device according to claim 1, wherein the thin plate is an epoxy resin plate.
の半導体装置。4. The semiconductor device according to claim 1, wherein the thin plate is a ceramics plate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8423294A JPH07297224A (en) | 1994-04-22 | 1994-04-22 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8423294A JPH07297224A (en) | 1994-04-22 | 1994-04-22 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH07297224A true JPH07297224A (en) | 1995-11-10 |
Family
ID=13824736
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8423294A Pending JPH07297224A (en) | 1994-04-22 | 1994-04-22 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH07297224A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2000048247A1 (en) * | 1999-02-15 | 2000-08-17 | Hitachi, Ltd. | Semiconductor device, method of manufacture thereof, electronic device |
| JP2003209213A (en) * | 2002-01-17 | 2003-07-25 | Fuji Electric Co Ltd | Method for manufacturing lead frame and semiconductor device |
| KR100705521B1 (en) * | 1998-12-02 | 2007-04-10 | 가부시키가이샤 히타치세이사쿠쇼 | Semiconductor device |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6352429A (en) * | 1986-08-22 | 1988-03-05 | Hitachi Ltd | Semiconductor device |
| JPS63293928A (en) * | 1987-05-27 | 1988-11-30 | Hitachi Ltd | Electronic device |
| JPH01270335A (en) * | 1988-04-22 | 1989-10-27 | Hitachi Ltd | Semiconductor device |
-
1994
- 1994-04-22 JP JP8423294A patent/JPH07297224A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6352429A (en) * | 1986-08-22 | 1988-03-05 | Hitachi Ltd | Semiconductor device |
| JPS63293928A (en) * | 1987-05-27 | 1988-11-30 | Hitachi Ltd | Electronic device |
| JPH01270335A (en) * | 1988-04-22 | 1989-10-27 | Hitachi Ltd | Semiconductor device |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100705521B1 (en) * | 1998-12-02 | 2007-04-10 | 가부시키가이샤 히타치세이사쿠쇼 | Semiconductor device |
| WO2000048247A1 (en) * | 1999-02-15 | 2000-08-17 | Hitachi, Ltd. | Semiconductor device, method of manufacture thereof, electronic device |
| JP2003209213A (en) * | 2002-01-17 | 2003-07-25 | Fuji Electric Co Ltd | Method for manufacturing lead frame and semiconductor device |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 19960618 |