JPH06821Y2 - Semiconductor device mounting structure - Google Patents
Semiconductor device mounting structureInfo
- Publication number
- JPH06821Y2 JPH06821Y2 JP1987195704U JP19570487U JPH06821Y2 JP H06821 Y2 JPH06821 Y2 JP H06821Y2 JP 1987195704 U JP1987195704 U JP 1987195704U JP 19570487 U JP19570487 U JP 19570487U JP H06821 Y2 JPH06821 Y2 JP H06821Y2
- Authority
- JP
- Japan
- Prior art keywords
- conductor
- semiconductor device
- insulating resin
- protective plate
- protruding electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Wire Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
【考案の詳細な説明】 〔産業上の利用分野〕 本考案は半導体装置（以下ＩＣと記す）を小型、薄型で
パッケージングする実装構造に関する。DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a mounting structure for packaging a semiconductor device (hereinafter referred to as an IC) in a small and thin shape.
従来、表面実装に対応する一般的なパッケージであるス
モールアウトラインパッケージ（ＳＯＰ）、クァッドフ
ラットパッケージ（ＱＦＰ）、プラスチックリーデッド
チップキャリア（ＰＬＣＣ）、リードレスチップキャリ
ア（ＬＣＣ）等は、その実装構造上外形寸法がＩＣチッ
プサイズに比べ占有面積で３〜４倍と、かなり大型にな
る。例えば、第５図に示したＳＯＰおよび第６図に示し
たＬＣＣにて説明する。Conventionally, general outline packages such as small outline package (SOP), quad flat package (QFP), plastic leaded chip carrier (PLCC), leadless chip carrier (LCC), etc., which are compatible with surface mounting, have an external shape due to their mounting structure. The size is 3 to 4 times larger than the IC chip size, which is considerably large. For example, the SOP shown in FIG. 5 and the LCC shown in FIG. 6 will be described.
ＳＯＰでは、絶縁樹脂３の外側にリードフレーム６を設
ける構造、ＬＣＣでは基板８上に導体４を形成し絶縁樹
脂３で封止する構造のため、ＩＣ１のチップサイズに比
べ従来構造の表面実装パッケージは、占有面積が約３倍
と大きい。近年、ＩＣの微細化、高密度表面実装の進展
にともない、前記した一般的なパッケージが、要求され
るＩＣ電極ピッチ及び外形寸法に対して適合しなくなっ
てきた。例えば、前記の一般的なパッケージはＩＣの電
極とアウターリードとの接続をワイヤーボンディング法
で行なっていることからピッチ１２０ミクロン以下のア
ウターリードへの接続が困難であること。また、リード
フレームを使うパッケージでは第４図に示したように、
ＩＣ１とリードフレーム６とを金ワイヤー７で接続し
て、このリードフレーム６も絶縁樹脂３で保護する構造
のため薄型化に適さないこと、更に、ワイヤーボンディ
ング法による接続は生産性及びコスト面に欠点を持つこ
とが挙げられる。The SOP has a structure in which the lead frame 6 is provided outside the insulating resin 3, and the LCC has a structure in which the conductor 4 is formed on the substrate 8 and sealed with the insulating resin 3. Therefore, the surface mount package has a conventional structure compared to the chip size of the IC 1. Occupies a large area of about three times. In recent years, with the miniaturization of ICs and the progress of high-density surface mounting, the above-mentioned general packages have become unsuitable for the required IC electrode pitch and external dimensions. For example, in the general package described above, it is difficult to connect the outer leads having a pitch of 120 μm or less because the electrodes of the IC are connected to the outer leads by a wire bonding method. In a package that uses a lead frame, as shown in Fig. 4,
The structure in which the IC 1 and the lead frame 6 are connected by the gold wire 7 and the lead frame 6 is also protected by the insulating resin 3 is not suitable for thinning. Further, the connection by the wire bonding method is in terms of productivity and cost. It has some drawbacks.
本考案の目的は、前記した一般的なパッケージよりも更
に小型、薄型のパッケージを低コストでかつ単純な構造
で提供することにある。そのためリードフレームや基板
を用いていない実装構造になっている。更にこの構造に
よりワイヤーボンディング法による接続も不用となる。An object of the present invention is to provide a package that is smaller and thinner than the general package described above, at a low cost and with a simple structure. Therefore, the mounting structure does not use a lead frame or a substrate. Furthermore, this structure also eliminates the need for connection by the wire bonding method.
構成 第２図(c)に示すように、ＩＣ(1)の電極上に蒸着、スパ
ッタ、メッキ、ペースト印刷等によりアルミ、銅、金、
半田等からなる突起電極２を露出するようにＩＣ１のほ
ぼ全面を厚さ数百ミクロンで覆う絶縁樹脂３と、突起電
極２と絶縁樹脂３外絶部を結ぶための深さ数十ミクロン
の導体４を形成する凹溝９と、この凹溝９に蒸着、スパ
ッタ、メッキ、ペースト印刷等で形成された銅、金、半
田、銀ペースト等からなる導体４とからなる構造を持つ
小型、薄型パッケージ。Structure As shown in Fig. 2 (c), aluminum, copper, gold, etc. are deposited on the electrodes of the IC (1) by vapor deposition, sputtering, plating, paste printing, etc.
An insulating resin 3 covering almost the entire surface of the IC 1 with a thickness of several hundreds of microns so as to expose the protruding electrode 2 made of solder or the like, and a conductor having a depth of several tens of microns for connecting the protruding electrode 2 and the insulating resin 3 isolation portion. 4, a small and thin package having a structure including a concave groove 9 forming 4 and a conductor 4 made of copper, gold, solder, silver paste or the like formed in the concave groove 9 by vapor deposition, sputtering, plating, paste printing or the like. .
構成 第３図(b)に示すようにＩＣ１の電極上に蒸着、スパッ
タ、メッキ、ペースト印刷等によりアルミ、銅、金、半
田等からなる突起電極２に対応した穴と、突起電極２と
プラスチック保護板５外縁部とを結ぶ導体４を形成する
凹溝９とが形成されたプラスチック保護板５を前記のＩ
Ｃ１の電極側上に位置あわせしたものと、プラスチック
保護板５の凹溝９に蒸着、スパッタ、メッキ、ペースト
印刷等で形成された銅、金、半田、銀ペースト等からな
る導体４と、ＩＣ１裏面を厚さ数百ミクロンで覆う絶縁
樹脂３とからなる構造を持つ小型、薄型パッケージ。Structure As shown in FIG. 3 (b), a hole corresponding to the protruding electrode 2 made of aluminum, copper, gold, solder or the like is formed on the electrode of the IC1 by vapor deposition, sputtering, plating, paste printing, etc., the protruding electrode 2 and the plastic. The plastic protective plate 5 having the concave groove 9 forming the conductor 4 connecting to the outer edge of the protective plate 5 is formed as described above in I.
C1 aligned on the electrode side, conductor 4 made of copper, gold, solder, silver paste or the like formed in the groove 9 of the plastic protective plate 5 by vapor deposition, sputtering, plating, paste printing, etc., and IC1 A small, thin package with a structure consisting of an insulating resin 3 that covers the back surface with a thickness of several hundreds of microns.
構成および構成のいずれもＩＣ１の電極は、突起電
極２を形成しなくても良い。In both of the configurations and the configurations, the electrodes of the IC 1 do not need to form the protruding electrodes 2.
以下、本考案の実施例における構成の構成を得るため
の方法を図面によって説明する。第１図はＩＣ１が絶縁
樹脂３で保護された平面図を示す。Hereinafter, a method for obtaining the configuration of the embodiment of the present invention will be described with reference to the drawings. FIG. 1 shows a plan view in which the IC 1 is protected by the insulating resin 3.
ここに示した実施例の構成ではＩＣ１の電極上に突起電
極２が形成されている。前述のようにＩＣ１の電極上に
は突起電極２を形成しなくても良い。第２図(a)は第１
図のＡ−Ａでの断面図を示す。第２図(b)は第２図(a)に
示す突起電極２上および突起電極２側の絶縁樹脂３上に
導体４を形成した断面図を示す。第２図(c)は第２図(b)
に示す導体４を絶縁樹脂３が現われるまで研磨して得ら
れた断面図を示す。第２図(d)は第２図(c)の斜視図を示
す。第１図に示すようにＩＣ１にアルミ、銅、金、半田
等からなる突起電極２をスパッタ、蒸着、メッキ等ある
いはそれらの組合せで形成する。金型等を用いて突起電
極２を露出するようにエポキシ系、ポリフェニレンサル
ファイド（ＰＰＳ）系等の絶縁樹脂３で厚さ数百ミクロ
ンに保護し同時に深さ数十ミクロンの導体４のパターン
に対応する凹溝９を形成する。そのときの第１図のＡ−
Ａの断面図は第２図(a)になる。次に第２図(b)に示すよ
うに凹溝９に銅、金、半田、銀ペースト等からなる導体
４を蒸着、スパッタ、メッキ、ペースト印刷等で形成す
る。In the structure of the embodiment shown here, the protruding electrode 2 is formed on the electrode of the IC 1. As described above, the protruding electrode 2 may not be formed on the electrode of the IC1. Figure 2 (a) shows the first
The sectional view in AA of a figure is shown. FIG. 2 (b) is a sectional view showing the conductor 4 formed on the protruding electrode 2 and the insulating resin 3 on the protruding electrode 2 side shown in FIG. 2 (a). Fig. 2 (c) is Fig. 2 (b).
3 is a sectional view obtained by polishing the conductor 4 shown in FIG. 1 until the insulating resin 3 appears. FIG. 2 (d) shows a perspective view of FIG. 2 (c). As shown in FIG. 1, a protruding electrode 2 made of aluminum, copper, gold, solder or the like is formed on the IC 1 by sputtering, vapor deposition, plating, or a combination thereof. Using a mold or the like, the insulating resin 3 such as epoxy-based or polyphenylene sulfide (PPS) -based so as to expose the protruding electrode 2 is protected to a thickness of several hundreds of microns, and at the same time it corresponds to the pattern of the conductor 4 with a depth of several tens of microns. The concave groove 9 is formed. A- of Fig. 1 at that time
A sectional view of A is shown in FIG. Next, as shown in FIG. 2B, a conductor 4 made of copper, gold, solder, silver paste or the like is formed in the groove 9 by vapor deposition, sputtering, plating, paste printing or the like.
最後に第２図(c)に示したように導体４表面を絶縁樹脂
３が現われるまで研磨することにより第２図(d)に示し
た絶縁樹脂３に導体４が埋込まれた構成の構造を持つ
パッケージが得られる。Finally, as shown in FIG. 2 (c), the surface of the conductor 4 is polished until the insulating resin 3 appears, so that the conductor 4 is embedded in the insulating resin 3 shown in FIG. 2 (d). A package with is obtained.
次に、本考案の実施例における構成の構成を得るため
の方法を図面によって説明する。Next, a method for obtaining the structure of the embodiment of the present invention will be described with reference to the drawings.
構造全体の大きさおよび用いたＩＣが構成Ａ０４０の
場合と同じ例を示す。第３図(a)はＩＣ１の電極側にプ
ラスチック保護板５を位置あわせした第１図のＡ−Ａ断
面図を示す。ここに示した実施例ではＩＣ１の電極上に
突起電極２が形成されている。第３図(a)の断面図は実
施例の構成で示した第１図の絶縁樹脂３の一部をプラ
スチック保護板５に代えたものとなる。第３図(b)は第
３図(a)に示す突起電極２上およびプラスチック保護板
５の凹溝９側上に導体４を形成した断面図を示す。第３
図(c)は第３図(b)に示すＩＣ１の裏面側を絶縁樹脂３で
保護した断面図を示す。The same example as in the case where the size of the entire structure and the IC used is the configuration A040 is shown. FIG. 3 (a) is a sectional view taken along line AA of FIG. 1 in which the plastic protective plate 5 is aligned with the electrode side of the IC 1. In the embodiment shown here, the protruding electrode 2 is formed on the electrode of the IC 1. In the sectional view of FIG. 3 (a), a part of the insulating resin 3 of FIG. 1 shown in the configuration of the embodiment is replaced with a plastic protective plate 5. FIG. 3 (b) is a sectional view showing the conductor 4 formed on the protruding electrode 2 and on the recess 9 side of the plastic protective plate 5 shown in FIG. 3 (a). Third
FIG. 3C is a sectional view of the back surface side of the IC 1 shown in FIG. 3B, which is protected by the insulating resin 3.
第１図に示すようにＩＣ１にアルミ、銅、金、半田等か
らなる突起電極２をスパッタ、蒸着、メッキ等あるいは
それらの組合せで形成する。次に第３図(a)に示すよう
にＩＣ１の突起電極２に対応した穴と、突起電極２とプ
ラスチック保護板５外縁部とを結ぶ導体４のパターンに
対応する深さ数十ミクロンの凹溝９とが形成された厚さ
数百ミクロンのプラスチック保護板５をＩＣ１の突起電
極２上に位置あわせを行ない、治具等を用いてＩＣ１と
プラスチック保護板５を固定する。As shown in FIG. 1, a protruding electrode 2 made of aluminum, copper, gold, solder or the like is formed on the IC 1 by sputtering, vapor deposition, plating, or a combination thereof. Next, as shown in FIG. 3 (a), a hole having a depth of several tens of microns corresponding to the hole corresponding to the protruding electrode 2 of the IC 1 and the pattern of the conductor 4 connecting the protruding electrode 2 and the outer edge of the plastic protective plate 5 are formed. A plastic protective plate 5 having a groove 9 and a thickness of several hundreds of microns is aligned with the protruding electrode 2 of the IC 1, and the IC 1 and the plastic protective plate 5 are fixed using a jig or the like.
次に第３図(b)に示すように突起電極２上およびプラス
チック保護板５の凹溝９上に蒸着、スパッタ、メッキ、
ペースト印刷等で形成された銅、金、半田、銀ペースト
等からなる導体４を形成する。Next, as shown in FIG. 3 (b), vapor deposition, sputtering, plating, on the protruding electrode 2 and on the concave groove 9 of the plastic protective plate 5,
The conductor 4 made of copper, gold, solder, silver paste or the like formed by paste printing or the like is formed.
そして第３図(c)に示すようにＩＣ１の裏面を厚さ数百
ミクロンのエポキシ系、ＰＰＳ系等の絶縁樹脂３で保護
する。第３図(c)に示したように、この構成は実施例
の構成に示した第２図(b)とほぼ同じ構造となる。Then, as shown in FIG. 3 (c), the back surface of the IC 1 is protected by an insulating resin 3 such as an epoxy resin or a PPS resin having a thickness of several hundred microns. As shown in FIG. 3 (c), this structure has almost the same structure as that of FIG. 2 (b) shown in the structure of the embodiment.
以後は、構成の場合と同様に導体４を研磨して第２図
(d)に示したものとほぼ同じ構造を持つ小型、薄型パッ
ケージが得られる。After that, the conductor 4 is polished in the same manner as in the case of the configuration, and FIG.
A small and thin package having almost the same structure as that shown in (d) can be obtained.
以上の説明で明らかなように本考案によればワイヤーボ
ンディング法を使わないパッケージング方法の実装構造
のためパッケージの低コスト化がはかれ、ＩＣ上の電極
までの接続点数が１個減るために接続信頼性の向上が期
待される。また、リードフレームや基板が無い構造であ
るため従来のパッケージより小型、薄型になり、チップ
サイズに近い超小型パッケージが可能となる。As is clear from the above description, according to the present invention, the packaging cost is reduced due to the packaging structure of the packaging method that does not use the wire bonding method, and the number of connection points to the electrodes on the IC is reduced by one. Improved connection reliability is expected. Further, since the structure does not have a lead frame or a substrate, the package is smaller and thinner than the conventional package, and an ultra-small package close to a chip size is possible.
第１図は本考案における半導体装置の実装構造を示す平
面図、第２図(a)〜(c)は本考案における第１の実施例に
おける構成を得るための工程を説明する第１図のＡ−Ａ
断面図、第２図(d)は第２図(c)に対応する斜視図、第３
図(a)〜(c)は本考案における第２の実施例における構成
を得るための工程を説明する断面図、第４図は従来例に
おける半導体装置の実装構造を示す断面図、第５図およ
び第６図はいずれも従来例における半導体装置の実装構
造を示す平面図である。 １……半導体装置（ＩＣ）、 ３……絶縁樹脂、 ４……導体、 ５……プラスチック保護板、 ９……凹溝。FIG. 1 is a plan view showing a mounting structure of a semiconductor device according to the present invention, and FIGS. 2 (a) to 2 (c) are views for explaining a process for obtaining a configuration according to a first embodiment of the present invention. A-A
Sectional view, FIG. 2 (d) is a perspective view corresponding to FIG. 2 (c), and FIG.
(A) to (c) are cross-sectional views illustrating a process for obtaining the structure of the second embodiment of the present invention, and FIG. 4 is a cross-sectional view showing a mounting structure of a semiconductor device in a conventional example, and FIG. 6 and 7 are plan views showing the mounting structure of the semiconductor device in the conventional example. 1 ... Semiconductor device (IC), 3 ... Insulating resin, 4 ... Conductor, 5 ... Plastic protective plate, 9 ... Recessed groove.
Claims (1)
溝を有し、半導体装置の上面に配置するプラスチック保
護板と、 半導体装置の側面と下面とを被覆する絶縁樹脂と、 凹溝に設ける導体とを備え、 導体は電極部分から端面部までの全面がプラスチック保
護板から露出していることを特徴とする半導体装置の実
装構造。1. A plastic protective plate having a groove continuously provided from an electrode portion to an end face portion, the plastic protective plate being arranged on an upper surface of a semiconductor device, an insulating resin covering a side surface and a lower surface of the semiconductor device, and a groove A mounting structure for a semiconductor device, comprising: a conductor to be provided, wherein the entire surface of the conductor from the electrode portion to the end face portion is exposed from the plastic protective plate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987195704U JPH06821Y2 (en) | 1987-12-25 | 1987-12-25 | Semiconductor device mounting structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987195704U JPH06821Y2 (en) | 1987-12-25 | 1987-12-25 | Semiconductor device mounting structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01100443U JPH01100443U (en) | 1989-07-05 |
| JPH06821Y2 true JPH06821Y2 (en) | 1994-01-05 |
Family
ID=31486366
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1987195704U Expired - Lifetime JPH06821Y2 (en) | 1987-12-25 | 1987-12-25 | Semiconductor device mounting structure |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH06821Y2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5589314B2 (en) * | 2009-06-25 | 2014-09-17 | 株式会社リコー | Manufacturing method of electronic component module |
| JP6304700B2 (en) * | 2016-09-26 | 2018-04-04 | 株式会社パウデック | Semiconductor packages, modules and electrical equipment |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5437473B2 (en) * | 1971-09-09 | 1979-11-15 | ||
| JPS61220346A (en) * | 1985-03-26 | 1986-09-30 | Toshiba Corp | Semiconductor device and manufacture thereof |
-
1987
- 1987-12-25 JP JP1987195704U patent/JPH06821Y2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH01100443U (en) | 1989-07-05 |
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