JPH07283336A - Chip carrier - Google Patents
Chip carrierInfo
- Publication number
- JPH07283336A JPH07283336A JP6067154A JP6715494A JPH07283336A JP H07283336 A JPH07283336 A JP H07283336A JP 6067154 A JP6067154 A JP 6067154A JP 6715494 A JP6715494 A JP 6715494A JP H07283336 A JPH07283336 A JP H07283336A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- lead
- mounting
- connection
- chip carrier
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体集積回路素子
（以下、チップと称する）を搭載し、外部回路に接続す
るために用いるチップキャリアに関する。詳しくは、ボ
ール・グリッド・アレイ型（Ball Grid Array …以下、
ＢＧＡと称する）の半導体パッケージ向けのチップキャ
リアに関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a chip carrier for mounting a semiconductor integrated circuit element (hereinafter referred to as a chip) and connecting it to an external circuit. For more details, please refer to Ball Grid Array ...
(Referred to as BGA) for chip packages for semiconductor packages.
【０００２】[0002]
【従来の技術】従来、チップをプリント配線板などの外
部回路に接続するための代表的な装置として、クワッド
・フラット・パッケージ（Quad Flat Package …以下、
ＱＦＰと称する）がある。2. Description of the Related Art Conventionally, as a typical device for connecting a chip to an external circuit such as a printed wiring board, a quad flat package (hereinafter referred to as "quad flat package")
(Referred to as QFP).
【０００３】ＱＦＰは、パッケージの内部でチップとリ
ードフレームのインナー・リードとをワイヤボンディン
グ等により接続し、チップを含む領域を樹脂にてモール
ドしてパッケージとし、その四辺からリードフレームの
アウター・リードを引き出し、前記リードをガルウィン
グ状に形成し、外部回路と接続する方式の半導体パッケ
ージであり、最も広く普及している。（図３参照）In the QFP, the chip and the inner lead of the lead frame are connected by wire bonding or the like inside the package, the region including the chip is molded with resin to form a package, and the outer leads of the lead frame are formed from the four sides. Is a semiconductor package in which the lead is formed, the lead is formed in a gull wing shape, and the lead is connected to an external circuit, and is most widely used. (See Figure 3)
【０００４】昨今、新規な上記の接続用装置として、Ｂ
ＧＡ型の半導体パッケージが普及しつつある。Recently, as a new connecting device, the B
GA type semiconductor packages are becoming popular.
【０００５】前記パッケージは、特開昭59−172758号公
報に例示されるような、外部回路に直接的表面取付けが
できるリードレス・チップキャリヤに関するものであ
り、 複数のワイヤボンドパッド51によって取り囲まれたダ
イボンディング部位を有する上方のボンディング面。
（図５(a) 参照） 前記上方のボンディング面に対向し、内側のはんだパ
ッド52配列を含む下方のはんだ付け面。（図５(b) 参
照） 前記はんだパッド52の一部を前記ワイヤボンドパッド
51の一部に電気的に結合する手段53。（図５(c) 参照） 前記内側のはんだパッド52を取り囲んでいる前記下方
のはんだ付け面の絶縁性周辺部位54。（図５(c) 参照） を具えることを特徴とする。（図５参照）The package relates to a leadless chip carrier which can be directly surface-mounted on an external circuit, as exemplified in JP-A-59-172758, and is surrounded by a plurality of wire bond pads 51. An upper bonding surface having a die bonding site.
(See FIG. 5A) A lower soldering surface facing the upper bonding surface and including an inner solder pad 52 array. (See FIG. 5 (b)) A part of the solder pad 52 is used as the wire bond pad.
Means 53 for electrically coupling to a portion of 51. (See FIG. 5C) Insulating peripheral portion 54 of the lower soldering surface surrounding the inner solder pad 52. (See FIG. 5 (c)). (See Figure 5)
【０００６】また、これに似た形態の半導体パッケージ
として、上記はんだパッドの代わりに金属ピンを立てた
構造で、プリント配線板に予め形成したスルーホールに
挿入してはんだ付けすることで固定する、いわゆるピン
・グリッド・アレイ型（PinGrid Array…以下、ＰＧＡ
と称する）の半導体パッケージがある。（図４参照）Further, as a semiconductor package of a form similar to this, a structure in which metal pins are erected in place of the solder pads is inserted into a through hole previously formed in the printed wiring board and fixed by soldering. So-called pin grid array type (PGA)
There is a semiconductor package). (See Figure 4)
【０００７】なお、上記参照図面では、チップの端子の
数およびリードの本数が９個についての場合で説明を簡
略化している。In the above referenced drawings, the description is simplified when the number of terminals of the chip and the number of leads are nine.
【０００８】ＱＦＰに対してのＢＧＡの利点は、特に実
装密度の向上にあり、ＱＦＰを取り付けるのに必要な外
部回路基板の実質的面積よりも、ＢＧＡを取り付けるの
に必要な前記面積が大幅に小さくなる点にある。The advantage of the BGA over the QFP lies particularly in the increased packing density, in that the area required for mounting the BGA is significantly larger than the substantial area of the external circuit board required for mounting the QFP. It's getting smaller.
【０００９】一般的なＢＧＡ型の半導体パッケージは、
プリント配線板用の銅張積層板（エポキシ樹脂等からな
る絶縁性基材の両面または片面に、銅箔を貼り合わせた
もの）をベース材料（上記）とし、これをフォトエッ
チング法等の方法で加工して、チップ搭載部と配線部
（上記と）を形成している。A general BGA type semiconductor package is
A copper clad laminate for printed wiring boards (a copper foil is attached to both sides or one side of an insulating base material made of epoxy resin etc.) is used as a base material (above), and this is applied by a method such as photoetching. By processing, the chip mounting portion and the wiring portion (as described above) are formed.
【００１０】[0010]
【発明が解決しようとする課題】上記のようにベース材
料として銅張積層板を使用したＢＧＡ型の半導体装置で
は、広く一般的に使われているＱＦＰ型の半導体パッケ
ージ用の製造設備がそのまま使用できないため、ＢＧＡ
向けの製造設備が新たに必要となる。As described above, in the BGA type semiconductor device using the copper clad laminate as the base material, the manufacturing equipment for the QFP type semiconductor package, which is widely and generally used, is used as it is. I can't, so BGA
New manufacturing equipment is needed.
【００１１】また、ＢＧＡ型の半導体パッケージをプリ
ント配線板（外部回路）に接続する際、２３０〜２６０
℃程度に加熱してはんだボール（パッド）を溶融させる
必要があり、この時の熱で半導体パッケージとプリント
配線板（外部回路）の両方に反りが発生することによ
り、ボール状に形成した半導体装置上の端子（はんだパ
ッド）とプリント配線板上に形成したパッドとの間に隙
間が発生してしまうため、端子数がおよそ３００ピンを
越えるチップを搭載する場合には、全てのピンを安定し
て接続することが難しい。When the BGA type semiconductor package is connected to the printed wiring board (external circuit), 230 to 260 are used.
It is necessary to melt the solder balls (pads) by heating to about ℃, and the heat generated at this time causes warpage in both the semiconductor package and the printed wiring board (external circuit), resulting in a ball-shaped semiconductor device. Since a gap is created between the upper terminal (solder pad) and the pad formed on the printed wiring board, when mounting a chip with more than 300 pins, stabilize all pins. Difficult to connect.
【００１２】さらに、発熱量の大きいチップを使用する
場合も、上記ベース材料として樹脂を基本とする従来の
ＢＧＡでは、放熱性・接続信頼性の点で満足のいくもの
ではない。Further, even when a chip having a large heat generation amount is used, the conventional BGA based on resin as the base material is not satisfactory in terms of heat dissipation and connection reliability.
【００１３】そのため、端子数がおよそ３００ピン以上
のものや、発熱量の大きいチップを使用する場合には、
接続信頼性を向上させるために、ＰＧＡ型の半導体パッ
ケージに加工してチップを搭載することになるので、半
導体装置自体が高価になってしまうという問題がある。Therefore, when a chip having more than about 300 pins or a chip having a large heat generation is used,
In order to improve the connection reliability, the PGA type semiconductor package is processed and the chip is mounted, which causes a problem that the semiconductor device itself becomes expensive.
【００１４】本発明は上記問題を考慮して、従来から広
く使用されているＱＦＰ型の半導体装置の製造設備をそ
のまま使用でき、ＰＧＡ型の半導体装置より安価で、従
来のＢＧＡ型の半導体装置より放熱性・接続信頼性の高
い、新規なＢＧＡ型の半導体装置を達成するようなチッ
プキャリアを提供することを目的とする。In consideration of the above problems, the present invention can use the manufacturing equipment of the QFP type semiconductor device which has been widely used in the past as it is, is cheaper than the PGA type semiconductor device, and is more expensive than the conventional BGA type semiconductor device. It is an object of the present invention to provide a chip carrier that achieves a novel BGA type semiconductor device having high heat dissipation and connection reliability.
【００１５】[0015]
【課題を解決するための手段】請求項１に記載の本発明
は、半導体集積回路の搭載用金属板の表面に、前記搭載
部を除く形状に設けられた絶縁性シートを介して、所定
の導体パターンよりなるリードが配置されてなるチップ
キャリアであって、前記リードが、半導体集積回路素子
と接続される多数の始端より略放射状に外側に延びてお
り、それらの末端が前記絶縁性基材の表面に略マトリク
ス状に配置されており、個々の前記末端には、外部回路
との接続用の球状パッドが設けられていることを特徴と
する。According to a first aspect of the present invention, a predetermined metal plate for mounting a semiconductor integrated circuit is provided on a surface thereof with an insulating sheet provided in a shape excluding the mounting portion. A chip carrier in which leads made of a conductor pattern are arranged, wherein the leads extend substantially radially outward from a plurality of starting ends connected to a semiconductor integrated circuit element, and the ends thereof are the insulating base material. Are arranged in a substantially matrix on the surface of, and spherical pads for connection with an external circuit are provided at each of the ends.
【００１６】上記構成（絶縁性シートを介して所定の導
体パターンよりなるリードが配置された構成）とする理
由は、前記リードの一例を示す平面図（図２）からわか
るように、各リードの末端が略マトリクス状に配置され
ており、各リードが独立しているため、単層の金属板の
みを用いては成形できないので、絶縁性シートによって
各リードを支持する必要があるためである。The reason for adopting the above-mentioned structure (the structure in which the leads having the predetermined conductor pattern are arranged via the insulating sheet) is as understood from the plan view (FIG. 2) showing an example of the leads. This is because the ends are arranged in a substantially matrix shape and the leads are independent, so that the leads cannot be formed using only a single-layer metal plate, and therefore it is necessary to support the leads with an insulating sheet.
【００１７】請求項２に記載の発明は、前記リードの末
端部のみが露出するように、略マトリクス状に開口が存
在する絶縁性シートが、前記リードの表面に積層され、
前記開口部に外部回路との接続用の球状パッドが設けら
れた構成であることを特徴とする。According to a second aspect of the present invention, an insulating sheet having openings in a substantially matrix shape is laminated on the surface of the lead so that only the end portion of the lead is exposed.
It is characterized in that a spherical pad for connection with an external circuit is provided in the opening.
【００１８】請求項３に記載の発明は、前記接続用の球
状パッドとして、錫，錫−鉛合金，金とこれらの金属を
主成分とする合金のうち、２種以上の金属を積層した構
成のものを用い、前記末端部側に金を含む合金を配置
し、外側に錫または錫−鉛合金を配置したことを特徴と
する。According to a third aspect of the present invention, the spherical pad for connection is formed by laminating two or more kinds of metals among tin, tin-lead alloy, gold and alloys containing these metals as main components. The alloy containing gold is arranged on the end side and the tin or tin-lead alloy is arranged on the outside.
【００１９】請求項４に記載の発明は、前記導体パター
ンの末端部が、対応する箇所の前記絶縁性基材と１０μ
ｍ以上の間隔を隔てていることを特徴とする。According to a fourth aspect of the present invention, the end portion of the conductor pattern is 10 μm thick with the insulating base material at a corresponding position.
It is characterized in that they are separated by an interval of m or more.
【００２０】[0020]
【作用】ＱＦＰと同様に、４連または５連のフレーム状
（帯状のフレーム材料に、モジュールが４つまたは５つ
ある構成）として、この状態でチップの搭載からパッケ
ージングまでが行なえるようになり、また、従来のＢＧ
Ａと異なり、配線パターンであるリード自体が剛性を有
する厚さであり、リードが主体な構成であるため、既存
のＱＦＰの製造設備がそのまま適用でき、ＢＧＡ型の半
導体パッケージが製造できる。[Function] Similar to QFP, four or five frames are formed (band-shaped frame material has four or five modules) so that chip mounting to packaging can be performed in this state. Also, conventional BG
Unlike A, the lead itself, which is a wiring pattern, has a thickness having rigidity, and since the lead is the main constituent, the existing QFP manufacturing equipment can be applied as it is, and a BGA type semiconductor package can be manufactured.
【００２１】また、導体パターンからなるリードを絶縁
性シートを介して形成したことにより、導体パターンの
電気特性（インピーダンス・インダクタンス等）を改善
することも可能となる。Further, by forming the lead consisting of the conductor pattern via the insulating sheet, it is possible to improve the electrical characteristics (impedance, inductance, etc.) of the conductor pattern.
【００２２】また、チップ搭載部を金属材料にて成形す
ることにより、チップからの発熱を直接金属部で放散で
きるようになり、放熱特性も向上する。Further, by molding the chip mounting portion with a metal material, the heat generated from the chip can be directly dissipated by the metal portion, and the heat dissipation characteristics are also improved.
【００２３】さらに、接続用パッドとしてボール状のは
んだパッドを用いると、外部回路との接続が確実となる
が、加熱・加圧によるボールの溶融に起因する隣合う配
線との短絡の問題が、前記パッドの層構成を改善したこ
とと、前記パッドの形成部に対応した開口を有する絶縁
性シートを介したことで改善される。Further, when a ball-shaped solder pad is used as the connection pad, connection with an external circuit is ensured, but there is a problem of short circuit between adjacent wirings due to melting of the ball due to heating / pressurization. It is improved by improving the layer structure of the pad and by interposing an insulating sheet having an opening corresponding to the pad forming portion.
【００２４】加えて、リードの末端部が対応する箇所の
絶縁性基材と１０μｍ以上の間隔を隔てていることによ
り、外部回路との接続の際の反り等に起因する接続部の
凹凸を吸収することが可能になる。In addition, since the ends of the leads are separated from the corresponding insulating base material by a distance of 10 μm or more, irregularities of the connecting portion due to warpage at the time of connection with an external circuit are absorbed. It becomes possible to do.
【００２５】[0025]
(1) リード材料の前処理 ニッケル約４２％を含有する厚さ１５０μｍの鉄−ニッ
ケル合金の条（ＹＥＦ−４２（商品名）；日立金属
（株）製）をリード材料とし、前記材料を７０℃に加熱
したアルカリ脱脂液（エークスリーン（商品名）；奥野
製薬（株）製を水に溶解させたもの）に１０分間浸漬
し、約５０℃の湯で攪拌しながら２分間洗浄し、さらに
約２０℃の水に２分間浸漬し、水を交換して再び２分間
浸漬した。(1) Pretreatment of lead material A 150 μm thick iron-nickel alloy strip (YEF-42 (trade name); manufactured by Hitachi Metals, Ltd.) containing about 42% nickel was used as a lead material, Immerse in alkaline degreasing liquid (Aksuline (trade name); product of Okuno Seiyaku Co., Ltd. dissolved in water) heated to ℃ for 10 minutes, wash with hot water at about 50 ℃ for 2 minutes, and further about It was immersed in water at 20 ° C. for 2 minutes, the water was exchanged, and it was immersed again for 2 minutes.
【００２６】次に、リード材料を約２０℃の５％塩酸に
３０〜６０秒間浸漬し、その後、約２０℃の水に１分間
浸漬し、別の槽に溜めておいた約２０℃の純水に１分間
浸漬して取り出した後、乾燥空気を吹きつけて表面の水
滴を完全に除去した。Next, the lead material was dipped in 5% hydrochloric acid at about 20 ° C. for 30 to 60 seconds, then dipped in water at about 20 ° C. for 1 minute, and pure water at about 20 ° C. stored in another tank. After immersing in water for 1 minute and taking it out, dry air was blown to completely remove water drops on the surface.
【００２７】前記材料を、予め８０℃に加熱しておいた
オーブンに入れ、１０分後に取り出し、すぐにデシケー
タに入れて温度が３０℃以下になるまでそのまま放置し
た。The above materials were placed in an oven preheated to 80 ° C., taken out after 10 minutes, immediately placed in a desiccator and allowed to stand until the temperature became 30 ° C. or lower.
【００２８】(2) リードの成形（レジスト・パターンの
形成） 前記材料を、約６０分後、デシケータから取り出し、塗
布・乾燥後の膜厚が約１０μｍになるように、ネガ型液
状レジスト（ＰＭＥＲ Ｎ−ＨＣ４０（商品名）；東京
応化（株）製）をディップコータで表面に塗布した。約
７０℃のオーブンに３０分間入れて、表面に塗布したレ
ジストがベトつかなくなるまで乾燥させた。(2) Lead Molding (Formation of Resist Pattern) After about 60 minutes, the above material was taken out from the desiccator, and a negative type liquid resist (PMER) was formed so that the film thickness after coating and drying was about 10 μm. N-HC40 (trade name); manufactured by Tokyo Ohka Co., Ltd.) was applied on the surface with a dip coater. It was placed in an oven at about 70 ° C. for 30 minutes and dried until the resist applied to the surface became non-sticky.
【００２９】次いで、前記材料にパターンマスクを重ね
合わせ、両面露光機（ＨＭＷ５３２Ｄ（商品名）；オー
ク（株）製）にセットして、紫外線を約１００mJ/cm2照
射して、被照射部のレジストを現像液に不溶な状態に変
化させた。Then, a pattern mask is superposed on the above material, set in a double-sided exposure machine (HMW532D (trade name); manufactured by Oak Co., Ltd.), and irradiated with ultraviolet rays of about 100 mJ / cm 2 to irradiate the irradiated portion. The resist was changed to be insoluble in the developer.
【００３０】レジスト・パターンは、成形後のリード・
パターンであり、チップと接続される多数の始端より略
放射状に外側に延びており、それらの末端が略マトリク
ス状に配置されており、必要に応じて、前記末端部が、
他の導体部より幅が広く、円形または多角形もしくはこ
れに類似する形状となるようにパターニングする。The resist pattern is a lead pattern after molding.
It is a pattern and extends outward in a substantially radial manner from a large number of starting ends connected to the chip, and their ends are arranged in a substantially matrix form.
Patterning is performed so that it is wider than other conductors and has a circular shape, a polygonal shape, or a shape similar thereto.
【００３１】さらに、５％のトリエタノールアミン溶液
に浸漬し、１０秒に１〜２回の割合で揺動しながら２分
後に取り出し、現像液が表面に残らなくなるまで水で洗
浄した。さらに、純水で洗浄し、約４０℃の乾燥空気を
吹きつけて水分を完全に飛ばし、表面を乾燥させた。そ
の後、前記材料を、予め１１０℃に加熱しておいたオー
ブンに入れ、エッチング液で剥離したり溶解したりしな
いようにレジストを十分に硬化させた。Further, it was immersed in a 5% triethanolamine solution, shaken at a rate of 1 to 2 times for 10 seconds, taken out after 2 minutes, and washed with water until no developer remained on the surface. Further, it was washed with pure water, and dried air at about 40 ° C. was blown to completely remove water, thereby drying the surface. Then, the material was placed in an oven preheated to 110 ° C., and the resist was sufficiently cured so as not to be peeled off or dissolved by an etching solution.
【００３２】(3) リードの成形（金属材料のエッチング
成形） 前記材料に、５０℃の塩化第二鉄をスプレーで吹きつ
け、レジストで覆われていない部分の鉄−ニッケル合金
を腐食させて除去した。材料表面に付着した塩化第二鉄
液を良く落としてから、約３０℃の水をスプレーで吹き
つけて塩化第二鉄液を完全に洗い流した。次いで、乾燥
空気を吹きつけて表面に付着した水分を飛ばした後、５
０℃に加熱した水酸化ナトリウム５％溶液に約２分間浸
漬し、レジストを膨潤させて除去し、３０℃の水で良く
洗浄して乾燥させた。以上、(1) 〜(3) の工程により、
例えば図２に示すようなリード部材20を得た。(3) Molding of Lead (Etching of Metal Material) Ferric chloride at 50 ° C. is sprayed on the material to corrode and remove the iron-nickel alloy in the area not covered with the resist. did. After the ferric chloride solution adhering to the surface of the material was well dropped, water at about 30 ° C. was sprayed to completely wash away the ferric chloride solution. Then, dry air is blown to remove the moisture adhering to the surface, and then 5
The resist was swollen and removed by immersing it in a 5% sodium hydroxide solution heated to 0 ° C. for about 2 minutes, washed well with water at 30 ° C. and dried. Above, by the steps (1) to (3),
For example, a lead member 20 as shown in FIG. 2 was obtained.
【００３３】(4) チップ搭載用金属板の成形 上記とは別に、厚さ約０．５mmの銅板の中央部の縦横約
２０mmを除いた部分を絞り加工して、深さ約０．７mmの
窪みを形成し、チップ搭載部とした。(4) Molding of metal plate for mounting chips Separately from the above, a copper plate having a thickness of about 0.5 mm is drawn by drawing the central part except about 20 mm in length and width, and having a depth of about 0.7 mm. A depression was formed and used as a chip mounting portion.
【００３４】次に、窪み部分の外側部に、絶縁性シート
となる厚さ６０μｍのエポキシ系接着シート（ＹＥＦ−
０４０（商品名）；三菱油化（株）製）を重ね、約１０
０℃の熱板で２〜５kg／cm2 の圧力を約１０秒間加え
て、チップ搭載部と絶縁性基材とを貼り合せ、チップ搭
載用金属板11を得た。（図１参照）Next, an epoxy adhesive sheet (YEF-) having a thickness of 60 μm, which serves as an insulating sheet, is provided on the outer side of the recessed portion.
040 (trade name); made by Mitsubishi Petrochemical Co., Ltd.
A chip mounting portion and an insulating base material were bonded together by applying a pressure of 2 to 5 kg / cm 2 with a hot plate at 0 ° C. for about 10 seconds to obtain a chip mounting metal plate 11. (See Figure 1)
【００３５】この際、エポキシ系接着シート（絶縁性基
材）を任意のパターン状とすることによって、後工程に
おいて、リード部材と積層した場合に、リード・パター
ンの末端部の接続用パッド部分がチップ搭載用金属板と
離間（シートの厚さ分）した構成とすることができる。At this time, the epoxy-based adhesive sheet (insulating base material) is formed into an arbitrary pattern, so that when it is laminated with the lead member in the subsequent step, the connecting pad portion at the end of the lead pattern is formed. It can be configured to be separated from the chip mounting metal plate (by the thickness of the sheet).
【００３６】(5) チップキャリアの製造（以下、図１参
照） チップ搭載用金属板11に設けられた絶縁性基材（接着シ
ート）12側の面に、リード部材20を位置合わせして重
ね、そのまま２〜５kg／cm2 の圧力を加えながら、１８
０℃に加熱し、両者を貼り合わせた。約３０分後、冷却
して取り出した。(5) Manufacture of chip carrier (refer to FIG. 1 below) The lead member 20 is aligned and superposed on the surface of the chip mounting metal plate 11 on the side of the insulating base material (adhesive sheet) 12 , While applying pressure of 2-5 kg / cm 2 as it is, 18
It heated at 0 degreeC and bonded both. After about 30 minutes, it was cooled and taken out.
【００３７】リード部材20とチップ搭載用金属板11の導
体部とを電気的に接続させることが必要な箇所には、予
め接続用の穴30を形成しておいた。両者の貼り合わせ
後、この穴30に銅粉を含む導電ペースト（ＮＦ２０００
（商品名）；タツタ電線（株）製）を充填し、１５０℃
で３０分間加熱してペーストを硬化させた。Holes 30 for connection are preliminarily formed at locations where it is necessary to electrically connect the lead member 20 and the conductor portion of the chip mounting metal plate 11. After bonding the both, a conductive paste containing copper powder (NF2000
(Product name); filled with Tatsuta Electric Wire Co., Ltd., 150 ° C
To heat the paste for 30 minutes to cure the paste.
【００３８】(6) 接続用パッドの形成 次に、リード部材20のリード末端部以外を覆うための絶
縁性樹脂（プロビマー５２（商品名）；チバガイギー
製）を、リード部材20のある面に塗布し、そのまま室温
で乾燥させた。(6) Formation of Connection Pads Next, an insulating resin (provimer 52 (trade name); manufactured by Ciba Geigy) for covering the lead members 20 other than the lead end portions is applied to the surface having the lead members 20. And dried at room temperature.
【００３９】次いで、８０℃で約１０分間加熱し、樹脂
中に含まれる溶剤を揮発させ、表面に塗布したレジスト
がベトつかなくなるまで乾燥させた。Next, it was heated at 80 ° C. for about 10 minutes to volatilize the solvent contained in the resin and dry it until the resist coated on the surface became non-sticky.
【００４０】その後、開口部分がリード部材20のリード
末端部に対応するパターンマスクを重ね合わせ、両面露
光機（ＨＭＷ５３２Ｄ（商品名）；オーク（株）製）に
セットして、紫外線を約７０００ｍＪ／cm2 照射して、
被照射部の樹脂を現像液に不溶な状態に変化させた。次
いで、現像処理によって、紫外線の当たらなかった部分
の樹脂を溶解させて除去した。１４０℃で３０分間加熱
して樹脂を完全に硬化させた。After that, a pattern mask whose opening corresponds to the lead end of the lead member 20 is overlaid and set in a double-sided exposure machine (HMW532D (trade name); manufactured by Oak Co.) to emit ultraviolet rays of about 7,000 mJ / irradiate cm 2
The resin in the irradiated area was changed to a state insoluble in the developing solution. Then, by a developing treatment, the resin in the portion not exposed to the ultraviolet rays was dissolved and removed. The resin was completely cured by heating at 140 ° C. for 30 minutes.
【００４１】樹脂を除去した部分にディスペンサで、は
んだクリーム（ＳＱ−１０３２０ＳＨＺ（商品名）；
（株）タムラ製作所製）を塗布し、ＩＲリフロー装置
（ＲＦ−３３０（商品名）；日本パルス技研（株）製）
で２３０℃、約１分間加熱してはんだクリームを溶融さ
せた。このまま冷却し洗浄することによって、球状のは
んだパッド40をリード部材20の導体パターンの外部端子
上に形成した。A solder cream (SQ-10320SHZ (trade name);
IR reflow device (RF-330 (trade name); manufactured by Nippon Pulse Giken Co., Ltd.)
At 230 ° C. for about 1 minute to melt the solder cream. The ball-shaped solder pad 40 was formed on the external terminal of the conductor pattern of the lead member 20 by cooling and washing as it was.
【００４２】この際、はんだパッドを複層構成とするこ
とも任意である。例えば、錫，錫−鉛合金，金とこれら
の金属を主成分とする合金のうち、２種以上の金属を積
層した構成とし、前記末端部側に金を含む合金のような
高融点の金属を配置し、外側に錫または錫−鉛合金を配
置することで、外側のはんだは接続に寄与し、内側のは
んだは接続の際の加熱・加圧によってもつぶれない剛性
を有するものであり、隣り合うリードとの短絡が防止さ
れる。At this time, the solder pad may have a multi-layer structure. For example, a metal having a high melting point such as tin, a tin-lead alloy, gold, and an alloy containing these metals as a main component, in which two or more kinds of metals are laminated, and an alloy containing gold on the end side. By arranging, and arranging tin or a tin-lead alloy on the outside, the solder on the outside contributes to the connection, and the solder on the inside has a rigidity that is not crushed even by heating / pressurization at the time of connection, A short circuit with adjacent leads is prevented.
【００４３】(7) チップの搭載 次に、チップ搭載用金属板11の中央部に形成した窪み
（チップ搭載箇所）に銀ペースト（ＣＲＮ−１０２２
（商品名）；住友ベークライト（株）製）を塗布し、チ
ップを乗せ、２００℃で３０分間加熱することにより、
銀ペーストを硬化してチップを固定させた。これらの一
連の操作はダイボンディング装置で行った。(7) Mounting of Chip Next, silver paste (CRN-1022) is placed in the recess (chip mounting location) formed in the central portion of the chip mounting metal plate 11.
(Trade name); by applying Sumitomo Bakelite Co., Ltd., put a chip, and heat at 200 ° C. for 30 minutes,
The silver paste was cured to fix the chips. These series of operations were performed by the die bonding apparatus.
【００４４】(8) 半導体パッケージの製造 チップ上の電極とリード部材20との電気的な接続を、ワ
イヤーボンダを用いて直径３０μｍの金線で行った。ま
た、チップ上のグランド電極は、チップ搭載用金属板11
の導体部と接続させた。(8) Manufacture of semiconductor package The electrodes on the chip and the lead members 20 were electrically connected with a gold wire having a diameter of 30 μm using a wire bonder. In addition, the ground electrode on the chip is the metal plate 11
It was connected to the conductor part of.
【００４５】なお、電気的に接続できる方法であれば、
ワイヤーボンディングによる方法に限定する必要はな
く、導電ペーストによる方法やバンプを使用する方式で
も良い。If it can be electrically connected,
The method is not limited to the method using wire bonding, and a method using a conductive paste or a method using bumps may be used.
【００４６】金線と半導体素子を保護するため、封止用
樹脂を任意の方法（例えば、ディスペンサやトランスフ
ァ・モールド）で塗布し、１８０℃で３０分間加熱して
樹脂を硬化させ、その後、フレームとの接続部を金型で
切断して半導体パッケージを得た。In order to protect the gold wire and the semiconductor element, a sealing resin is applied by an arbitrary method (for example, a dispenser or transfer mold) and heated at 180 ° C. for 30 minutes to cure the resin, and then the frame. The connection portion with and was cut with a mold to obtain a semiconductor package.
【００４７】[0047]
【発明の効果】ＱＦＰ型の半導体装置の製造設備をその
まま使用でき、ＰＧＡ型の半導体装置より安価で、既存
のＢＧＡ型の半導体装置より放熱性・接続信頼性の高
い、新規なＢＧＡ型の半導体装置を達成するようなチッ
プキャリアが提供された。Industrial Applicability A novel BGA type semiconductor that can use the QFP type semiconductor device manufacturing equipment as it is, is cheaper than the PGA type semiconductor device, and has higher heat dissipation and connection reliability than the existing BGA type semiconductor device. A chip carrier was provided to complete the device.
【図１】本発明のチップキャリアの断面説明図。FIG. 1 is a sectional explanatory view of a chip carrier of the present invention.
【図２】本発明のチップキャリアを形成するリード部材
の一例を示す平面図。FIG. 2 is a plan view showing an example of a lead member forming the chip carrier of the present invention.
【図３】従来のチップキャリア（ＱＦＰ）の説明図。FIG. 3 is an explanatory diagram of a conventional chip carrier (QFP).
【図４】従来のチップキャリア（ＰＧＡ）の説明図。FIG. 4 is an explanatory diagram of a conventional chip carrier (PGA).
【図５】従来のＢＧＡ方式のチップキャリアのの説明
図。FIG. 5 is an explanatory diagram of a conventional BGA type chip carrier.
10…チップキャリア 11…チップ搭載用金属板 12…絶縁性基材 20…リード部材 40…はんだパッド 50…ＢＧＡ型の半導体パッケージ 10 ... Chip carrier 11 ... Chip mounting metal plate 12 ... Insulating substrate 20 ... Lead member 40 ... Solder pad 50 ... BGA type semiconductor package
Claims (4)
前記搭載部を除く形状に設けられた絶縁性シートを介し
て、所定の導体パターンよりなるリードが配置されてな
るチップキャリアであって、 前記リードが、半導体集積回路素子と接続される多数の
始端より略放射状に外側に延びており、それらの末端が
前記絶縁性基材の表面に略マトリクス状に配置されてお
り、個々の前記末端には、外部回路との接続用の球状パ
ッドが設けられていることを特徴とするチップキャリ
ア。1. A surface of a metal plate for mounting a semiconductor integrated circuit,
A chip carrier in which leads made of a predetermined conductor pattern are arranged via an insulating sheet provided in a shape excluding the mounting portion, wherein the leads are connected to a semiconductor integrated circuit element at a large number of starting ends. More substantially radially outwardly, their ends are arranged on the surface of the insulating substrate in a substantially matrix form, and each of the ends is provided with a spherical pad for connection with an external circuit. Is a chip carrier.
に、略マトリクス状に開口が存在する絶縁性シートが、
前記リードの表面に積層され、前記開口部に外部回路と
の接続用パッドが設けられた構成の請求項１または請求
項２に記載のチップキャリア。2. An insulating sheet having openings in a substantially matrix shape so that only the end portions of the leads are exposed,
The chip carrier according to claim 1 or 2, wherein the chip is laminated on the surface of the lead, and a pad for connection to an external circuit is provided in the opening.
鉛合金，金とこれらの金属を主成分とする合金のうち、
２種以上の金属を積層した構成のものを用い、前記末端
部側に金を含む合金を配置し、外側に錫または錫−鉛合
金を配置したことを特徴とする請求項１〜請求項３の何
れかに記載のチップキャリア。3. The spherical pad for connection comprises tin, tin-
Of lead alloys, gold and alloys containing these metals as main components,
4. An alloy containing two or more metals is used, an alloy containing gold is arranged on the end side, and tin or a tin-lead alloy is arranged on the outside. The chip carrier according to any one of 1.
所の前記絶縁性基材と１０μｍ以上の間隔を隔てている
ことを特徴とする請求項１〜請求項４の何れかに記載の
チップキャリア。4. The chip according to claim 1, wherein an end portion of the conductor pattern is separated from the insulating base material at a corresponding position by a distance of 10 μm or more. Career.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6715494A JP3617072B2 (en) | 1994-04-05 | 1994-04-05 | Chip carrier |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6715494A JP3617072B2 (en) | 1994-04-05 | 1994-04-05 | Chip carrier |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH07283336A true JPH07283336A (en) | 1995-10-27 |
| JP3617072B2 JP3617072B2 (en) | 2005-02-02 |
Family
ID=13336708
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6715494A Expired - Fee Related JP3617072B2 (en) | 1994-04-05 | 1994-04-05 | Chip carrier |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3617072B2 (en) |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH11191602A (en) * | 1997-12-26 | 1999-07-13 | Nec Corp | Semiconductor device and its manufacture |
| JPH11284092A (en) * | 1998-03-27 | 1999-10-15 | Mitsui High Tec Inc | Semiconductor device |
| EP1079433A2 (en) * | 1999-08-27 | 2001-02-28 | Texas Instruments Incorporated | Ball grid array package having two ground levels |
| WO2002045164A3 (en) * | 2000-12-01 | 2003-03-27 | Broadcom Corp | Thermally and electrically enhanced ball grid array packaging |
| US6559536B1 (en) | 1999-12-13 | 2003-05-06 | Fujitsu Limited | Semiconductor device having a heat spreading plate |
| US6876553B2 (en) | 2002-03-21 | 2005-04-05 | Broadcom Corporation | Enhanced die-up ball grid array package with two substrates |
| US6879039B2 (en) | 2001-12-18 | 2005-04-12 | Broadcom Corporation | Ball grid array package substrates and method of making the same |
| US7239024B2 (en) * | 2003-04-04 | 2007-07-03 | Thomas Joel Massingill | Semiconductor package with recess for die |
| WO2008073084A1 (en) * | 2006-12-12 | 2008-06-19 | Agere Systems, Inc. | An integrated circuit package and a method for dissipating heat in an integrated circuit package |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6286848A (en) * | 1985-10-14 | 1987-04-21 | Matsushita Electric Works Ltd | Chip carrier |
| JPS63307762A (en) * | 1987-06-09 | 1988-12-15 | Mitsubishi Electric Corp | Semiconductor device |
| JPH0358455A (en) * | 1989-07-26 | 1991-03-13 | Matsushita Electric Works Ltd | Semiconductor package |
| JPH03297152A (en) * | 1990-04-16 | 1991-12-27 | Hitachi Chem Co Ltd | Manufacture of semiconductor device |
| JPH04277636A (en) * | 1991-03-05 | 1992-10-02 | Shinko Electric Ind Co Ltd | Preparation of semiconductor device |
| JPH05144980A (en) * | 1991-11-25 | 1993-06-11 | Sumitomo Bakelite Co Ltd | Manufacture of semiconductor loading substrate |
| JPH05218228A (en) * | 1992-02-04 | 1993-08-27 | Ibiden Co Ltd | Substrate for electronic component mounting use |
| JPH0645401A (en) * | 1992-07-23 | 1994-02-18 | Nec Corp | Package for semiconductor device |
-
1994
- 1994-04-05 JP JP6715494A patent/JP3617072B2/en not_active Expired - Fee Related
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6286848A (en) * | 1985-10-14 | 1987-04-21 | Matsushita Electric Works Ltd | Chip carrier |
| JPS63307762A (en) * | 1987-06-09 | 1988-12-15 | Mitsubishi Electric Corp | Semiconductor device |
| JPH0358455A (en) * | 1989-07-26 | 1991-03-13 | Matsushita Electric Works Ltd | Semiconductor package |
| JPH03297152A (en) * | 1990-04-16 | 1991-12-27 | Hitachi Chem Co Ltd | Manufacture of semiconductor device |
| JPH04277636A (en) * | 1991-03-05 | 1992-10-02 | Shinko Electric Ind Co Ltd | Preparation of semiconductor device |
| JPH05144980A (en) * | 1991-11-25 | 1993-06-11 | Sumitomo Bakelite Co Ltd | Manufacture of semiconductor loading substrate |
| JPH05218228A (en) * | 1992-02-04 | 1993-08-27 | Ibiden Co Ltd | Substrate for electronic component mounting use |
| JPH0645401A (en) * | 1992-07-23 | 1994-02-18 | Nec Corp | Package for semiconductor device |
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH11191602A (en) * | 1997-12-26 | 1999-07-13 | Nec Corp | Semiconductor device and its manufacture |
| US6111311A (en) * | 1997-12-26 | 2000-08-29 | Nec Corporation | Semiconductor device and method of forming the same |
| JPH11284092A (en) * | 1998-03-27 | 1999-10-15 | Mitsui High Tec Inc | Semiconductor device |
| EP1079433A3 (en) * | 1999-08-27 | 2004-03-03 | Texas Instruments Incorporated | Ball grid array package having two ground levels |
| EP1079433A2 (en) * | 1999-08-27 | 2001-02-28 | Texas Instruments Incorporated | Ball grid array package having two ground levels |
| US6559536B1 (en) | 1999-12-13 | 2003-05-06 | Fujitsu Limited | Semiconductor device having a heat spreading plate |
| US6796024B2 (en) | 1999-12-13 | 2004-09-28 | Fujitsu Limited | Method for making semiconductor device |
| WO2002045164A3 (en) * | 2000-12-01 | 2003-03-27 | Broadcom Corp | Thermally and electrically enhanced ball grid array packaging |
| US6879039B2 (en) | 2001-12-18 | 2005-04-12 | Broadcom Corporation | Ball grid array package substrates and method of making the same |
| US6876553B2 (en) | 2002-03-21 | 2005-04-05 | Broadcom Corporation | Enhanced die-up ball grid array package with two substrates |
| US7239024B2 (en) * | 2003-04-04 | 2007-07-03 | Thomas Joel Massingill | Semiconductor package with recess for die |
| WO2008073084A1 (en) * | 2006-12-12 | 2008-06-19 | Agere Systems, Inc. | An integrated circuit package and a method for dissipating heat in an integrated circuit package |
| US8859333B2 (en) | 2006-12-12 | 2014-10-14 | Lsi Corporation | Integrated circuit package and a method for dissipating heat in an integrated circuit package |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3617072B2 (en) | 2005-02-02 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6048755A (en) | Method for fabricating BGA package using substrate with patterned solder mask open in die attach area | |
| TWI316749B (en) | Semiconductor package and fabrication method thereof | |
| US6670219B2 (en) | Method of fabricating a CDBGA package | |
| JP3541491B2 (en) | Electronic components | |
| JP2003318327A (en) | Printed wiring board and stacked package | |
| KR20000006421A (en) | Semiconductor device | |
| JP3617072B2 (en) | Chip carrier | |
| JP2002043467A (en) | Board for semiconductor package, its manufacturing method, semiconductor package using board and manufacturing method of semiconductor package | |
| JP5000105B2 (en) | Semiconductor device | |
| JPH11163024A (en) | Semiconductor device and lead frame for assembling the same, and manufacture of the device | |
| JP3513983B2 (en) | Manufacturing method of chip carrier | |
| JP3522403B2 (en) | Semiconductor device | |
| JPH104151A (en) | Semiconductor device and its manufacture | |
| JP3417292B2 (en) | Semiconductor device | |
| JP2936540B2 (en) | Circuit board, method of manufacturing the same, and method of manufacturing semiconductor package using the same | |
| JP2000082760A (en) | Semiconductor device | |
| JP3003510B2 (en) | Method for forming electrode part of wiring board | |
| JPH11233673A (en) | Semiconductor device, its manufacture, and electronic device | |
| JP3932771B2 (en) | Manufacturing method of semiconductor chip mounting substrate and manufacturing method of semiconductor device | |
| JP2003332495A (en) | Method of manufacturing semiconductor device | |
| JPH06291246A (en) | Multi-chip semiconductor device | |
| JPH0358455A (en) | Semiconductor package | |
| JPH1167953A (en) | Semiconductor device | |
| JP2003332491A (en) | Semiconductor device | |
| JPH11330301A (en) | Semiconductor device and its mounting structure, resin wiring board and its manufacture |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20040130 |
|
| A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20040406 |
|
| A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20040602 |
|
| A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20040706 |
|
| A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20040906 |
|
| TRDD | Decision of grant or rejection written | ||
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20041019 |
|
| A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20041101 |
|
| R150 | Certificate of patent or registration of utility model |
Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20071119 Year of fee payment: 3 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20081119 Year of fee payment: 4 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20091119 Year of fee payment: 5 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20091119 Year of fee payment: 5 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20101119 Year of fee payment: 6 |
|
| LAPS | Cancellation because of no payment of annual fees |