JP3513983B2 - Manufacturing method of chip carrier - Google Patents

Manufacturing method of chip carrier

Info

Publication number
JP3513983B2
JP3513983B2 JP15473195A JP15473195A JP3513983B2 JP 3513983 B2 JP3513983 B2 JP 3513983B2 JP 15473195 A JP15473195 A JP 15473195A JP 15473195 A JP15473195 A JP 15473195A JP 3513983 B2 JP3513983 B2 JP 3513983B2
Authority
JP
Japan
Prior art keywords
chip carrier
chip
hole
layer
metal plate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP15473195A
Other languages
Japanese (ja)
Other versions
JPH0897330A (en
Inventor
健人 塚本
秀克 関根
俊雄 大房
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toppan Inc
Original Assignee
Toppan Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toppan Inc filed Critical Toppan Inc
Priority to JP15473195A priority Critical patent/JP3513983B2/en
Publication of JPH0897330A publication Critical patent/JPH0897330A/en
Application granted granted Critical
Publication of JP3513983B2 publication Critical patent/JP3513983B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/05—Insulated conductive substrates, e.g. insulated metal substrate
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H05K3/425—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern
    • H05K3/427—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern initial plating of through-holes in metal-clad substrates
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【産業上の利用分野】本発明は、半導体集積回路素子
（以下、チップと称する）を一つ、あるいは、複数個搭
載し、プリント配線板に接続するために用いるチップキ
ャリア、特に、プリント配線基板との接続端子を面上に
配置したボール・グリッド・アレイ（Ball Grid Array
…以下、ＢＧＡと称する）構造を有するチップキャリア
に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a chip carrier used to connect one or a plurality of semiconductor integrated circuit elements (hereinafter referred to as "chips") to a printed wiring board, and particularly to a printed wiring board. Ball grid array (connecting terminals to and on the surface)
(Hereinafter, referred to as BGA) structure.

【０００２】[0002]

【従来の技術】電子機器の小型化の要求に対応するた
め、チップを搭載した半導体装置をプリント配線板表面
上に実装する方式がとられてきた。従来、代表的な表面
実装方式として、クワッド・フラット・パッケージ（Qu
ad Flat Package …以下、ＱＦＰと称する）があげられ
る。2. Description of the Related Art In order to meet the demand for miniaturization of electronic equipment, there has been adopted a method of mounting a semiconductor device having a chip on the surface of a printed wiring board. Conventionally, as a typical surface mounting method, a quad flat package (Qu
ad Flat Package ... Hereafter, referred to as QFP).

【０００３】ＱＦＰは図５に示すように、リードフレー
ムのダイパッド上にチップが搭載され、インナー・リー
ドと金線等にてワイヤボンディング接続し、チップ近辺
はモールド樹脂にて樹脂封止され、その四辺からガルウ
ィング状のアウターリードが伸び、外部端子と半田付け
によって実装される。As shown in FIG. 5, in QFP, a chip is mounted on a die pad of a lead frame, and wire bonding connection is made with an inner lead and a gold wire, and the vicinity of the chip is resin-sealed with a mold resin. Gull wing-shaped outer leads extend from the four sides and are mounted by soldering to external terminals.

【０００４】近年、ゲートアレイ等ＡＳＩＣの分野では
チップの端子数が増加の傾向にあるが、パッケージサイ
ズは現状レベルか縮小の要求が高い。このため、アウタ
ーリードのピッチは０．５ｍｍから０．３ｍｍへ狭まる
方向にある。アウターリードピッチが０．３ｍｍのＱＦ
Ｐでは、半田ブリッジ等の問題が発生し、プリント配線
板等の外部接続端子への実装が困難になると言われてい
る。In recent years, in the field of ASICs such as gate arrays, the number of chip terminals has been increasing, but there is a strong demand for the package size to be at the current level or to be reduced. Therefore, the pitch of the outer leads is narrowed from 0.5 mm to 0.3 mm. QF with outer lead pitch of 0.3 mm
It is said that with P, a problem such as a solder bridge occurs and it becomes difficult to mount it on an external connection terminal such as a printed wiring board.

【０００５】なお、本明細書においては、「パッケー
ジ」も「チップキャリア」も、チップを搭載して外部回
路（プリント配線板）に接続させるという基本的機能は
同一であり、その意味においては同義語であると言え、
以後、混在して用いることとする。In this specification, both the "package" and the "chip carrier" have the same basic function of mounting a chip and connecting the chip to an external circuit (printed wiring board). A word,
Hereinafter, they will be used in a mixed manner.

【０００６】昨今、新規な上記の接続用装置として、Ｂ
ＧＡ型のチップキャリアが普及しつつある。前記装置
は、特開昭５９−１７２７５８号公報に例示されるよう
な、外部回路に直接的表面取付けができるリードレス・
チップキャリアに関するものであり、 複数のワイヤボンドパッド５１によって取り囲まれた
ダイボンディング部位を有する上方のボンディング面
（図７（ａ）参照）。 前記上方のボンディング面に対向し、内側のはんだパ
ッド５２配列を含む下方のはんだ付け面（図７（ｂ）参
照）。 前記はんだパッド５２の一部を前記ワイヤボンドパッ
ド５１の一部に電気的に結合する手段５３（図７（ｃ）
参照）。 前記内側のはんだパッド５２を取り囲んでいる前記下
方のはんだ付け面の絶縁性周辺部位５４（図７（ｃ）参
照）を具えることを特徴とする。Recently, as a new connecting device, the B
GA type chip carriers are becoming popular. The device is a leadless type device that can be directly surface-mounted on an external circuit, as exemplified in Japanese Patent Laid-Open No. 59-172758.
An upper bonding surface, which relates to a chip carrier and has a die bonding portion surrounded by a plurality of wire bond pads 51 (see FIG. 7A). A lower soldering surface facing the upper bonding surface and including an inner solder pad 52 array (see FIG. 7B). Means 53 for electrically coupling a portion of the solder pad 52 to a portion of the wire bond pad 51 (FIG. 7 (c)).
reference). An insulating peripheral portion 54 (see FIG. 7C) of the lower soldering surface surrounding the inner solder pad 52 is provided.

【０００７】また、これに似た形態の半導体パッケージ
として、上記はんだパッドの代わりに金属ピンを立てた
構造で、プリント配線板に予め形成したスルーホールに
挿入してはんだ付けすることで固定する、いわゆるピン
・グリッド・アレイ型（PinGrid Array…以下、ＰＧＡ
と称する）の半導体パッケージがある（図６参照）。Further, as a semiconductor package having a similar form to this, a structure in which metal pins are erected in place of the solder pads is inserted into through holes formed in advance in a printed wiring board and fixed by soldering. So-called pin grid array type (PGA)
There is a semiconductor package) (refer to FIG. 6).

【０００８】なお、上記参照図面では、チップの端子の
数およびリードの本数が９個についての場合で説明を簡
略化している。In the above referenced drawings, the description is simplified in the case where the number of terminals of the chip and the number of leads are nine.

【０００９】ＱＦＰに対してのＢＧＡの利点は、特に実
装密度の向上にあり、ＱＦＰを取り付けるのに必要な外
部回路基板の実質的面積よりも、ＢＧＡを取り付けるの
に必要な前記面積が大幅に小さくなる点にある。The advantage of the BGA over the QFP lies particularly in the increased packing density, where the area required for mounting the BGA is significantly larger than the substantial area of the external circuit board required for mounting the QFP. It's getting smaller.

【００１０】一般的なＢＧＡ型のチップキャリアは、プ
リント配線板用の銅張積層板（エポキシ樹脂等からなる
絶縁性基材の両面または片面に、銅箔を貼り合わせたも
の）をベース材料（上記）とし、これをフォトエッチ
ング法等の方法で加工して、チップ搭載部と配線部（上
記と）を形成している。In a general BGA type chip carrier, a copper clad laminate for a printed wiring board (a copper foil is bonded to both sides or one side of an insulating base material made of epoxy resin or the like) as a base material ( The above) is processed by a method such as a photoetching method to form a chip mounting portion and a wiring portion (above).

【００１１】[0011]

【発明が解決しようとする課題】上記のようにベース材
料として銅張積層板を使用したＢＧＡ型の半導体装置で
は、以下に挙げる問題点を有する。The BGA type semiconductor device using the copper clad laminate as the base material as described above has the following problems.

【００１２】チップキャリアをプリント配線板（外部回
路）に接続する際、２３０〜２６０℃程度に加熱しては
んだボール（パッド）を溶融させる必要があり、この時
の熱で半導体パッケージとプリント配線板（外部回路）
の両方に反りが発生することにより、ボール状に形成し
た半導体装置上の端子（はんだパッド）とプリント配線
板上に形成したパッドとの間に隙間が発生してしまうた
め、端子数がおよそ３００を越えるチップを搭載する場
合には、全てのパッドを安定して接続することが難し
い。When the chip carrier is connected to the printed wiring board (external circuit), it is necessary to heat the solder balls (pads) by heating at about 230 to 260 ° C., and the heat at this time causes the semiconductor package and the printed wiring board. (External circuit)
As a result of the warpage of both of them, a gap is generated between the terminals (solder pads) formed on the ball-shaped semiconductor device and the pads formed on the printed wiring board. It is difficult to connect all the pads stably when mounting chips exceeding the above.

【００１３】さらに、発熱量の大きいチップを使用する
場合も、上記ベース材料として樹脂を主体とする従来の
ＢＧＡでは、放熱性・接続信頼性の点で満足のいくもの
ではない。Further, even when a chip having a large amount of heat generation is used, the conventional BGA mainly made of resin as the base material is not satisfactory in terms of heat dissipation and connection reliability.

【００１４】そのため、端子数がおよそ３００以上のも
のや、発熱量の大きいチップを使用する場合には、接続
信頼性を向上させるために、ＰＧＡ型の半導体パッケー
ジに加工してチップを搭載することになるので、半導体
装置自体が高価になってしまう。Therefore, when a chip having more than about 300 terminals or a chip having a large heat generation is used, the chip is processed and mounted on a PGA type semiconductor package in order to improve the connection reliability. Therefore, the semiconductor device itself becomes expensive.

【００１５】本発明は、ＰＧＡ型の半導体装置より安価
で、従来のＢＧＡ型の半導体装置より放熱性・接続信頼
性の高い、新規なＢＧＡ型のチップキャリアを提供する
ことを目的とする。It is an object of the present invention to provide a novel BGA type chip carrier which is cheaper than a PGA type semiconductor device and has higher heat dissipation and connection reliability than a conventional BGA type semiconductor device.

【００１６】[0016]

【課題を解決するための手段】上記目的を達成するため
に、べース材料として、樹脂を主体とする従来のＢＧＡ
に代わって、金属板を主体とする材料を用いた。In order to achieve the above object, a conventional BGA mainly composed of a resin as a base material is used.
Instead of, a material mainly composed of a metal plate was used.

【００１７】すなわち本発明は、略マトリクス状に複数
の孔が形成され、前記孔の壁面を含む表面に絶縁薄膜が
形成された金属板をベース基板とし、前記基板の片面に
は、配線用導体パターンが形成され、前記パターンの始
端と半導体集積回路素子とが接続されており、前記基板
の他面には、外部回路との直接的接続のためのはんだパ
ッド配列が、前記パターンの終端となる電極端子それぞ
れに対応して配置された構成のチップキャリアの製造方
法である。すなわち、略マトリックス状に配置された貫
通孔を有する金属板を使用したチップキャリアの製造に
あたって、前記金属板の両面に金属箔、絶縁フィルム、
接着剤層の３層からなるフィルムを貼り合わせて、前記
貫通孔を接着剤にて埋めるラミネート工程と、上記工程
にて得られた積層板のバイアホールとなる箇所の金属箔
をパターニング加工して開口部を設け、該開口部にレー
ザービームを照射して、絶縁フィルム層、接着剤層にバ
イアホール用の孔部を形成する工程とを具備することを
特徴とするチップキャリアの製造方法及び、前記金属板
の貫通孔が深さ方向に対しテーパー形状を有することを
特徴とする請求項１に記載のチップキャリアの製造方法
を提供する。That is, the present invention uses a metal plate having a plurality of holes formed in a substantially matrix shape and an insulating thin film formed on a surface including wall surfaces of the holes as a base substrate, and one side of the substrate has a wiring conductor. A pattern is formed, a start end of the pattern is connected to a semiconductor integrated circuit element, and a solder pad array for direct connection to an external circuit serves as the end of the pattern on the other surface of the substrate. How to manufacture chip carriers that are arranged corresponding to each electrode terminal
Is the law . That is, in manufacturing a chip carrier using a metal plate having through holes arranged in a substantially matrix, a metal foil, an insulating film, on both surfaces of the metal plate,
A film consisting of three layers of an adhesive layer is laminated, and a laminating step of filling the through holes with an adhesive, and a patterning process of a metal foil at a place to be a via hole of the laminate obtained in the above step. A step of providing an opening and irradiating the opening with a laser beam to form a hole for a via hole in the insulating film layer and the adhesive layer.
Method for producing a chip carrier, characterized and, to provide a method of manufacturing a chip carrier according to claim 1, characterized in that it comprises a through hole depth direction with respect to the tapered shape of the metal plate.

【００１８】[0018]

【作用】チップ搭載部を、金属主体のベース材料を用い
て成形することにより、チップからの発熱を金属部で放
散できるようになり、（従来のベース材料よりも、平均
熱伝導度が大きいため）放熱特性が向上する。さらに、
金属箔、絶縁フィルム、接着剤の３層からなるフィルム
を貫通孔を有する金属板の両面から貼り合わせる際、貫
通孔の深さ方向にテーパー形状を持たせることにより、
貼り合わせ時の貫通孔周辺の接着剤の流動性が良くな
り、気泡のない貼り合わせができる。[Function] By molding the chip mounting part using a metal-based base material, the heat generated from the chip can be dissipated in the metal part (because the average thermal conductivity is higher than that of the conventional base material). ) The heat dissipation characteristics are improved. further,
When a film composed of three layers of a metal foil, an insulating film, and an adhesive is attached from both sides of a metal plate having a through hole, by providing a taper shape in the depth direction of the through hole,
The fluidity of the adhesive around the through holes at the time of bonding is improved, and bonding can be performed without bubbles.

【００１９】[0019]

【実施例】以下に実施例をあげて本発明の内容を詳しく
説明する。 〈参考例〉以下金属板をベースにしたチップキャリアの
参考例について図１、２に基づいて説明する。厚さ０．
２ｍｍのＣｕ系合金の金属板にフォトエッチングによっ
て、略マトリクス状に複数の貫通孔１２を形成した金属
板１１を作成した（図２参照）。EXAMPLES The contents of the present invention will be described in detail below with reference to examples. < Reference example > Below is a chip carrier based on a metal plate.
A reference example will be described with reference to FIGS. Thickness 0.
A metal plate 11 having a plurality of through holes 12 formed in a substantially matrix shape was prepared by photoetching a 2 mm Cu-based alloy metal plate (see FIG. 2).

【００２０】前記孔あけした金属板１１に、ポリブタジ
エン変性品電着液（日石化学（株）製）を用いて、前記
貫通孔１２の壁面を含む表面に絶縁薄膜１３を形成し
た。On the perforated metal plate 11, an insulating thin film 13 was formed on the surface including the wall surface of the through hole 12 by using a polybutadiene modified electrodeposition liquid (manufactured by Nisseki Chemical Co., Ltd.).

【００２１】電着条件は、７０Ｖの定電圧、キュア２０
０℃、時間１０分であり、絶縁薄膜１３の平均厚さは１
５μｍである。The electrodeposition conditions are a constant voltage of 70 V and cure 20.
The temperature is 0 ° C., the time is 10 minutes, and the average thickness of the insulating thin film 13 is 1
It is 5 μm.

【００２２】（１）配線用導体パターン・電極端子の形
成（以下、図１参照）。次いで、前記金属板１１の絶縁
薄膜１３の表面に、厚さ約３０μｍのＣｕ層を形成し
た。その手順は、まず、無電解めっき法により厚さ１μ
ｍのＣｕ膜を形成した後、前記Ｃｕ膜の表面に、電気め
っき法（前記Ｃｕ膜を電極として）によりＣｕ膜をさら
に形成した。(1) Formation of wiring conductor patterns and electrode terminals (see FIG. 1 below). Then, a Cu layer having a thickness of about 30 μm was formed on the surface of the insulating thin film 13 of the metal plate 11. The procedure is as follows.
After forming the Cu film of m, a Cu film was further formed on the surface of the Cu film by electroplating (using the Cu film as an electrode).

【００２３】前記Ｃｕ膜を、フォトリソグラフィ法によ
り、上面を第１配線パターン１４ａとし、他面を外部接
続用電極端子１５となるようにパターニングした。The Cu film was patterned by photolithography so that the upper surface was the first wiring pattern 14a and the other surface was the external connection electrode terminal 15.

【００２４】配線パターンとして、高密度で複雑なパタ
ーンを設ける必要があり、単層で形成するのが不可能な
場合には、前記パターンを多層に配置（金属基板側より
パターン１４ａ、１４ｂ…というように）して、配線の
高密度化を図る必要がある。As a wiring pattern, it is necessary to provide a high-density and complicated pattern, and when it is not possible to form a single layer, the patterns are arranged in multiple layers (patterns 14a, 14b ... from the metal substrate side). Therefore, it is necessary to increase the wiring density.

【００２５】前記配線パターンの多層化にあたっては、
下層の配線パターンを含む表面に、絶縁層１６を形成し
た後、同様に導電層（Ｃｕ膜）を形成し、パターニング
を行う。In forming the wiring pattern in multiple layers,
After forming the insulating layer 16 on the surface including the lower wiring pattern, a conductive layer (Cu film) is similarly formed and patterned.

【００２６】この際、上下の配線パターン間で導通をと
るため、絶縁層１６にスルーホール１７を形成し、スル
ーホール壁面に形成した導電層で、両者を導通させる。At this time, in order to establish electrical continuity between the upper and lower wiring patterns, a through hole 17 is formed in the insulating layer 16 and the conductive layer formed on the wall surface of the through hole electrically connects the two.

【００２７】絶縁層１６の所望部分にスルーホール１７
を形成するため、絶縁層１６は、フォトリソグラフィ法
によりパターニングできる材質であることが望ましく、
感光性樹脂が適切である。Through holes 17 are formed in desired portions of the insulating layer 16.
In order to form, the insulating layer 16 is desirably made of a material that can be patterned by a photolithography method,
A photosensitive resin is suitable.

【００２８】配線パターンの形成後、最上層の第２配線
パターン１４ｂの表面にＡｕめっきを施し、チップとの
接続（ワイヤ・ボンディング）適性を向上させる。After the wiring pattern is formed, the surface of the uppermost second wiring pattern 14b is plated with Au to improve the suitability for connection with a chip (wire bonding).

【００２９】（２）チップキャリアの作製 最上層の第２配線パターンに取り囲まれた領域のチップ
搭載部に、銀ペースト（ＣＲＭ−１０３５Ｔ；住友ベー
クライト（株）製）を用いて、チップ１８を搭載し、Ａ
ｕワイヤによるボンディングでチップ１８と配線用パタ
ーンとを接続した。(2) Manufacture of Chip Carrier The chip 18 is mounted on the chip mounting portion in the region surrounded by the second wiring pattern on the uppermost layer by using silver paste (CRM-1035T; manufactured by Sumitomo Bakelite Co., Ltd.). Then A
The chip 18 and the wiring pattern were connected by bonding with u wire.

【００３０】次いで、チップ搭載部を含む所望領域を樹
脂封止した。樹脂封止にあたっては、金型を用いたモー
ルディングにはよらず、光硬化型樹脂をポッティング
（滴下）した後、露光硬化させることにより、樹脂封止
を行った。Next, a desired area including the chip mounting portion was resin-sealed. In resin encapsulation, the resin encapsulation was performed by potting (dripping) a photo-curable resin and then exposing and curing the resin, not by molding using a mold.

【００３１】他面においては、外部接続用電極端子１５
にはんだパッド１９を形成した。はんだパッドの形成に
あたっては、外部接続用電極端子１５にはんだペースト
を滴下し、球状のはんだパッド１９を形成する。また
は、固形のはんだボールを電極端子１５に配置した後、
リフロー加熱を行なうことによるか、ディスペンサでは
んだペーストを塗布した後、ＩＲリフロー装置で加熱し
てはんだペーストを溶融させることによっても作成でき
る。以上によって、本発明のチップキャリアを作製し
た。On the other side, the external connection electrode terminal 15
The solder pad 19 is formed on the substrate. In forming the solder pad, a solder paste is dropped on the external connection electrode terminal 15 to form a spherical solder pad 19. Alternatively, after disposing solid solder balls on the electrode terminals 15,
It can also be produced by performing reflow heating or by applying a solder paste with a dispenser and then heating with an IR reflow device to melt the solder paste. As described above, the chip carrier of the present invention was manufactured.

【００３２】〈実施例１〉以下、請求項１、２に掲げた
内容の製造法についての実施例について、図３、４に基
づいて説明する。あらかじめ脱脂、酸洗処理を工程を経
て洗浄した、厚さ０．１ｍｍの銅系合金金属板１の両面
に、フォトレジストＰＭＥＲ（東京応化工業社製）を浸
漬塗布した。８０℃、３０分プリベークを行った後、所
望のパターンを有するフォトマスクを介して、超高圧水
銀灯にて１００ｍＪ／ｃｍ２露光を行った。その後、専
用の現像液にてスプレー現像を行い、１１０℃、３０分
ポストベークを行った。続いて、４５ボーメ度、５０℃
の塩化第２鉄液を用いスプレーエッチング加工を行い、
貫通孔２を形成した。その際、貫通孔２にテーパー形状
がつくようにエッチング条件を設定した。その後、専用
の剥離液に浸漬してフォトレジスト膜を除去し、水洗、
乾燥して、前記金属板に略マトリックス状に複数の０．
１５ｍｍの径を有する貫通孔２を形成した（図４（ｂ）
参照）。<Example 1 > An example of a manufacturing method having the contents recited in claims 1 and 2 will be described below with reference to FIGS. Photoresist PMER (manufactured by Tokyo Ohka Kogyo Co., Ltd.) was applied by dip coating on both sides of a copper-based alloy metal plate 1 having a thickness of 0.1 mm which had been degreased and pickled in advance. After prebaking at 80 ° C. for 30 minutes, 100 mJ / cm 2 exposure was performed with an ultrahigh pressure mercury lamp through a photomask having a desired pattern. After that, spray development was performed with a dedicated developer, and post baking was performed at 110 ° C. for 30 minutes. Then, 45 Baume degree, 50 ℃
Spray etching using ferric chloride solution
The through hole 2 was formed. At that time, the etching conditions were set so that the through hole 2 was tapered. After that, the photoresist film is removed by immersing in a dedicated stripping solution, washing with water,
After being dried, a plurality of particles of 0.
A through hole 2 having a diameter of 15 mm was formed (Fig. 4 (b)).
reference).

【００３３】前記貫通孔２を形成した金属板１１の両面
から１８μｍ厚の銅箔３ａ、３ｂ／７０μｍ厚のポリイ
ミドフィルム４ａ、４ｂ／１００μｍ厚のポリイミド接
着剤５ａ、５ｂの各３層構成から成るテープを加熱、加
圧ロールにてラミネートした。このときのラミネート温
度は１８０℃であった。貫通孔２はあらかじめ深さ方向
にテーパーを持たせてあるため、貫通孔周辺のポリイミ
ド接着剤は流動性が良くなり、気泡が混入することなく
埋まった（図４（Ｃ）参照）。ラミネートの終わった積
層板は２２０℃で１時間加熱し、ポリイミド接着剤５を
完全に硬化させた。A copper foil 3a having a thickness of 18 μm, a polyimide film 4a having a thickness of 70 μm, a polyimide film 4b having a thickness of 70 μm, and a polyimide adhesive 5a having a thickness of 100 μm are provided on both sides of the metal plate 11 having the through holes 2. The tape was heated and laminated with a pressure roll. The laminating temperature at this time was 180 ° C. Since the through-hole 2 has a taper in the depth direction in advance, the polyimide adhesive around the through-hole has good fluidity and is filled without bubbles mixed therein (see FIG. 4C). The laminated plate having been laminated was heated at 220 ° C. for 1 hour to completely cure the polyimide adhesive 5.

【００３４】次に、フォトエッチング加工により、前記
ラミネート積層板の銅箔３ａ部に、貫通孔と同心円でか
つ小径を有する開口部２１を形成した。この径の直径は
０．０５ｍｍであった（図４（ｄ）参照）。Next, by photo-etching, an opening 21 having a small diameter and a concentric circle with the through hole was formed in the copper foil 3a portion of the laminate laminate. The diameter of this diameter was 0.05 mm (see FIG. 4 (d)).

【００３５】この開口部２１に、波長が２４８ｎｍのＫ
ｒＦエキシマーレーザー光を照射し、ポリイミドフィル
ム層４ａ、ポリイミド接着剤層５、ポリイミドフィルム
層４ｂを貫通する第１のバイアホール形成のための孔部
２２を形成した。この孔部２２の断面形状は良好で、開
口部２１からほぼ垂直に孔部が形成された。さらに、本
実験で使用したレーザービームの加工条件では下部の銅
箔３ｂがストッパーの役目をすると同時に、レーザービ
ームが照射された銅箔表面の樹脂は完全に除去された。
また、金属板１１の貫通孔２の側面は、金属面が露出す
ることなく、およそ、０．０５ｍｍのバイアホール形成
のための孔部２２が形成された（図４（ｅ）参照）。A wavelength of 248 nm K
Irradiation with rF excimer laser light was performed to form holes 22 for forming first via holes that penetrate the polyimide film layer 4a, the polyimide adhesive layer 5, and the polyimide film layer 4b. The cross-sectional shape of the hole 22 was good, and the hole was formed almost vertically from the opening 21. Further, under the processing conditions of the laser beam used in this experiment, the lower copper foil 3b served as a stopper, and at the same time, the resin on the surface of the copper foil irradiated with the laser beam was completely removed.
Further, on the side surface of the through hole 2 of the metal plate 11, a hole portion 22 for forming a via hole of about 0.05 mm was formed without exposing the metal surface (see FIG. 4 (e)).

【００３６】この孔部２２に導体層を形成するために、
無電解めっき、電解めっきを行い、厚さ０．０１ｍｍの
銅層２３を形成した。これにより、銅箔３ａ層と銅箔３
ｂ層は第１バイアホール２４にて電気的に接続された
（図４（ｆ）参照）。In order to form a conductor layer in this hole 22,
Electroless plating and electrolytic plating were performed to form a copper layer 23 having a thickness of 0.01 mm. Thereby, the copper foil 3a layer and the copper foil 3
The layer b was electrically connected through the first via hole 24 (see FIG. 4 (f)).

【００３７】さらに、両面同時に、フォトエッチング加
工を行い、銅箔３ａ層には第１配線パターン２５を、銅
箔３ｂ層には外部接続用電極端子２６を形成した（図４
（ｇ）参照）。Further, photoetching is performed on both surfaces simultaneously to form a first wiring pattern 25 on the copper foil 3a layer and an external connection electrode terminal 26 on the copper foil 3b layer (FIG. 4).
(See (g)).

【００３８】次に、第１配線パターン２５の上面部に１
８μｍの銅箔３１／７０μｍ厚のポリイミドフィルム３
２／１００μｍ厚のポリイミド接着剤３３の３層構成か
ら成る３層テープをラミネートした。以下、第１バイア
ホール２４、第１配線パターン２５を形成するのと同様
に、銅箔３１に開口部３４を設け、開口部３４にレーザ
ービームを照射して、ポリイミドフィルム３２、ポリイ
ミド接着剤３３層に第２バイアホール形成のための孔部
３６を形成し、銅箔３１層と第１配線パターンを電気的
に接続するための、銅層３８を無電解、電解メッキで形
成し、第２バイアホール３７、フォトエッチング加工に
より第２配線パターン３９を形成した。このとき、上記
配線層をパターニング、メッキ処理する際、下面外部接
続用電極端子２６を保護するために、保護膜３５を形成
し、第２配線パターン３９形成後に剥離した（図４
（ｈ）〜（ｋ）参照）。Next, 1 is formed on the upper surface of the first wiring pattern 25.
8 μm copper foil 31/70 μm thick polyimide film 3
A three-layer tape having a three-layer structure of the polyimide adhesive 33 having a thickness of 2/100 μm was laminated. Hereinafter, similarly to the case of forming the first via hole 24 and the first wiring pattern 25, the opening portion 34 is provided in the copper foil 31, and the opening portion 34 is irradiated with a laser beam, so that the polyimide film 32 and the polyimide adhesive 33. A hole 36 for forming a second via hole is formed in the layer, and a copper layer 38 for electrically connecting the copper foil 31 layer and the first wiring pattern is formed by electroless and electrolytic plating. A second wiring pattern 39 was formed by using the via hole 37 and photo etching. At this time, when patterning and plating the wiring layer, a protective film 35 is formed in order to protect the lower surface external connection electrode terminal 26, and is peeled off after the second wiring pattern 39 is formed (FIG. 4).
(See (h) to (k)).

【００３９】第２配線パターン３９の必要部分にはチッ
プとの接続（ワイヤーボンディング）を行うためにニッ
ケルめっき、さらに、金めっきを行った。The required portion of the second wiring pattern 39 was nickel-plated and then gold-plated for connection with the chip (wire bonding).

【００４０】次に、チップキャリアの作製工程について
説明する。最上層のニッケルおよび金めっきを施した第
２配線パターンに取り囲まれた領域のチップ搭載部に、
銀ペースト（ＣＲＭ−１０３５Ｔ；住友ベークライト社
製）を用いて、チップ１８を搭載し、金ワイヤーによる
ボンディングでチップ１８と配線用パターンとを接続し
た（図４（ｋ）参照）。Next, a manufacturing process of the chip carrier will be described. In the chip mounting part in the area surrounded by the second wiring pattern plated with nickel and gold on the uppermost layer,
The chip 18 was mounted using a silver paste (CRM-1035T; manufactured by Sumitomo Bakelite Co., Ltd.), and the chip 18 and the wiring pattern were connected by bonding with a gold wire (see FIG. 4 (k)).

【００４１】次いで、チップ搭載部を含む所望領域を樹
脂封止した。樹脂封止にあたっては、金型を用いたモー
ルディングにはよらず、光硬化型樹脂をポッティング
（滴下）した後、ＵＶ露光、硬化させることにより、樹
脂封止を行った。Next, a desired area including the chip mounting portion was resin-sealed. In resin encapsulation, the resin encapsulation was performed by potting (dropping) a photo-curable resin, followed by UV exposure and curing, instead of molding using a mold.

【００４２】他面においては、外部接続用電極端子２６
にはんだパッド１９を形成した。はんだパッド１９の形
成にあたっては、外部接続用電極端子２６にはんだペー
ストを滴下し、球状のはんだパッド１９を形成する。ま
たは、固形のはんだボールを電極端子２６に配置した
後、リフロー加熱を行なうことによるか、ディスペンサ
ではんだペーストを塗布した後、ＩＲリフロー装置で加
熱してはんだペーストを溶融させることによっても作成
できる。以上によって、本発明のチップキャリアを作製
した。On the other side, the electrode terminal 26 for external connection is used.
The solder pad 19 is formed on the substrate. When forming the solder pad 19, a solder paste is dropped on the external connection electrode terminal 26 to form a spherical solder pad 19. Alternatively, it can be also prepared by placing solid solder balls on the electrode terminals 26 and then performing reflow heating, or by applying solder paste with a dispenser and then heating with an IR reflow device to melt the solder paste. As described above, the chip carrier of the present invention was manufactured.

【００４３】[0043]

【発明の効果】チップ搭載部として、金属主体のベース
材料が用いられているため、外部回路との接続の際の加
熱による反りの問題が軽減される。また、従来のベース
材料よりも、平均熱伝導度が大きい構成であるため、放
熱特性が向上し、従来のＢＧＡ型のチップキャリアより
も放熱性・接続信頼性が高いＢＧＡ型のチップキャリア
が提供できる。さらに、金属板をベースにした積層板は
金属箔、ポリイミドフィルム、ポリイミド接着剤による
３層フイルムを金属板の両面から貼り合わせて作成する
ため、積層工程の簡略化が計れ、かつ金属板の貫通孔が
テーパー形状を有しているため、貫通孔周辺の接着剤の
流動性が良くなり気泡の混入がない積層板を作成するこ
とが出来た。またバイアホールの孔部加工にレーザービ
ームを使うことにより、孔部孔壁が凹凸の少ない滑らか
な面に仕上がり、銅箔を孔あけした開口部からレーザー
ビームを照射しているため、孔周辺部は熱影響がほとん
ど認められなかった。さらに、バイアホール形成のため
の孔部下端の銅箔表面の接着剤は完全に除去されてお
り、メッキ後の被膜接着性及び電気導通は良好であっ
た。Since the base material mainly made of metal is used for the chip mounting portion, the problem of warpage due to heating at the time of connection with an external circuit is reduced. Also, since the average thermal conductivity is higher than that of the conventional base material, the heat dissipation characteristics are improved, and the BGA type chip carrier having higher heat dissipation and connection reliability than the conventional BGA type chip carrier is provided. it can. Furthermore, since a laminated plate based on a metal plate is made by bonding a three-layer film made of a metal foil, a polyimide film, and a polyimide adhesive from both sides of the metal plate, the lamination process can be simplified and the metal plate can be penetrated. Since the holes have a tapered shape, the flowability of the adhesive around the through holes was improved, and it was possible to produce a laminated plate in which air bubbles were not mixed. Also, by using a laser beam for hole processing of the via hole, the hole wall is finished to a smooth surface with less unevenness and the laser beam is radiated from the opening where the copper foil is drilled Almost no heat effect was observed. Furthermore, the adhesive on the surface of the copper foil at the lower end of the hole for forming the via hole was completely removed, and the coating adhesion and electrical continuity after plating were good.

【００４４】[0044]

【図面の簡単な説明】[Brief description of drawings]

【図１】本発明のチップキャリアの断面説明図。FIG. 1 is a sectional explanatory view of a chip carrier of the present invention.

【図２】本発明のチップキャリアを構成する金属板を示
す平面図。FIG. 2 is a plan view showing a metal plate that constitutes the chip carrier of the present invention.

【図３】本発明のチップキャリアの断面説明図。FIG. 3 is an explanatory cross-sectional view of the chip carrier of the present invention.

【図４】本発明のチップキャリアの製造工程を示す断面
説明図。FIG. 4 is a sectional explanatory view showing a manufacturing process of the chip carrier of the present invention.

【図５】従来のチップキャリア（ＱＦＰ）の説明図。FIG. 5 is an explanatory diagram of a conventional chip carrier (QFP).

【図６】従来のチップキャリア（ＰＧＡ）の説明図。FIG. 6 is an explanatory diagram of a conventional chip carrier (PGA).

【図７】従来のＢＧＡ方式のチップキャリアの説明図。FIG. 7 is an explanatory diagram of a conventional BGA type chip carrier.

【符号の説明】[Explanation of symbols]

１……金属板 ２、１２……貫通孔 ３ａ、３ｂ、３１……銅箔 ４ａ、４ｂ、３２……ポリイミドフィルム ５、５ａ、５ｂ、３３……ポリイミド接着剤 ６……加熱、加圧ロール １１……孔あけ加工された金属板 １３……絶縁薄膜 １４ａ、２５……第１配線パターン １４ｂ、３９……第２配線パターン １５、２６……外部接続用電極端子 １６……絶縁層 １７……スルーホール １８……チップ １９……はんだパッド ２１……開口部 ２２、３４……バイアホール形成のための孔部 ２３、３８……メッキ銅層 ２４……第１バイアホール ３５……保護膜 ３７……第２バイアホール ５０……ＢＧＡ型のチップキャリア ５１……ワイヤボンドパッド ５２……はんだパッド ５３……メッキ導通層 ５４……絶縁性周辺部位 1 ... Metal plate 2, 12 ... through hole 3a, 3b, 31 ... Copper foil 4a, 4b, 32 ... Polyimide film 5, 5a, 5b, 33 ... Polyimide adhesive 6 ... Heating and pressure roll 11 ... Metal plate that has been punched 13 ... Insulating thin film 14a, 25 ... First wiring pattern 14b, 39 ... second wiring pattern 15, 26 ... Electrode terminals for external connection 16 ... Insulating layer 17-Through hole 18 ... Chip 19 ... Solder pad 21 ... Opening 22, 34 ... Holes for forming via holes 23, 38 ... Plated copper layer 24 …… First via hole 35 ... Protective film 37 …… Second via hole 50 ... BGA type chip carrier 51: Wire bond pad 52 ... Solder pad 53 ... Plating conductive layer 54 ... Insulating peripheral area

───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 23/12 - 23/15 H05K 1/05,3/00,3/44 ─────────────────────────────────────────────────── ─── Continuation of front page (58) Fields surveyed (Int.Cl. 7 , DB name) H01L 23/12-23/15 H05K 1 / 05,3 / 00,3 / 44

Claims (2)

(57)【特許請求の範囲】(57) [Claims] 【請求項１】略マトリックス状に配置された貫通孔を有
する金属板を使用したチップキャリアの製造にあたっ
て、 前記金属板の両面に金属箔、絶縁フィルム、接着剤層の
３層からなるフィルムを貼り合わせて、前記貫通孔を接
着剤にて埋めるラミネート工程と、 上記工程にて得られた積層板のバイアホールとなる箇所
の金属箔をパターニング加工して開口部を設け、該開口
部にレーザービームを照射して、絶縁フィルム層、接着
剤層にバイアホール用の孔部を形成する工程と、を具備
することを特徴とするチップキャリアの製造方法。1. When manufacturing a chip carrier using a metal plate having through-holes arranged in a substantially matrix shape, a film consisting of three layers of a metal foil, an insulating film and an adhesive layer is attached to both surfaces of the metal plate. At the same time, a laminating step of filling the through holes with an adhesive and a patterning process are performed on the metal foil of the laminated plate obtained in the above step to be a via hole to form an opening, and a laser beam is formed in the opening. by irradiating the insulating film layer, the manufacturing method of the chip carrier, characterized by comprising the steps of forming a hole for via hole in the adhesive layer. 【請求項２】前記貫通孔が深さ方向に対しテーパー形状
を有することを特徴とする請求項１に記載のチップキャ
リアの製造方法。2. The method of manufacturing a chip carrier according to claim 1 , wherein the through hole has a taper shape in the depth direction.
JP15473195A 1994-07-25 1995-06-21 Manufacturing method of chip carrier Expired - Fee Related JP3513983B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15473195A JP3513983B2 (en) 1994-07-25 1995-06-21 Manufacturing method of chip carrier

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP6-172519 1994-07-25
JP17251994 1994-07-25
JP15473195A JP3513983B2 (en) 1994-07-25 1995-06-21 Manufacturing method of chip carrier

Publications (2)

Publication Number Publication Date
JPH0897330A JPH0897330A (en) 1996-04-12
JP3513983B2 true JP3513983B2 (en) 2004-03-31

Family

ID=26482938

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15473195A Expired - Fee Related JP3513983B2 (en) 1994-07-25 1995-06-21 Manufacturing method of chip carrier

Country Status (1)

Country Link
JP (1) JP3513983B2 (en)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100209259B1 (en) * 1996-04-25 1999-07-15 이해규 Ic card and method for manufacture of the same
JP2817717B2 (en) * 1996-07-25 1998-10-30 日本電気株式会社 Semiconductor device and manufacturing method thereof
KR100209263B1 (en) * 1996-12-31 1999-07-15 이해규 Chip carrier and its manufacturing method, semiconductor accessory using its chip carrier
ATE224099T1 (en) * 1997-10-04 2002-09-15 Unimicron Taiwan Corp SUPPORT FOR SUBSTRATES OF INTEGRATED CIRCUIT ARRANGEMENTS WITH A SPHERE MATRIX
US6711812B1 (en) * 1999-04-13 2004-03-30 Unicap Electronics Industrial Corporation Method of making metal core substrate printed circuit wiring board enabling thermally enhanced ball grid array (BGA) packages
US7723842B2 (en) 2005-09-02 2010-05-25 Semiconductor Energy Laboratory Co., Ltd Integrated circuit device
CN107864555B (en) * 2017-12-09 2024-02-09 中国电子科技集团公司第四十三研究所 Flexible circuit board

Also Published As

Publication number Publication date
JPH0897330A (en) 1996-04-12

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