JPH07263491A - Mounting method for semiconductor element - Google Patents
Mounting method for semiconductor elementInfo
- Publication number
- JPH07263491A JPH07263491A JP4938194A JP4938194A JPH07263491A JP H07263491 A JPH07263491 A JP H07263491A JP 4938194 A JP4938194 A JP 4938194A JP 4938194 A JP4938194 A JP 4938194A JP H07263491 A JPH07263491 A JP H07263491A
- Authority
- JP
- Japan
- Prior art keywords
- bump
- semiconductor element
- substrate
- pad
- electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8312—Aligning
- H01L2224/83136—Aligning involving guiding structures, e.g. spacers or supporting members
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
Landscapes
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、基板に半導体素子を位
置決めすることにより該半導体素子を該基板に保持さ
せ、バンプを介して該半導体素子を該基板に実装する半
導体素子の実装方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor element mounting method for positioning a semiconductor element on a substrate to hold the semiconductor element on the substrate and mounting the semiconductor element on the substrate via bumps.
【０００２】プリント基板などの基板に複数のLSI 素子
などの半導体素子を実装する場合は、それぞれの半導体
素子にバンプを固着させ、バンプの固着した半導体素子
を基板の所定箇所に位置決めし、複数の半導体素子が配
列された基板を例えば、高温槽などに挿入し、高温槽の
加熱によってバンプを溶融し、それぞれの半導体素子の
電極がバンプを介して基板のパッドに接合されることに
よって半導体素子の実装が行われる。When mounting a plurality of semiconductor elements such as LSI elements on a substrate such as a printed circuit board, bumps are fixed to the respective semiconductor elements, and the semiconductor elements to which the bumps are fixed are positioned at predetermined positions on the board, and a plurality of semiconductor elements are attached. A substrate on which semiconductor elements are arranged is inserted into, for example, a high temperature tank, the bumps are melted by heating in the high temperature tank, and the electrodes of the respective semiconductor elements are bonded to the pads of the substrate through the bumps, thereby Implementation is done.
【０００３】このような半導体素子の実装に際しては、
半導体素子を基板の所定箇所に位置決め後、バンプの溶
融を行うまでの間に、半導体素子が位置ずれを起こすと
半導体素子が基板の所定箇所に実装されなくなる。When mounting such a semiconductor element,
After the semiconductor element is positioned at a predetermined position on the substrate and before the bumps are melted, if the semiconductor element is displaced, the semiconductor element will not be mounted at the predetermined position on the substrate.
【０００４】そこで、半導体素子を基板の所定箇所に位
置決めし、バンプの溶融が行われ、電極をパッドに接合
するリフローが終了するまでの間は確実に半導体素子が
基板の所定箇所に保持されることが必要となる。Therefore, the semiconductor element is reliably held at the predetermined location on the substrate until the semiconductor element is positioned at the predetermined location on the substrate, the bumps are melted, and the reflow for bonding the electrode to the pad is completed. Will be required.
【０００５】[0005]
【従来の技術】従来は、図５の従来の説明図に示すよう
に行われていた。図５の(a) 〜(d) は側面図である。2. Description of the Related Art Conventionally, this has been done as shown in the conventional explanatory view of FIG. 5A to 5D are side views.
【０００６】図５の(a) に示すように、半導体素子3 の
電極4 にはバンプ7 を固着すると共に、パッド2 が配列
された基板1 の配列面1Aにはフラックス10を塗布し、所
定の端子4 が所定のパッド2 に合致するよう位置決め
し、矢印A に示すように半導体素子3 を降下させること
が行われる。As shown in FIG. 5A, the bumps 7 are fixed to the electrodes 4 of the semiconductor element 3, and the flux 10 is applied to the array surface 1A of the substrate 1 on which the pads 2 are arrayed, to a predetermined size. The terminal 4 is positioned so as to match the predetermined pad 2, and the semiconductor element 3 is lowered as shown by the arrow A.
【０００７】このような半導体素子3 の降下により、図
５の(b) に示すように、バンプ7 の先端がパッド2 に当
接され、フラックス10が基板1 と半導体素子3 との間に
充填され、フラックス10の粘着力により半導体素子3 は
基板1 の配列面1Aに保持されることになる。Due to the lowering of the semiconductor element 3, the tip of the bump 7 is brought into contact with the pad 2 as shown in FIG. 5B, and the flux 10 is filled between the substrate 1 and the semiconductor element 3. Then, the semiconductor elements 3 are held on the array surface 1A of the substrate 1 by the adhesive force of the flux 10.
【０００８】このように基板1 に実装すべき半導体素子
3 を所定箇所に位置決めすることにより、基板1 に複数
の半導体素子3 を保持させ、次に、基板1 を高温槽に挿
入し、所定温度に加熱し、それぞれのバンプ7 を一括し
て溶融させ、端子4 とバンプ2 とが図５の(c) に示すよ
うに、互いがバンプ7 によって接合されるように形成す
る。A semiconductor device to be mounted on the substrate 1 in this way
The semiconductor elements 3 are held on the substrate 1 by positioning the 3 at predetermined positions, and then the substrate 1 is inserted into a high temperature bath and heated to a predetermined temperature to melt the respective bumps 7 collectively. , The terminals 4 and the bumps 2 are formed so that they are joined by the bumps 7 as shown in FIG. 5 (c).
【０００９】この場合、バンプ7 の溶融に際して、端子
4 とバンプ2 との接合が確実に行われるように、通常、
一つの電極4 に対して2 〜3gの加圧となる圧力P が半導
体素子3 に加えられる。In this case, when melting the bumps 7,
To ensure the bond between 4 and bump 2,
A pressure P of 2 to 3 g against one electrode 4 is applied to the semiconductor element 3.
【００１０】最後に、洗浄液によって洗浄し、図５の
(d) に示すように、基板1 と半導体素子3 との間に充填
されたフラックス10の除去を行うことにより、基板1 に
半導体素子3 を実装することが行われていた。Finally, cleaning with a cleaning solution
As shown in (d), the semiconductor element 3 is mounted on the substrate 1 by removing the flux 10 filled between the substrate 1 and the semiconductor element 3.
【００１１】したがって、基板1 に複数の半導体素子3
を位置決め、保持することにより配列させ、基板1 の加
熱により一括してそれぞれの半導体素子3 に固着された
バンプ7 の溶融を行い、バンプ7 のリフロー後は、フラ
ックスの除去を行い、基板1に複数の半導体素子3 を同
時に実装することが行われていた。Therefore, a plurality of semiconductor elements 3 are formed on the substrate 1.
The bumps 7 fixed to each semiconductor element 3 are collectively melted by heating and heating the substrate 1, and the flux is removed after the bump 7 is reflowed. A plurality of semiconductor elements 3 have been mounted at the same time.
【００１２】[0012]
【発明が解決しようとする課題】このようなフラックス
10によって半導体素子3 の保持を行うことでは、バンプ
7 の溶融により電極4 とパッド2 とを接合した後は、フ
ラックス10を除去するよう洗浄が必要となる。しかし、
このようなフラックス10を除去する洗浄では、洗浄液が
残留することがあり、洗浄液の残留が生じると、フラッ
クス10に含まれるハロゲンの影響により腐食が発生す
る。[Problems to be Solved by the Invention]
By holding the semiconductor element 3 by the 10
After the electrode 4 and the pad 2 are joined by melting of 7, the cleaning is required to remove the flux 10. But,
In such cleaning for removing the flux 10, the cleaning liquid may remain, and when the cleaning liquid remains, corrosion occurs due to the influence of the halogen contained in the flux 10.
【００１３】したがって、特に、電極4 およびパッド2
の外形、または、配列ピッチが微細化された場合は、腐
食による接続不良などの障害の発生が増加する問題を有
していた。Therefore, in particular, the electrode 4 and the pad 2
If the outer shape or the arrangement pitch is made finer, there is a problem that the occurrence of failures such as connection failure due to corrosion increases.
【００１４】そこで、本発明では、位置決め後の半導体
素子の保持を確実にすると共に、品質の向上を図ること
を目的とする。Therefore, it is an object of the present invention to ensure the holding of the semiconductor element after positioning and to improve the quality.
【００１５】[0015]
【課題を解決するための手段】図１は、本第１の発明の
原理説明図で、図２は、本第２の発明の原理説明図であ
る。FIG. 1 is an explanatory view of the principle of the first invention, and FIG. 2 is an explanatory view of the principle of the second invention.
【００１６】図１の(a) 〜(c) に示すように、複数の電
極4 を有する半導体素子3 と、該電極3 に対応するパッ
ド2 が配列される基板1 と、該電極4 と該パッド2 との
間を接合する第１のバンプ5 と、第２のバンプ6 とを備
え、該第１のバンプ5 と、該第２のバンプ6 とを予め該
電極4 に固着させ、所定の該電極4 を所定の該パッド2
に合致するよう該半導体素子3 を該基板1 に位置決めす
ることによって該半導体素子3 を該基板1 に保持させ、
該第１のバンプ5 と、該第２のバンプ6 との溶融によっ
て該電極4 と、該パッド2 とを接合する半導体素子の実
装方法であって、前記第２のバンプ6 は溶融温度が前記
第１のバンプ5 より低く、かつ、前記電極4 に固着した
該第２のバンプ6 の突出高さH2が該第１のバンプ5 の突
出高さH1より大となるよう形成し、前記半導体素子3 を
前記基板1 に保持させることが該第２のバンプ6 の溶融
によって行われるように、また、図２の(a) 〜(c) に示
すように、複数の電極4 を有する半導体素子3 と、該電
極4 に対応するパッド2 が配列される基板1 と、該電極
4 と該パッド2 との間を接合するバンプ7 とを備え、該
バンプ7 を予め該電極4 に固着させ、所定の該電極4 を
所定の該パッド2 に合致するよう該半導体素子3 を該基
板1 に位置決めすることによって該半導体素子3 を該基
板1 に保持させ、該バンプ7 の溶融によって該電極4 と
該パッド2 とを接合する半導体素子の実装方法であっ
て、前記電極4 の配列面3A、または、前記パッド2 の配
列面1Aのいずれか一方にゲル状の接着剤8 を塗布し、前
記半導体素子3 を前記基板1 に保持させることが該接着
剤8 によって行われ、かつ、該接着剤8 が前記バンプ7
の溶融と同時に、昇華されるように構成する。As shown in FIGS. 1A to 1C, a semiconductor element 3 having a plurality of electrodes 4, a substrate 1 on which pads 2 corresponding to the electrodes 3 are arranged, the electrodes 4, and A first bump 5 and a second bump 6 for joining between the pad 2 and the pad 2 are provided, and the first bump 5 and the second bump 6 are fixed to the electrode 4 in advance, The electrode 4 to the predetermined pad 2
To hold the semiconductor element 3 on the substrate 1 by positioning the semiconductor element 3 on the substrate 1 so that
A method for mounting a semiconductor element, wherein the first bump 5 and the second bump 6 are melted to bond the electrode 4 and the pad 2, and the second bump 6 has a melting temperature of the above. The semiconductor element is formed so as to be lower than the first bump 5 and the protrusion height H2 of the second bump 6 fixed to the electrode 4 is larger than the protrusion height H1 of the first bump 5. 3 is held on the substrate 1 by melting the second bumps 6, and as shown in FIGS. 2A to 2C, a semiconductor element 3 having a plurality of electrodes 4 is formed. A substrate 1 on which pads 2 corresponding to the electrodes 4 are arranged;
4 and a bump 7 for joining the pad 2 to each other, the bump 7 is fixed to the electrode 4 in advance, and the semiconductor element 3 is attached so that the predetermined electrode 4 is aligned with the predetermined pad 2. A method for mounting a semiconductor element, in which the semiconductor element 3 is held on the substrate 1 by positioning it on the substrate 1, and the electrode 4 and the pad 2 are joined by melting the bump 7, which is an array of the electrodes 4. The adhesive 8 in a gel form is applied to one of the surface 3A or the arrangement surface 1A of the pad 2, and the semiconductor element 3 is held on the substrate 1 by the adhesive 8, and The adhesive 8 is the bump 7
It is configured to be sublimated at the same time as the melting of.
【００１７】このように構成することによって前述の課
題は解決される。The above-mentioned problems can be solved by such a configuration.
【００１８】[0018]
【作用】即ち、第１の発明では、半導体素子3 の電極4
に固着される第２のバンプ6 の突出高さH2を大きく、し
かも、溶融温度を低くすることにより、半導体素子3 を
基板1 に位置決めした時、第２のバンプ6 を溶融させ、
所定のパッド2 に固着させることによって半導体素子3
を基板1 に保持させるようにしたものである。Function: That is, in the first invention, the electrode 4 of the semiconductor element 3 is
When the semiconductor element 3 is positioned on the substrate 1, the second bump 6 is melted by increasing the protrusion height H2 of the second bump 6 fixed to the substrate 1 and lowering the melting temperature.
By fixing it to the specified pad 2, the semiconductor element 3
Is held on the substrate 1.
【００１９】このように構成すると、基板1 を加熱し、
第１のバンプ5 によって半導体素子3 の電極4 をパッド
2 に接合するリフロー後、前述のような洗浄は不要とな
る。また、第２の発明では、電極4 が配列された半導体
素子3 の配列面3Aまたはパッド2 が配列された基板1 の
配列面1Aのいずれか一方にゲル状の接着剤8 を塗布し、
半導体素子3 を基板1 に位置決めした時、接着剤8 の粘
着力によって半導体素子3 の保持が行われ、しかも、接
着剤8 は、バンプ7 の溶融と同時に昇華されるようにし
たものである。With this structure, the substrate 1 is heated,
Pad the electrode 4 of the semiconductor device 3 with the first bump 5.
After the reflow process of joining to 2, the above-mentioned cleaning is not necessary. In the second invention, the gel adhesive 8 is applied to either the array surface 3A of the semiconductor element 3 on which the electrodes 4 are arrayed or the array surface 1A of the substrate 1 on which the pads 2 are arrayed,
The semiconductor element 3 is held by the adhesive force of the adhesive 8 when the semiconductor element 3 is positioned on the substrate 1, and the adhesive 8 is sublimated at the same time when the bumps 7 are melted.
【００２０】このように構成しても、前述と同様、バン
プ7 によって半導体素子3 の電極4をパッド2 に接合す
るリフロー後の洗浄は不要となる。いずれの場合でも、
リフロー後の洗浄が不要となり、洗浄液による障害の発
生を防ぐことができ、信頼性の向上が図れることにな
る。Even with this structure, the cleaning after the reflow for bonding the electrode 4 of the semiconductor element 3 to the pad 2 by the bump 7 is not necessary as in the above. In any case,
Cleaning after the reflow is not necessary, and it is possible to prevent troubles caused by the cleaning liquid and improve reliability.
【００２１】[0021]
【実施例】以下本発明を図３および図４を参考に詳細に
説明する。図３は本第１の発明による一実施例の説明図
で、(a1)〜(a3)は側面図,(b)は半導体素子の平面図,(c)
は第２のバンプの接合図, 図４は本第２の発明による一
実施例の説明図で、(a) 〜(c) は側面図である全図を通
じて、同一符号は同一対象物を示す。DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below with reference to FIGS. FIG. 3 is an explanatory view of an embodiment according to the first invention, (a1) to (a3) are side views, (b) is a plan view of a semiconductor device, and (c).
Is a bonding diagram of the second bump, and FIG. 4 is an explanatory diagram of an embodiment according to the second invention. (A) to (c) are side views, and the same reference numerals denote the same objects. .
【００２２】本発明は、図３の(a1)に示すように、半導
体素子3 の電極4 には第１のバンプ5 と、第２のバンプ
6 とを固着し、所定の電極4 が基板1 の配列面1Aに配列
された所定のパッド2 に合致するよう半導体素子3 を位
置決めし、矢印A のように半導体素子3 を降下させる。According to the present invention, as shown in (a1) of FIG. 3, a first bump 5 and a second bump 5 are provided on the electrode 4 of the semiconductor element 3.
6 are fixed, the semiconductor element 3 is positioned so that the predetermined electrode 4 is aligned with the predetermined pad 2 arranged on the arrangement surface 1A of the substrate 1, and the semiconductor element 3 is lowered as indicated by arrow A.
【００２３】この場合、第１のバンプ5 の突出高さH1
は、第２のバンプ6 の突出高さH2より低く形成され、ま
た、第１のバンプ5 の溶融温度は、第２のバンプ6 の溶
融温度より高く形成されている。In this case, the protruding height H1 of the first bump 5 is
Is formed lower than the protruding height H2 of the second bump 6, and the melting temperature of the first bump 5 is higher than the melting temperature of the second bump 6.
【００２４】そこで、前述の降下によって第１のバンプ
5 の先端がパッド2 に当接する前に第２のバンプ6 の先
端がパッド2 に当接することになるので、第２のバンプ
だけを溶融させる低温の加熱により、図３の(a2)に示す
ように、第２のバンプ6 が固着された電極4 と、パッド
2 とが第２のバンプ6 によって接合され、第１のバンプ
5 先端は、パッド2 に当接される状態で半導体素子3 が
基板1 に保持されることになる。Therefore, the first bump is formed by the above-mentioned descent.
Since the tip of the second bump 6 comes into contact with the pad 2 before the tip of 5 comes into contact with the pad 2, it is shown in (a2) of FIG. 3 by the low temperature heating that melts only the second bump. The electrode 4 to which the second bump 6 is fixed and the pad
2 and 2 are joined by the second bump 6, and the first bump
5 The semiconductor element 3 is held on the substrate 1 while the tip is in contact with the pad 2.
【００２５】したがって、基板1 に複数の半導体素子3
を位置決めし、半導体素子3 を基板1 の配列面1Aに仮固
定することが行える。この場合、第２のバンプ6 によっ
て半導体素子3 を配列面1Aに対して平行に保持させ、位
置ずれが生じることのないように保持を確実するために
は、図３の(b) に示すように、配列面3Aに配列された電
極4 の少なくとも3 箇所に第２のバンプ6 を設ける必要
がある。Therefore, a plurality of semiconductor elements 3 are formed on the substrate 1.
Can be positioned, and the semiconductor elements 3 can be temporarily fixed to the array surface 1A of the substrate 1. In this case, in order to hold the semiconductor elements 3 in parallel with the array surface 1A by the second bumps 6 and to ensure the holding so as not to cause the positional deviation, as shown in FIG. In addition, it is necessary to provide the second bumps 6 on at least three positions of the electrodes 4 arranged on the arrangement surface 3A.
【００２６】また、第２のバンプ6 の接合によって第１
のバンプ5 の先端がパッド2 に当接するように形成する
ことは、図３の(c) に示すように、配列面1Aと3Aと間が
所定の間隔S になるようにすることが望ましい。Further, by joining the second bumps 6,
It is desirable to form the bumps 5 so that the tips of the bumps 5 come into contact with the pads 2 so that a predetermined space S is provided between the array surfaces 1A and 3A, as shown in FIG. 3 (c).
【００２７】このような間隔S が得られるようにするこ
とは、第２のバンプ6 のサイズを増減させ、第２のバン
プ6 の体積V が所定の値になるようにするか、または、
第２のバンプ6 のサイズが所定の大きさであっても、パ
ッド2 の面積が大きい場合は、溶融した時の広がりによ
り、間隔S を小さくすることができ、逆に、パッド2の
面積が狭い場合は、溶融した時の広がりが少なく、間隔
S を大きくすることができる。To obtain such an interval S, the size of the second bump 6 is increased or decreased so that the volume V of the second bump 6 becomes a predetermined value, or
Even if the size of the second bump 6 is a predetermined size, if the area of the pad 2 is large, the space S can be reduced due to the spread when the pad 2 melts. If it is narrow, there is little spread when melted,
S can be increased.
【００２８】したがって、パッド2 の直径D の増減によ
っても、間隔S の調節を行うことができる。基板1 に複
数の半導体素子3 を位置決めし、半導体素子3 を基板1
の配列面1Aに仮固定した後は、例えば、高温槽に基板1
を挿入し、第１のバンプ5 を溶融させる加熱を行い、図
３の(a3)に示すように、第１のバンプ5 を溶融させると
同時に半導体素子3 に所定の圧力P を加えることによ
り、電極4 とパッド2 との接合を行う。Therefore, the spacing S can be adjusted also by increasing or decreasing the diameter D of the pad 2. Position a plurality of semiconductor elements 3 on the board 1 and attach the semiconductor elements 3 to the board 1.
After being temporarily fixed to the array surface 1A of, for example, the substrate 1
By heating to melt the first bumps 5 and melt the first bumps 5 and simultaneously apply a predetermined pressure P to the semiconductor element 3 as shown in (a3) of FIG. Bond electrode 4 and pad 2.
【００２９】このように構成すると、前述のようなリフ
ロー後の洗浄は不要となり、洗浄液による障害を防ぐこ
とができる。また、図４の(a) の場合は、半導体素子3
の電極4 にはバンプ7 を固着し、所定の電極4 が基板1
の配列面1Aに配列された所定のパッド2 に合致するよう
半導体素子3 を位置決めし、矢印A のように半導体素子
3 を降下させる。With this configuration, the cleaning after the reflow as described above becomes unnecessary, and the trouble due to the cleaning liquid can be prevented. In addition, in the case of FIG.
Bumps 7 are fixed to the electrodes 4 of the
Position the semiconductor element 3 so that it matches the specified pad 2 arranged on the arrangement surface 1A of the
Drop 3
【００３０】この場合、基板1 の配列面1A、または、半
導体素子3 の配列面3Aのいずれか一方に例えば、分子量
500 のポリエチレンから成るゲル状の接着剤8 を塗布す
る。( 図４の(a) では基板1 の配列面1Aに塗布した場合
が図示されている。)このような接着剤8 を塗布するこ
とにより、半導体素子3 を配列面1Aに降下させると、図
４の(b) に示すように、バンプ7 の先端をパッド2 と当
接させることにより、接着剤8 の粘着力によって半導体
素子3 を基板1 に保持させることが行える。In this case, for example, the molecular weight may be on either the array surface 1A of the substrate 1 or the array surface 3A of the semiconductor element 3.
Apply a gel adhesive 8 consisting of 500 polyethylene. (In FIG. 4 (a), the case where the semiconductor device 3 is applied to the array surface 1A of the substrate 1 is illustrated.) When the semiconductor element 3 is lowered to the array surface 1A by applying such an adhesive 8, As shown in FIG. 4B, the tip of the bump 7 is brought into contact with the pad 2, so that the semiconductor element 3 can be held on the substrate 1 by the adhesive force of the adhesive 8.
【００３１】そこで、基板1 に複数の半導体素子3 を位
置決めし、半導体素子3 を基板1 の配列面1Aに仮固定し
た後は、前述と同様に、高温槽に基板1 を挿入し、バン
プ7を溶融させる加熱を行い、半導体素子3 に所定の圧
力P を加える。Therefore, after positioning the plurality of semiconductor elements 3 on the substrate 1 and temporarily fixing the semiconductor elements 3 to the array surface 1A of the substrate 1, the substrate 1 is inserted into the high temperature bath and the bumps 7 are formed in the same manner as described above. Is heated to apply a predetermined pressure P 1 to the semiconductor element 3.
【００３２】この場合の加熱温度を、例えば、350 ℃に
すると、バンプ7 の溶融と同時に、接着剤8 は昇華する
ことになり、図４の(c) に示すように、接着剤8 の昇華
と同時に電極4 と、パッド2 とを接合させることが行え
る。When the heating temperature in this case is set to 350 ° C., for example, the adhesive 8 is sublimated at the same time as the bumps 7 are melted, and as shown in FIG. 4 (c), the adhesive 8 is sublimated. At the same time, the electrode 4 and the pad 2 can be joined.
【００３３】このように構成すると、前者のような第２
のバンプ６を溶融する加熱が不要となり、加熱による悪
影響を避けることができ、しかも、前述と同様に、電極
4 をパッド2 に接合するリフロー後の洗浄を不要にする
ことができる。With this configuration, the second type like the former
The heating for melting the bumps 6 is unnecessary, and the adverse effect of the heating can be avoided.
Post-reflow cleaning to bond 4 to pad 2 can be eliminated.
【００３４】[0034]
【発明の効果】以上説明したように、本発明によれば、
第１のバンプと第２のバンプとを設け、半導体素子の位
置決め後の保持が第２のバンプの溶融によって行われる
か、または、バンプの溶融によって昇華される接着剤を
基板に塗布し、半導体素子の位置決め後の保持が接着剤
によって行われることになる。As described above, according to the present invention,
The first bump and the second bump are provided, and the semiconductor element is held after positioning by melting the second bump, or an adhesive that is sublimated by melting the bump is applied to the substrate to form a semiconductor. After the element is positioned, it is held by the adhesive.
【００３５】したがって、従来のようなフラックスを使
用しないため、電極とパッドとを接合するリフロー後の
洗浄が不要となり、洗浄液による障害の発生を防ぎ、信
頼性の向上が図れ、実用的効果は大である。Therefore, since the conventional flux is not used, cleaning after reflow for joining the electrode and the pad is not necessary, the trouble due to the cleaning liquid is prevented, the reliability is improved, and the practical effect is great. Is.
【図１】 本第１の発明の原理説明図FIG. 1 is an explanatory view of the principle of the first invention.
【図２】 本第２の発明の原理説明図FIG. 2 is an explanatory view of the principle of the second invention.
【図３】 本第１の発明による一実施例の説明図FIG. 3 is an explanatory diagram of an embodiment according to the first invention.
【図４】 本第２の発明による一実施例の説明図FIG. 4 is an explanatory diagram of an embodiment according to the second invention.
【図５】 従来の説明図FIG. 5 is a conventional explanatory diagram.
１ 基板 ２ パッド ３ 半導体素子 ４ 電極 ５ 第１のバンプ ６ 第２のバンプ ７ バンプ ８ 接着剤 1 Substrate 2 Pad 3 Semiconductor Element 4 Electrode 5 First Bump 6 Second Bump 7 Bump 8 Adhesive
Claims (2)
と、該電極(4) に対応するパッド(2) が配列される基板
(1) と、該電極(4) と該パッド(2) との間を接合する第
１のバンプ(5) と、第２のバンプ(6) とを備え、該第１
のバンプ(5)と、該第２のバンプ(6) とを予め該電極(4)
に固着させ、所定の該電極(4) を所定の該パッド(2)
に合致するよう該半導体素子(3) を該基板(1) に位置決
めすることによって該半導体素子(3) を該基板(1) に保
持させ、該第１のバンプ(5) と、該第２のバンプ(6) と
の溶融によって該電極(4) と、該パッド(2) とを接合す
る半導体素子の実装方法であって、 前記第２のバンプ(6) は溶融温度が前記第１のバンプ
(5) より低く、かつ、前記電極(4) に固着れた突出高さ
(H2)が該第１のバンプ(5) の突出高さ(H1)より大となる
よう形成され、前記半導体素子(3) を前記基板(1) に保
持させることが該第２のバンプ(6) の溶融によって行わ
れることを特徴とする半導体素子の実装方法。1. A semiconductor device (3) having a plurality of electrodes (4)
And a substrate on which the pads (2) corresponding to the electrodes (4) are arranged
(1), a first bump (5) for joining between the electrode (4) and the pad (2), and a second bump (6).
The bumps (5) and the second bumps (6) of the electrode (4) in advance.
The electrode (4) is fixed to the pad (2)
The semiconductor element (3) is held on the substrate (1) by positioning the semiconductor element (3) on the substrate (1) so as to match the first bump (5) and the second bump (5). A method of mounting a semiconductor element, wherein the electrode (4) and the pad (2) are joined by melting with the bump (6) of the second bump (6), wherein the second bump (6) has a melting temperature of the first bump (6). bump
Lower than (5) and protruding height fixed to the electrode (4)
(H2) is formed to have a height higher than the protrusion height (H1) of the first bump (5), and the second bump (H2) can be held by holding the semiconductor element (3) on the substrate (1). 6) A method for mounting a semiconductor element, which is performed by melting.
と、該電極(4) に対応するパッド(2) が配列される基板
(1) と、該電極(4) と該パッド(2) との間を接合するバ
ンプ(7) とを備え、該バンプ(7) を予め該電極(4) に固
着させ、所定の該電極(4) を所定の該パッド(2) に合致
するよう該半導体素子(3) を該基板(1) に位置決めする
ことによって該半導体素子(3) を該基板(1) に保持さ
せ、該バンプ(7) の溶融によって該電極(4) と該パッド
(2) とを接合する半導体素子の実装方法であって、 前記電極(4) の配列面(3A)、または、前記パッド(2) の
配列面(1A)のいずれか一方にゲル状の接着剤(8) を塗布
し、前記半導体素子(3) を前記基板(1) に保持させるこ
とが該接着剤(8) によって行われ、かつ、該接着剤(8)
が前記バンプ(7) の溶融と同時に、昇華されることを特
徴とする半導体素子の実装方法。2. A semiconductor device (3) having a plurality of electrodes (4)
And a substrate on which the pads (2) corresponding to the electrodes (4) are arranged
(1) and a bump (7) for joining between the electrode (4) and the pad (2), the bump (7) is fixed to the electrode (4) in advance, and the predetermined electrode The semiconductor element (3) is held on the substrate (1) by positioning the semiconductor element (3) on the substrate (1) so that (4) is aligned with the predetermined pad (2), and the bump The electrode (4) and the pad by melting (7)
(2) A method for mounting a semiconductor element, which comprises bonding with a gel-like adhesive on either the array surface (3A) of the electrodes (4) or the array surface (1A) of the pads (2). Applying the agent (8) and holding the semiconductor element (3) on the substrate (1) is performed by the adhesive (8), and the adhesive (8)
The method for mounting a semiconductor element is characterized in that the sublimation is performed at the same time when the bump (7) is melted.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4938194A JPH07263491A (en) | 1994-03-18 | 1994-03-18 | Mounting method for semiconductor element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4938194A JPH07263491A (en) | 1994-03-18 | 1994-03-18 | Mounting method for semiconductor element |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH07263491A true JPH07263491A (en) | 1995-10-13 |
Family
ID=12829450
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4938194A Pending JPH07263491A (en) | 1994-03-18 | 1994-03-18 | Mounting method for semiconductor element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH07263491A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH11111878A (en) * | 1997-10-07 | 1999-04-23 | Denso Corp | Manufacture of semiconductor device |
| US6902098B2 (en) * | 2001-04-23 | 2005-06-07 | Shipley Company, L.L.C. | Solder pads and method of making a solder pad |
-
1994
- 1994-03-18 JP JP4938194A patent/JPH07263491A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH11111878A (en) * | 1997-10-07 | 1999-04-23 | Denso Corp | Manufacture of semiconductor device |
| US6902098B2 (en) * | 2001-04-23 | 2005-06-07 | Shipley Company, L.L.C. | Solder pads and method of making a solder pad |
| US6927492B2 (en) | 2001-04-23 | 2005-08-09 | Shipley Company, L.L.C. | Solder pads and method of making a solder pad |
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