JPH07226356A - 多層レジストを利用したパターン形成方法 - Google Patents

多層レジストを利用したパターン形成方法

Info

Publication number: JPH07226356A
Authority: JP; Japan
Prior art keywords: resist; layer; pattern; forming; intermediate layer
Prior art date: 1993-11-19
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.): Pending

Application number

JP5314066A

Other languages

English (en)

Japanese (ja)

Inventor

Jun Seok Lee

ズン・ソク・リ

Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)

SK Hynix Inc

Original Assignee

LG Semicon Co Ltd

Goldstar Electron Co Ltd

Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)

1993-11-19

Filing date

1993-11-22

Publication date

1995-08-22

1993-11-19 Priority to DE4339466A priority Critical patent/DE4339466C2/de

1993-11-22 Application filed by LG Semicon Co Ltd, Goldstar Electron Co Ltd filed Critical LG Semicon Co Ltd

1993-11-22 Priority to JP5314066A priority patent/JPH07226356A/ja

1995-08-22 Publication of JPH07226356A publication Critical patent/JPH07226356A/ja

Status Pending legal-status Critical Current

Links

238000000034 method Methods 0.000 title claims abstract description 56
229920002120 photoresistant polymer Polymers 0.000 claims description 7
229920003986 novolac Polymers 0.000 claims description 5
230000007261 regionalization Effects 0.000 claims description 5
238000005530 etching Methods 0.000 claims description 3
238000000059 patterning Methods 0.000 claims description 3
238000001228 spectrum Methods 0.000 claims description 3
229910010272 inorganic material Inorganic materials 0.000 claims description 2
239000011147 inorganic material Substances 0.000 claims description 2
230000003287 optical effect Effects 0.000 claims description 2
230000007704 transition Effects 0.000 claims 1
239000000758 substrate Substances 0.000 abstract description 11
230000015572 biosynthetic process Effects 0.000 abstract description 4
238000011161 development Methods 0.000 abstract description 2
238000010438 heat treatment Methods 0.000 abstract description 2
238000005468 ion implantation Methods 0.000 abstract description 2
239000010410 layer Substances 0.000 description 83
239000004065 semiconductor Substances 0.000 description 10
230000002093 peripheral effect Effects 0.000 description 7
230000000694 effects Effects 0.000 description 6
239000003990 capacitor Substances 0.000 description 4
238000007796 conventional method Methods 0.000 description 4
238000010586 diagram Methods 0.000 description 4
238000012546 transfer Methods 0.000 description 3
238000000149 argon plasma sintering Methods 0.000 description 2
230000000903 blocking effect Effects 0.000 description 2
239000011248 coating agent Substances 0.000 description 2
238000000576 coating method Methods 0.000 description 2
230000007547 defect Effects 0.000 description 2
238000013461 design Methods 0.000 description 2
238000002955 isolation Methods 0.000 description 2
238000001459 lithography Methods 0.000 description 2
238000004519 manufacturing process Methods 0.000 description 2
239000000463 material Substances 0.000 description 2
229920000642 polymer Polymers 0.000 description 2
239000000126 substance Substances 0.000 description 2
ALSTYHKOOCGGFT-KTKRTIGZSA-N (9Z)-octadecen-1-ol Chemical compound CCCCCCCC\C=C/CCCCCCCCO ALSTYHKOOCGGFT-KTKRTIGZSA-N 0.000 description 1
VVQNEPGJFQJSBK-UHFFFAOYSA-N Methyl methacrylate Chemical compound COC(=O)C(C)=C VVQNEPGJFQJSBK-UHFFFAOYSA-N 0.000 description 1
XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
230000018109 developmental process Effects 0.000 description 1
239000011521 glass Substances 0.000 description 1
239000012044 organic layer Substances 0.000 description 1
238000000206 photolithography Methods 0.000 description 1
229920003229 poly(methyl methacrylate) Polymers 0.000 description 1
239000004926 polymethyl methacrylate Substances 0.000 description 1
229910052710 silicon Inorganic materials 0.000 description 1
239000010703 silicon Substances 0.000 description 1
239000002356 single layer Substances 0.000 description 1
230000001052 transient effect Effects 0.000 description 1

Classifications

- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step

Landscapes

Engineering & Computer Science (AREA)
Physics & Mathematics (AREA)
Condensed Matter Physics & Semiconductors (AREA)
General Physics & Mathematics (AREA)
Manufacturing & Machinery (AREA)
Computer Hardware Design (AREA)
Microelectronics & Electronic Packaging (AREA)
Power Engineering (AREA)
Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
Photosensitive Polymer And Photoresist Processing (AREA)
Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)

JP5314066A 1993-11-19 1993-11-22 多層レジストを利用したパターン形成方法 Pending JPH07226356A (ja)

Priority Applications (2)

Application Number	Priority Date	Filing Date	Title
DE4339466A DE4339466C2 (de)	1993-11-19	1993-11-19	Verfahren zur Bildung von Mustern unter Verwendung eines Mehrschichtresists
JP5314066A JPH07226356A (ja)	1993-11-19	1993-11-22	多層レジストを利用したパターン形成方法

Applications Claiming Priority (2)

Application Number	Priority Date	Filing Date	Title
DE4339466A DE4339466C2 (de)	1993-11-19	1993-11-19	Verfahren zur Bildung von Mustern unter Verwendung eines Mehrschichtresists
JP5314066A JPH07226356A (ja)	1993-11-19	1993-11-22	多層レジストを利用したパターン形成方法

Publications (1)

Publication Number	Publication Date
JPH07226356A true JPH07226356A (ja)	1995-08-22

Family

ID=25931345

Family Applications (1)

Application Number	Title	Priority Date	Filing Date
JP5314066A Pending JPH07226356A (ja)	1993-11-19	1993-11-22	多層レジストを利用したパターン形成方法

Country Status (2)

Country	Link
JP (1)	JPH07226356A (de)
DE (1)	DE4339466C2 (de)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
US7435682B2 (en)	2004-05-31	2008-10-14	Kabushiki Kaisha Toshiba	Method of manufacturing semiconductor device
US10312074B2 (en)	2014-10-31	2019-06-04	Samsung Sdi Co., Ltd.	Method of producing layer structure, layer structure, and method of forming patterns
US10663863B2 (en)	2015-10-23	2020-05-26	Samsung Sdi Co., Ltd.	Method of producing layer structure, and method of forming patterns
US10770293B2 (en)	2017-08-29	2020-09-08	Taiwan Semiconductor Manufacturing Co., Ltd.	Method for manufacturing a semiconductor device

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
US7262070B2 (en)	2003-09-29	2007-08-28	Intel Corporation	Method to make a weight compensating/tuning layer on a substrate

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
US4891303A (en) *	1988-05-26	1990-01-02	Texas Instruments Incorporated	Trilayer microlithographic process using a silicon-based resist as the middle layer

1993
- 1993-11-19 DE DE4339466A patent/DE4339466C2/de not_active Expired - Fee Related
- 1993-11-22 JP JP5314066A patent/JPH07226356A/ja active Pending

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
US7435682B2 (en)	2004-05-31	2008-10-14	Kabushiki Kaisha Toshiba	Method of manufacturing semiconductor device
US10312074B2 (en)	2014-10-31	2019-06-04	Samsung Sdi Co., Ltd.	Method of producing layer structure, layer structure, and method of forming patterns
US10663863B2 (en)	2015-10-23	2020-05-26	Samsung Sdi Co., Ltd.	Method of producing layer structure, and method of forming patterns
US10770293B2 (en)	2017-08-29	2020-09-08	Taiwan Semiconductor Manufacturing Co., Ltd.	Method for manufacturing a semiconductor device

Also Published As

Publication number	Publication date
DE4339466A1 (de)	1995-05-24
DE4339466C2 (de)	2001-07-19

Publication	Publication Date	Title
JP2707416B2 (ja)	1998-01-28	多層レジストパターン形成方法
US20040102048A1 (en)	2004-05-27	Method for manufacturing semiconductor device
JP3355239B2 (ja)	2002-12-09	パターンの形成方法
US20120171865A1 (en)	2012-07-05	Method for fabricating fine patterns
JP4389242B2 (ja)	2009-12-24	フォトレジストパターンをマスクに利用するエッチング方法
JP2001274063A (ja)	2001-10-05	半導体装置の製造方法
US6569605B1 (en)	2003-05-27	Photomask and method for forming micro patterns of semiconductor device using the same
US5770350A (en)	1998-06-23	Method for forming pattern using multilayer resist
JP3874989B2 (ja)	2007-01-31	パターンの形成方法
KR0135165B1 (ko)	1998-04-22	다층레지스트를 이용한 패턴형성방법
KR102359750B1 (ko)	2022-02-08	교호하는 위상 시프팅 마스크를 사용하는 포토레지스트 아일랜드 패턴들의 개선된 임계 치수(ｃｄ) 균일성
JPH07226356A (ja)	1995-08-22	多層レジストを利用したパターン形成方法
CN109935515B (zh)	2021-07-13	形成图形的方法
JP2009139695A (ja)	2009-06-25	半導体装置の製造方法
JP2010156819A (ja)	2010-07-15	半導体装置の製造方法
US20120214103A1 (en)	2012-08-23	Method for fabricating semiconductor devices with fine patterns
US20060147846A1 (en)	2006-07-06	Method of forming photoresist pattern and semiconductor device employing the same
JP4081793B2 (ja)	2008-04-30	フォトレジストパターンを利用した半導体素子の製造方法
TWI694309B (zh)	2020-05-21	半導體裝置的形成方法
KR20010011143A (ko)	2001-02-15	반도체소자의 미세패턴 형성방법
JP3978852B2 (ja)	2007-09-19	半導体装置の製造方法
JP5007084B2 (ja)	2012-08-22	レジストフロー工程及びコーティング処理工程を含む半導体素子の製造方法
US7087533B2 (en)	2006-08-08	Method for fabricating semiconductor device
JP2000021978A (ja)	2000-01-21	フォトマスクおよびパターン形成方法
US8003303B2 (en)	2011-08-23	Intensity selective exposure method and apparatus

JPH07226356A - 多層レジストを利用したパターン形成方法 - Google Patents

Info

Links

Classifications

Landscapes

Priority Applications (2)

Applications Claiming Priority (2)

Publications (1)

Family

ID=25931345

Family Applications (1)

Country Status (2)

Cited By (4)

Families Citing this family (1)

Family Cites Families (1)

Cited By (4)

Also Published As

Similar Documents