JPH07183740A - Operational amplifier circuit - Google Patents
Operational amplifier circuitInfo
- Publication number
- JPH07183740A JPH07183740A JP5346718A JP34671893A JPH07183740A JP H07183740 A JPH07183740 A JP H07183740A JP 5346718 A JP5346718 A JP 5346718A JP 34671893 A JP34671893 A JP 34671893A JP H07183740 A JPH07183740 A JP H07183740A
- Authority
- JP
- Japan
- Prior art keywords
- operational amplifier
- inverting
- inverting input
- amplification
- resistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、電動機の制御装置に用
いて好適な演算増幅回路に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an operational amplifier circuit suitable for use in a motor control device.
【０００２】[0002]
【従来の技術】電動機制御装置では、開閉手段によっ
て、増幅回路あるいは積分回路の符号を反転もしくは非
反転とする機能が必要とされる場合がある。特に、電動
機が駆動する機構の機械共振を制御する装置では、フィ
ードバック補償器の構成や機械振動の周波数に応じて観
測した機械振動信号の位相を調整する必要があるため、
スイッチ等の開閉手段によって、増幅器の符号を反転あ
るいは非反転としなければならない。そこで、第１の従
来技術として、図３に示すように増幅度Ａの２個の演算
増幅器と１個の切換手段Ｓを用いて演算増幅回路を構成
する方法がある。図において演算増幅回路のゲインは可
変抵抗器ＶＲ１で変えている。切換手段Ｓを端子ａに接
続すると非反転増幅回路となり、端子ｂに接続すると反
転増幅回路となる。また、第２の従来例として、図４に
示すように１個の演算増幅器１と１個の開閉手段Ｋを用
いて演算増幅回路を構成する方法がある。開閉手段Ｋを
開とすると非反転増幅回路となり、閉とすると反転増幅
回路となる。Ｒ１、Ｒ２は抵抗、Ｚ３はインピーダンス
である。2. Description of the Related Art In a motor control device, there is a case where a function of inverting or non-inverting the sign of an amplifier circuit or an integrating circuit is required depending on the opening / closing means. In particular, in the device that controls the mechanical resonance of the mechanism driven by the electric motor, it is necessary to adjust the phase of the observed mechanical vibration signal according to the configuration of the feedback compensator and the frequency of mechanical vibration.
The sign of the amplifier must be inverted or non-inverted by an opening / closing means such as a switch. Therefore, as a first conventional technique, there is a method of forming an operational amplifier circuit by using two operational amplifiers having an amplification degree A and one switching means S as shown in FIG. In the figure, the gain of the operational amplifier circuit is changed by the variable resistor VR1. When the switching means S is connected to the terminal a, it becomes a non-inverting amplifier circuit, and when it is connected to the terminal b, it becomes an inverting amplifier circuit. As a second conventional example, there is a method of forming an operational amplifier circuit using one operational amplifier 1 and one switching means K as shown in FIG. When the opening / closing means K is opened, it becomes a non-inverting amplifier circuit, and when it is closed, it becomes an inverting amplifier circuit. R1 and R2 are resistors, and Z3 is impedance.
【０００３】[0003]
【発明が解決しようとする課題】ところが、第１の従来
技術では、符号の反転をするためだけに、演算増幅器が
１個余分に必要となる欠点がある。即ち、演算増幅器１
個だけでは、目的とする演算増幅回路の構成が不可能で
あった。第２の従来例では、インピーダンスＺ３が抵抗
でかつ増幅度Ａが１のとき、すなわちＺ３＝Ｒ１のとき
だけしか目的とする演算増幅回路が構成できなかった。
すなわち、反転増幅時の増幅度は、入力インピーダンス
と増幅度が非常に大きい理想的な増幅手段を仮定する
と、 Ｇi ＝Ｚ3 ／Ｒ1 （１） となる。非反転増幅時の増幅度も同様にHowever, the first prior art has a drawback in that an extra operational amplifier is required only to invert the sign. That is, the operational amplifier 1
It was not possible to construct the target operational amplifier circuit with only one unit. In the second conventional example, the target operational amplifier circuit can be constructed only when the impedance Z3 is a resistance and the amplification degree A is 1, that is, when Z3 = R1.
That is, the amplification factor at the time of inverting amplification is G i = Z 3 / R 1 (1), assuming an ideal amplification means having an extremely large input impedance and amplification factor. The degree of amplification during non-inverting amplification is also the same.
【０００４】[0004]
【数１】 [Equation 1]
【０００５】であるが、演算増幅器の増幅度Ａが非常に
大きいので、 Ｇn ＝１ （３） となる。（１）式と（３）式より、反転増幅時と非反転
増幅時とで演算特性が全く異なることがわかる。上記の
ように、従来技術では、反転増幅時と非反転増幅時で同
一の機能（増幅、積分あるいは不完全積分等）を持った
演算増幅回路を構成することができないという問題点が
あった。そこで本発明は、１個の演算増幅器によって、
反転増幅時と非反転増幅時で同一の機能（増幅、積分あ
るいは不完全積分等）を持った演算増幅回路を構成する
ことを目的とする。However, since the amplification degree A of the operational amplifier is very large, G n = 1 (3). From the equations (1) and (3), it can be seen that the operational characteristics are completely different between the inverting amplification and the non-inverting amplification. As described above, the conventional technique has a problem in that it is not possible to configure an operational amplifier circuit having the same function (amplification, integration, incomplete integration, etc.) during inverting amplification and non-inverting amplification. Therefore, the present invention uses one operational amplifier to
It is an object to configure an operational amplifier circuit having the same function (amplification, integration, incomplete integration, etc.) during inverting amplification and non-inverting amplification.
【０００６】[0006]
【課題を解決するための手段】上記の問題を解決するた
めに、本発明では、演算増幅回路を、反転入力部と非反
転入力部を備えた演算増幅器と、信号入力端と前記反転
入力部および前記非反転入力部とをそれぞれ接続する第
１、第２の抵抗器と、一端を前記演算増幅器の出力部に
接続し、他端を接地する可変抵抗器と、前記可変抵抗器
の摺動端と前記演算増幅器の反転入力部を接続する第３
の抵抗器と、前記非反転入力部を接地あるいは非接地と
する開閉手段とを備え、前記第１、第３の抵抗器の抵抗
値を等しくする。あるいは、演算増幅回路を、反転入力
部と非反転入力部を備えた演算増幅器と、入力信号を一
端あるいは他端に切り換える切換手段と、前記切換手段
の一端と前記反転入力部とを接続する第１の抵抗器と、
前記切換手段の他端と前記非反転入力部とを接続する第
２の抵抗器と、一端を前記反転入力部に接続し他端を接
地する第３の抵抗器と、一端を前記演算増幅器の出力部
に接続し、他端を接地する可変抵抗器と、前記可変抵抗
器の摺動端と前記演算増幅器の反転入力部とを接続する
第１のインピーダンスと、前記演算増幅器の非反転入力
部に一端を接続し他端を接地する第２のインピーダンス
とを備え、前記第１、第２、第３の抵抗器の抵抗値を等
しくするとともに、前記第１のインピーダンスと第２の
インピーダンスの値を等しくする。In order to solve the above problems, in the present invention, an operational amplifier circuit includes an operational amplifier having an inverting input section and a non-inverting input section, a signal input terminal and the inverting input section. And first and second resistors respectively connecting the non-inverting input section, a variable resistor having one end connected to the output section of the operational amplifier and the other end grounded, and sliding of the variable resistor. A third connecting the end and the inverting input of the operational amplifier
And the opening / closing means for grounding or non-grounding the non-inverting input section, and the resistance values of the first and third resistors are made equal. Alternatively, the operational amplifier circuit includes an operational amplifier having an inverting input section and a non-inverting input section, switching means for switching an input signal to one end or the other end, and one end for connecting the one end of the switching means and the inverting input section. 1 resistor,
A second resistor connecting the other end of the switching means to the non-inverting input unit, a third resistor having one end connected to the inverting input unit and the other end grounded, and one end of the operational amplifier. A variable resistor connected to the output part and having the other end grounded, a first impedance connecting the sliding end of the variable resistor and the inverting input part of the operational amplifier, and a non-inverting input part of the operational amplifier. A second impedance having one end connected to the other end and the other end grounded, the resistance values of the first, second, and third resistors being equalized, and the values of the first impedance and the second impedance. Are equal.
【０００７】[0007]
【作用】第１の手段によると、可変抵抗器の一端を前記
増幅手段の出力部に接続し、他端を接地し、摺動端と前
記増幅手段の反転入力部を第３の抵抗器で接続するの
で、反転増幅時と非反転増幅時とで増幅度が同一とな
る。また、第２の手段によると、反転増幅時には演算増
幅器の反転入力と非反転入力が共にゼロ電位となるの
で、第１の抵抗器と第１のインピーダンスと可変抵抗器
とで演算機能が定まり、非反転増幅時には第２、第３の
抵抗器および第１、第２のインピーダンスと可変抵抗器
で演算機能が定まり、前記各抵抗器の抵抗値を等しく、
前記各インピーダンスの値を等しくすることにより、非
反転増幅時と反転増幅時とで同一の演算機能が実現でき
る。According to the first means, one end of the variable resistor is connected to the output part of the amplifying means, the other end is grounded, and the sliding end and the inverting input part of the amplifying means are connected by the third resistor. Since they are connected, the amplification degree is the same during inverting amplification and during non-inverting amplification. Further, according to the second means, since the inverting input and the non-inverting input of the operational amplifier both become zero potential during the inverting amplification, the computing function is determined by the first resistor, the first impedance and the variable resistor. At the time of non-inverting amplification, the arithmetic function is determined by the second and third resistors and the first and second impedances and the variable resistor, and the resistance values of the respective resistors are equal,
By making the values of the impedances equal, the same arithmetic function can be realized during non-inverting amplification and during inverting amplification.
【０００８】[0008]
【実施例】以下、本発明の具体的実施例を説明する。本
発明の第１の実施例を図１に示す。図１において、入力
端と増幅手段１の反転入力部（以下−で示す）とを抵抗
Ｒ１で接続し、入力端と増幅手段の非反転入力部（以下
＋で示す）とを抵抗Ｒ２で接続し、増幅手段１の出力に
可変抵抗器ＶＲ１の一端を接続し、他端を接地し、可変
抵抗器ＶＲ１の摺動端と増幅手段１の反転入力−とを抵
抗器Ｒ３で接続し、非反転入力を開閉手段Ｋを通して接
地する。この演算増幅回路は、開閉手段Ｋが短絡状態で
は、反転増幅器となり、開閉手段Ｋが開状態では、非反
転増幅器となる。増幅度は可変抵抗器ＶＲ１で自由に増
減できる。可変抵抗器ＶＲ１の摺動端の電圧Ｖαは Ｖα＝αＶ0 （４） となる。ここで、αは可変抵抗器ＶＲ１の摺動片の位置
に関して定まり、０≦α≦１である。Ｖ0 は出力電圧で
ある。反転増幅時は非反転入力がゼロ電位となるため増
幅度は、入力インピーダンスと増幅度が非常に大きい理
想的な増幅手段を仮定すると、 Ｇi ＝（−１／α）（Ｒ3 ／Ｒ1 ） （５） となる。非反転時は非反転入力の電位が入力電圧Ｖi と
等しくなるので、増幅度はEXAMPLES Specific examples of the present invention will be described below. A first embodiment of the present invention is shown in FIG. In FIG. 1, the input end and the inverting input portion (hereinafter indicated by −) of the amplifying means 1 are connected by a resistor R1, and the input end and the non-inverting input portion of the amplifying means (hereinafter indicated by +) are connected by a resistor R2. Then, one end of the variable resistor VR1 is connected to the output of the amplifying means 1, the other end is grounded, and the sliding end of the variable resistor VR1 and the inverting input-of the amplifying means 1 are connected by the resistor R3, and The inverting input is grounded through the opening / closing means K. This operational amplifier circuit serves as an inverting amplifier when the opening / closing means K is short-circuited, and serves as a non-inverting amplifier when the opening / closing means K is open. The amplification degree can be freely increased or decreased by the variable resistor VR1. The voltage Vα at the sliding end of the variable resistor VR1 is Vα = αV 0 (4). Here, α is determined with respect to the position of the sliding piece of the variable resistor VR1, and 0 ≦ α ≦ 1. V 0 is the output voltage. Since the non-inverting input has a zero potential during inverting amplification, the amplification factor is G i = (− 1 / α) (R 3 / R 1 supposing an ideal amplification means having a very large input impedance and amplification factor. ) (5) At the time of non-inverting, the potential of the non-inverting input becomes equal to the input voltage V i , so the amplification degree is
【０００９】[0009]
【数２】 [Equation 2]
【００１０】であるが、増幅手段１の増幅度Ａが非常に
大きいので、 Ｇn ＝１／α （７） となる。（５）式と（７）式より、Ｒ１＝Ｒ３のとき、
反転増幅時と非反転増幅時で符号の反転以外の演算機能
（増幅度の設定）が一致する。本発明の第２の実施例を
図２に示す。図２において、切換手段Ｓは入力電圧Ｖi
を一端ａあるいは他端ｂに切り換える。前記切換手段Ｓ
の一端ａと演算増幅器１の反転入力部とを抵抗Ｒ１で接
続し、前記切換手段Ｓの他端ｂと演算増幅器１の非反転
入力部とを抵抗Ｒ２で接続し、前記演算増幅器１の出力
側に可変抵抗器ＶＲ１の一端を接続し、他端を接地し、
可変抵抗器ＶＲ１の摺動端と演算増幅器１の反転入力部
とをインピーダンスＺ１で接続し、演算増幅器１の非反
転入力部をインピーダンスＺ２を通して接地する。切換
手段Ｓがａの時は、演算増幅器１の非反転入力部がゼロ
電位となるので、出力電圧Ｖ0 は、入力インピーダンス
と増幅度が非常に大きい理想的な演算増幅器を仮定する
と、 Ｖ0 ＝（−１／α）（Ｚ１・Ｖi ／Ｒ１） （８） となる。切換手段Ｓがｂの時は、非反転入力部の電位が
入力電位と等しくなるので、演算増幅器１の増幅度をＡ
とすると出力電圧Ｖ0 は、However, since the amplification degree A of the amplifying means 1 is very large, G n = 1 / α (7). From equations (5) and (7), when R1 = R3,
The arithmetic functions (setting of the amplification degree) other than the inversion of the sign are the same during the inverting amplification and the non-inverting amplification. The second embodiment of the present invention is shown in FIG. In FIG. 2, the switching means S has an input voltage V i.
Is switched to one end a or the other end b. The switching means S
Of the operational amplifier 1 is connected to the inverting input of the operational amplifier 1 by a resistor R1, and the other end b of the switching means S is connected to the non-inverting input of the operational amplifier 1 by a resistor R2. Connect one end of the variable resistor VR1 to the side and ground the other end,
The sliding end of the variable resistor VR1 and the inverting input portion of the operational amplifier 1 are connected by the impedance Z1, and the non-inverting input portion of the operational amplifier 1 is grounded through the impedance Z2. When switching means S is a, since the non-inverting input of the operational amplifier 1 becomes the zero potential, the output voltage V 0 is the amplification of the input impedance is assumed very large ideal operational amplifier, V 0 = (− 1 / α) (Z1 · V i / R1) (8) When the switching means S is b, the potential of the non-inverting input section becomes equal to the input potential, so the amplification degree of the operational amplifier 1 is set to A.
Then, the output voltage V 0 is
【００１１】[0011]
【数３】 [Equation 3]
【００１２】となる。ここで、演算増幅器１の増幅度Ａ
が非常に大きいので、出力Ｖ0 は、[0012] Here, the amplification degree A of the operational amplifier 1
Is very large, the output V 0 is
【００１３】[0013]
【数４】 [Equation 4]
【００１４】となる。（８）式と（１０）式において Ｒ＝Ｒ１＝Ｒ２＝Ｒ３、Ｚ＝Ｚ１＝Ｚ２ とおくと、（８）式と（１０）式はそれぞれ Ｖ0 ＝（−１／α）（Ｚ／Ｒ）Ｖi （１２ａ） Ｖ0 ＝（１／α）（Ｚ／Ｒ）Ｖi （１２ｂ） となる。（１２ａ）、（１２ｂ）式より、反転増幅時と
非反転増幅時で符号の反転以外は同一の機能を持つこと
が説明できる。なお、反転時、非反転時にかかわらずゲ
インはαで可変できる。なお、（１２ａ）、（１２ｂ）
式のインピーダンスを抵抗とすれば、増幅回路は、反転
／非反転の増幅回路となり、インピーダンスを容量性Ｚ
＝１／ｊωｃとすれば、増幅回路は反転／非反転の積分
器となる。また、Ｚ＝Ｒ＋１／ｊωｃとすると増幅回路
は反転／非反転の不完全積分器に、誘導性インピーダン
スＺ＝ｊωＬとすると、反転／非反転の微分器となる。[0014] When R = R1 = R2 = R3 and Z = Z1 = Z2 in the equations (8) and (10), the equations (8) and (10) are respectively V 0 = (− 1 / α) (Z / R) V i (12a) V 0 = (1 / α) (Z / R) V i (12b). From equations (12a) and (12b), it can be explained that the same function is provided during inverting amplification and during non-inverting amplification except for inverting the sign. The gain can be changed by α regardless of whether it is inverted or not. Note that (12a) and (12b)
If the impedance of the equation is taken as a resistance, the amplifier circuit becomes an inverting / non-inverting amplifier circuit, and the impedance becomes a capacitive Z
= 1 / jωc, the amplifier circuit becomes an inverting / non-inverting integrator. Further, when Z = R + 1 / jωc, the amplifier circuit becomes an inverting / non-inverting incomplete integrator, and when inductive impedance Z = jωL, the amplifier circuit becomes an inverting / non-inverting differentiator.
【００１５】[0015]
【発明の効果】以上述べたように、本発明によれば、増
幅手段が一個であっても、反転増幅時と非反転増幅時で
符号の反転以外は同一の機能（増幅、積分あるいは不完
全積分等）を持った演算増幅回路を構成することができ
る。As described above, according to the present invention, even if there is only one amplifying means, the same function (amplification, integration or incompleteness) is obtained during inverting amplification and non-inverting amplification except for inverting the sign. It is possible to configure an operational amplifier circuit having integration (or the like).
【図１】本発明の第１の実施例を説明する図。FIG. 1 is a diagram illustrating a first embodiment of the present invention.
【図２】本発明の第２の実施例を説明する図。FIG. 2 is a diagram illustrating a second embodiment of the present invention.
【図３】第１の従来技術を説明する図。FIG. 3 is a diagram illustrating a first conventional technique.
【図４】第２の従来技術を説明する図。FIG. 4 is a diagram illustrating a second conventional technique.
１ 演算装置 Ｒ１、Ｒ２、Ｒ３ 抵抗 Ａ 増幅度 ＶＲ１ 可変抵抗器 Ｚ１、Ｚ２、Ｚ３ インピーダンス Ｋ 開閉手段 Ｓ 切換手段 Ｖi 入力電圧 Ｖ0 出力電圧1 arithmetic unit R1, R2, R3 resistor A amplification degree VR1 variable resistor Z1, Z2, Z3 impedance K closing means S switching means V i input voltage V 0 Output voltage
Claims (2)
増幅器と、信号入力端と前記反転入力部および前記非反
転入力部とをそれぞれ接続する第１、第２の抵抗器と、
一端を前記演算増幅器の出力部に接続し、他端を接地す
る可変抵抗器と、前記可変抵抗器の摺動端と前記演算増
幅器の反転入力部を接続する第３の抵抗器と、前記非反
転入力部を接地あるいは非接地とする開閉手段とを備
え、前記第１、第３の抵抗器の抵抗値を等しくしたこと
を特徴とする演算増幅回路。1. An operational amplifier having an inverting input section and a non-inverting input section, and first and second resistors for connecting a signal input terminal to the inverting input section and the non-inverting input section, respectively.
A variable resistor having one end connected to the output of the operational amplifier and the other end grounded; a third resistor connecting a sliding end of the variable resistor and an inverting input of the operational amplifier; An operational amplifier circuit comprising: an opening / closing means for grounding or non-grounding the inverting input portion, wherein the resistance values of the first and third resistors are made equal.
増幅器と、入力信号を一端あるいは他端に切り換える切
換手段と、前記切換手段の一端と前記反転入力部とを接
続する第１の抵抗器と、前記切換手段の他端と前記非反
転入力部とを接続する第２の抵抗器と、一端を前記反転
入力部に接続し他端を接地する第３の抵抗器と、一端を
前記演算増幅器の出力部に接続し、他端を接地する可変
抵抗器と、前記可変抵抗器の摺動端と前記演算増幅器の
反転入力部とを接続する第１のインピーダンスと、前記
演算増幅器の非反転入力部に一端を接続し他端を接地す
る第２のインピーダンスとを備え、前記第１、第２、第
３の抵抗器の抵抗値を等しくするとともに、前記第１の
インピーダンスと第２のインピーダンスの値を等しくし
たことを特徴とする演算増幅回路。2. An operational amplifier having an inverting input section and a non-inverting input section, switching means for switching an input signal to one end or the other end, and a first connecting the one end of the switching means and the inverting input section. A resistor, a second resistor connecting the other end of the switching means and the non-inverting input unit, a third resistor having one end connected to the inverting input unit and the other end grounded, and one end A variable resistor connected to the output part of the operational amplifier and having the other end grounded; a first impedance connecting the sliding end of the variable resistor and the inverting input part of the operational amplifier; A second impedance having one end connected to the non-inverting input part and the other end grounded, the resistance values of the first, second, and third resistors being made equal, and the first impedance and the second impedance being equal to each other. Characterized by equalizing the impedance values of Operational amplifier circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5346718A JPH07183740A (en) | 1993-12-21 | 1993-12-21 | Operational amplifier circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5346718A JPH07183740A (en) | 1993-12-21 | 1993-12-21 | Operational amplifier circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH07183740A true JPH07183740A (en) | 1995-07-21 |
Family
ID=18385349
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5346718A Pending JPH07183740A (en) | 1993-12-21 | 1993-12-21 | Operational amplifier circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH07183740A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002008942A (en) * | 2000-06-16 | 2002-01-11 | Fujitsu Ltd | Capacitor device, method of manufacturing the same, and module mounted with the device |
-
1993
- 1993-12-21 JP JP5346718A patent/JPH07183740A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002008942A (en) * | 2000-06-16 | 2002-01-11 | Fujitsu Ltd | Capacitor device, method of manufacturing the same, and module mounted with the device |
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