JPH07140443A - Method for driving liquid crystal element - Google Patents
Method for driving liquid crystal elementInfo
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- JPH07140443A JPH07140443A JP10869594A JP10869594A JPH07140443A JP H07140443 A JPH07140443 A JP H07140443A JP 10869594 A JP10869594 A JP 10869594A JP 10869594 A JP10869594 A JP 10869594A JP H07140443 A JPH07140443 A JP H07140443A
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- liquid crystal
- period
- selection period
- pulse
- scanning
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- Liquid Crystal Display Device Control (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、液晶素子に関し、特に
メモリー性を有する液晶を用いた電気光学素子（液晶素
子）の駆動方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal element, and more particularly to a method for driving an electro-optical element (liquid crystal element) using liquid crystal having a memory property.
【０００２】[0002]
【従来の技術】従来、メモリー性を有する強誘電性液晶
素子のマルチプレッシング駆動方法としては、特願昭５
９−８５４８１の「液晶素子の駆動方法」が提案されて
いる。図１（ａ）（ｂ）に特願昭５９一８５４８１の駆
動波形を示す。走査電極Ｖｔには、所定周期毎の選択時
間ｔ0内の最初のｔ1には、パルス幅ｔ1，波高値−Ｖ0の
消去パルスを印加し、残りのｔ2間には、周期２ｔ4，パ
ルス幅ｔ4，波高値＋２Ｖ1で消去パルスと逆符号の選択
パルス列を印加する。一方、信号電極Ｖdには、周期２
ｔ4，パルス幅ｔ4，波高値±Ｖ1の表示パルス列を選択
時間の最後のｔ3間だけ印加する。2. Description of the Related Art Conventionally, as a method for driving a ferroelectric liquid crystal device having a memory property, Japanese Patent Application No.
9-85481 "Method of driving liquid crystal element" has been proposed. 1 (a) and 1 (b) show driving waveforms of Japanese Patent Application No. 59-85148. The scanning electrodes Vt, the first t 1 within the selected time t 0 for each predetermined period, the pulse width t 1, and applying the erase pulse crest value -V 0, Between remaining t 2, the period 2t 4 , the pulse width t 4 , the peak value + 2V 1 , and the selection pulse train having the opposite sign to the erase pulse is applied. On the other hand, the signal electrode Vd has a period of 2
A display pulse train having t 4 , pulse width t 4 , and peak value ± V 1 is applied only for the last t 3 of the selection time.
【０００３】また、特許出願済みの駆動波形及び液晶に
印加される波形を図２に示す。走査電極Ｘ1 には、選択
期間ｔ0 内に液晶の飽和値を越えるＶ1 及びＶ2 の波高
値及び、極性の異なる電圧パルスをパルス幅ｔ3 ｔ4 で
それぞれ印加し、非選択期間ｔl 内は零Ｖが印加され
る。一方信号電極Ｙ1 には、選択期間ｔ0 内の電圧パル
スＶ1 ，Ｖ2 とそれぞれ同一極性で波高値がＶ3 でパル
ス幅がｔ3 以下の正負電圧パルスを、又光透過状態を別
の状態にする時は、選択期間ｔ0 の時間零Ｖにされる。FIG. 2 shows the driving waveforms for which a patent has been applied and the waveforms applied to the liquid crystal. During the selection period t 0 , the pulse values of V 1 and V 2 that exceed the saturation value of the liquid crystal and voltage pulses of different polarities are applied to the scan electrode X 1 with a pulse width t 3 t 4 , respectively, and the non-selection period t Zero V is applied in l . On the other hand, to the signal electrode Y 1 , positive and negative voltage pulses having the same polarity as the voltage pulses V 1 and V 2 in the selection period t 0 , a crest value of V 3 and a pulse width of t 3 or less, and the light transmission state are different. When the state is set to 0 , the time is set to 0V during the selection period t 0 .
【０００４】これらの駆動方法は、非選択時に液晶に
は、他の画素の選択内容及び多重度に関係なく液晶のし
きい値以下で常に正負電圧パルスの直流成分の平均値が
零となるように構成されており、液晶の劣化防止、及
び、液晶のしきい値に与えるパルス幅依存性、累積応等
効果等による液晶の選択内容変化防止の特徴がある。In these driving methods, when the liquid crystal is not selected, the average value of the DC components of the positive and negative voltage pulses is always zero below the threshold value of the liquid crystal regardless of the selection contents of other pixels and the multiplicity. It is characterized by preventing deterioration of the liquid crystal and preventing changes in the selection content of the liquid crystal due to the pulse width dependence of the threshold value of the liquid crystal, cumulative response effect, and the like.
【０００５】[0005]
【発明が解決しようとする課題】上記従来の駆動方法に
おいてはいずれの場合も選択期間内に消去パルスを印加
している。しかし、最近の我々の数々の実験によれば、
図３に示すような波形を液晶電気光学素子に印加した場
合その光透過特性は、図４に示すように、メモリー性の
低下現象が認められることが判明した。ところが、図５
に求すような波形を液晶電気光学素子に印加した場合の
図６に示した光透過特性は、メモリー性の低下現像が認
められない。この現象の原因については現在検討中であ
るが、実際のマルチプレックス駆動においては、メモリ
ー性の低下が起こり好ましくない。In any of the above-mentioned conventional driving methods, the erase pulse is applied within the selection period. However, according to our recent experiments,
When a waveform as shown in FIG. 3 was applied to the liquid crystal electro-optical element, it was found that the light transmission characteristics showed a phenomenon of deterioration in memory property as shown in FIG. However, Figure 5
In the light transmission characteristics shown in FIG. 6 when a waveform as shown in FIG. The cause of this phenomenon is currently under study, but in actual multiplex driving, the memory property deteriorates, which is not preferable.
【０００６】本発明は、消去パルスを選択期間外に印加
する事で上記問題点を解決し、良好なコントラストを長
時間にわたって維持できる強誘電性液晶電気光学素子を
提供することを目的とする。An object of the present invention is to provide a ferroelectric liquid crystal electro-optical element which solves the above problems by applying an erasing pulse outside the selection period and which can maintain good contrast for a long time.
【０００７】[0007]
【課題を解決するための手段】本発明は、それぞれの交
差部で画素を形成する走査電極群と信号電極群を有し、
該走査電極群と信号電極群の間にメモリー性を有する液
晶を配置してなる液晶素子を線順次走査方式により駆動
してなる液晶素子の駆動方法であって、前記各走査電極
に電圧を印加する周期中に、当該走査電極を選択して表
示信号に応じた電圧を印加する選択期間と、当該走査電
極を選択せずに他の走査電極を選択する非選択期間とを
有し、前記各走査電極の非選択期間中に、当該走査電極
に対応する画素の液晶分子を一方向に揃えるためのパル
スを印加する期間を設け、この後所定期間後に前記選択
期間となるようにしたことを特徴とする。The present invention has a scanning electrode group and a signal electrode group which form pixels at respective intersections,
A method for driving a liquid crystal element, which comprises driving a liquid crystal element having a memory property between the scan electrode group and the signal electrode group by a line-sequential scanning method, wherein a voltage is applied to each of the scan electrodes. In the cycle, a selection period in which the scan electrode is selected and a voltage according to a display signal is applied, and a non-selection period in which another scan electrode is selected without selecting the scan electrode are included. In the non-selection period of the scan electrode, a period for applying a pulse for aligning liquid crystal molecules of pixels corresponding to the scan electrode in one direction is provided, and thereafter, the selection period comes after a predetermined period. And
【０００８】[0008]
【実施例】以下に本発明の詳細を実施例を挙げて説明す
る。EXAMPLES The details of the present invention will be described below with reference to examples.
【０００９】本発明の強誘電性スメクチック液晶のマル
チブレッシング駆動波形を図７に示す。液晶素子は一対
の基板に形成された走査電極群Ｘと信号電極群Ｙからな
る対向透明電極間に、メモリー性を有する液晶を封入し
て構成される。周知のように、一対の対向電極の交差部
に画素が形成される。FIG. 7 shows a multi-blessing drive waveform of the ferroelectric smectic liquid crystal of the present invention. The liquid crystal element is configured by enclosing a liquid crystal having a memory property between opposing transparent electrodes formed of a scanning electrode group X and a signal electrode group Y formed on a pair of substrates. As is well known, pixels are formed at the intersections of a pair of counter electrodes.
【００１０】走査電極Ｘ1 には、選択期間ｔ0 内に、パ
ルス幅ｔ3 で零Ｖ、及び、パルス幅ｔ4 で液晶の飽和値
を越える電圧−Ｖ2 を印加し、非選択期間ｔl 内には、
期間ｔ5 及び期間ｔ7 は零Ｖ、パルス幅ｔ6 で液晶の飽
和値を越える選択期間に印加される電圧パルスと逆極性
の電圧パルスを印加する。一方、信号電極Ｙ1 には、選
択期間ｔ0 内の電圧パルス−Ｖ2 と逆極性で波高値がＶ
3 、パルス幅ｔ3 の電圧パルス及び電圧パルス−Ｖ2 と
同極性で波高値が−Ｖ3 、パルス幅ｔ4 の電圧パルスを
印加し、又、光透過状態を別の状態にするときは、選択
期間にそれぞれ逆極性の波高値−Ｖ3 ，Ｖ3の電圧パル
スを印加する。During the selection period t 0 , zero V with a pulse width t 3 and a voltage −V 2 with a pulse width t 4 that exceeds the saturation value of the liquid crystal are applied to the scan electrode X 1 , and the non-selection period t Within l
In the periods t 5 and t 7, a voltage pulse having a voltage of 0 V and a pulse width t 6 and having a polarity opposite to that of the voltage pulse applied in the selection period exceeding the saturation value of the liquid crystal is applied. On the other hand, the signal electrode Y 1 has a crest value of V with a polarity opposite to that of the voltage pulse −V 2 in the selection period t 0 .
3, the pulse width t 3 of the voltage pulse and the voltage pulse -V 2 and a peak value -V 3 in the same polarity, and applying a voltage pulse having a pulse width t 4, also when the light transmission state to another state is , And voltage pulses having peak values −V 3 and V 3 of opposite polarities are applied during the selection period.
【００１１】波高値の設定は次のように行った。合成波
形のＶ1 −Ｖ3 ，Ｖ1 ＋Ｖ3の値は液晶の飽和電圧以
上、−Ｖ2 ＋Ｖ3 は液晶の飽和電圧未満、−Ｖ2 −Ｖ3
は液晶の飽和値以上となるように設定した。本合成波形
を液晶電気光学素子に印加したときの光応答特性にはメ
モリーの低下も認められず、波高値Ｖ1 ±Ｖ3 の消去パ
ルスの位置を移動させる事で階調表示も可能となった。
同時に本発明は、選択期間内に液晶を一方向に揃えるた
めの消去パルスを印加するマルチブレッシング駆動方法
すべてに応用できる。図７においては、すでに出願済の
駆動波形の消去パルスを選択期間内から非選択期間内へ
移動させるという非常に簡便な方法であるが、メモリー
性の維持、及び階調表示が容易である。 （実施例１）本実施例では、液晶材料にＤＯＢＡＭＢＣ
（Ｐ−decyloxybenzyliden Ｐ’−amino−２−methylb
utyl cinnamata ）を使用し、液晶層厚１．０μｍ，ｔ
o ＝２００μｓ，ｔ1 ＝３ｍｓ，ｔ3 ＝ｔ4 ＝ｔ6 ＝１
００μｓ，ｔ5 ＝２．４ｍｓ，ｔ7 ＝５００μｓ，Ｖ1
＝２０Ｖ，Ｖ2 ＝−２３Ｖ，Ｖ3 ＝４Ｖ としたところ
１：２１のコントラストが得られた。The crest value was set as follows. The values of V 1 -V 3 and V 1 + V 3 of the composite waveform are equal to or higher than the saturation voltage of the liquid crystal, -V 2 + V 3 is lower than the saturation voltage of the liquid crystal, -V 2 -V 3
Was set to be equal to or higher than the saturation value of the liquid crystal. No deterioration in memory was observed in the optical response characteristics when this composite waveform was applied to the liquid crystal electro-optical element, and gradation display was also possible by moving the position of the erasing pulse of the peak value V 1 ± V 3. It was
At the same time, the present invention can be applied to all the multi-blessing driving methods in which an erase pulse for aligning liquid crystals in one direction is applied within a selection period. In FIG. 7, it is a very simple method of moving the erase pulse of the drive waveform already applied for from the selection period to the non-selection period, but it is easy to maintain the memory property and display the gradation. (Example 1) In this example, the liquid crystal material is DOBAMBC.
(P-decyloxybenzyliden P'-amino-2-methylb
utyl cinnamata), liquid crystal layer thickness 1.0 μm, t
o = 200 μs, t 1 = 3 ms, t 3 = t 4 = t 6 = 1
00 μs, t 5 = 2.4 ms, t 7 = 500 μs, V 1
= 20V, V 2 = -23V, the contrast of 1:21 was the V 3 = 4V is obtained.
【００１２】（実施例２）本実施例では、液晶層の厚さ
０．５μｍ，ｔ0 ＝４００μｓ，ｔ1 ＝６ｍｓ，ｔ3 ＝
ｔ4 ＝ｔ6 ＝２００μｓ，ｔ5 ＝４．８ｍｓ，ｔ7 ＝１
ｍｓ，Ｖ1 ＝２５Ｖ，Ｖ2 ＝−１８Ｖ，Ｖ3 ＝２Ｖとし
たところ１：３５のコントラスト比が得られた。(Embodiment 2) In this embodiment, the thickness of the liquid crystal layer is 0.5 μm, t 0 = 400 μs, t 1 = 6 ms, t 3 =
t 4 = t 6 = 200 μs, t 5 = 4.8 ms, t 7 = 1
ms, the contrast ratio of V 1 = 25V, V 2 = -18V, was a V 3 = 2V 1:35 was obtained.
【００１３】[0013]
【発明の効果】本発明は、電極を有する一対の基板間に
強誘電性液晶を挟持してなる液晶素子を、線順次走査に
よりマルチプレッシング駆動をする方法において走査電
極には、液晶分子を一方向に揃えて消去するための飽和
値を越える大きさの電圧パルスを選択期間外に印加する
事を特微とする。この駆動方法は、メモリー性，コント
ラストの良好な液晶表示素子を提供するものである。同
時に消去パルスの位置を、フレーム周期内で自由に選択
できるので、高速応答プリンターヘッドの階調表示も容
易である。According to the present invention, a liquid crystal element having a ferroelectric liquid crystal sandwiched between a pair of substrates having electrodes is subjected to multiplexing driving by line-sequential scanning. It is characterized in that a voltage pulse having a magnitude exceeding a saturation value for erasing in the same direction is applied outside the selection period. This driving method provides a liquid crystal display device having a good memory property and a good contrast. At the same time, the position of the erase pulse can be freely selected within the frame period, so that the gradation display of the high-speed response printer head is easy.
【図１】（ａ），（ｂ）出願済みの液晶表示素子の駆動
波形図。FIG. 1A and FIG. 1B are drive waveform diagrams of a liquid crystal display element for which an application has been filed.
【図２】出願済みの液晶表示素子の駆動波形図。FIG. 2 is a drive waveform diagram of a liquid crystal display element that has been applied for.
【図３】液晶表示素子の印加波形図。FIG. 3 is an applied waveform diagram of a liquid crystal display element.
【図４】液晶表示素子の光応答特製図。FIG. 4 is a special drawing of light response of a liquid crystal display device.
【図５】液晶表示素子の印加波形図。FIG. 5 is an applied waveform diagram of a liquid crystal display element.
【図６】液晶表示素子の光応答特性図FIG. 6 is a photoresponse characteristic diagram of a liquid crystal display device.
【図７】本発明の駆動波形図。FIG. 7 is a drive waveform diagram of the present invention.
【手続補正書】[Procedure amendment]
【提出日】平成６年６月２１日[Submission date] June 21, 1994
【手続補正１】[Procedure Amendment 1]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】０００２[Name of item to be corrected] 0002
【補正方法】変更[Correction method] Change
【補正内容】[Correction content]
【０００２】[0002]
【従来の技術】従来、メモリー性を有する強誘電性液晶
素子のマルチプレッシング駆動方法としては、特願昭５
９−８５４８１号の「液晶素子の駆動方法」が提案され
ている。図１（ａ）（ｂ）に特願昭５９−８５４８１号
の駆動波形を示す。走査電極Ｖｔには、所定周期毎の選
択時間ｔ０内の最初のｔ１には、パルス幅ｔ１’波高値
−Ｖ０の消去パルスを印加し、残りのｔ２間には、周期
２ｔ４’パルス幅ｔ４’波高値＋２ Ｖ１で消去パルス
と逆符号の選択パルス列を印加する。一方、信号電極Ｖ
ｄは、周期２ｔ４’パルス幅ｔ４’波高値±Ｖ１の表示
パルス列を選択時間の最後ｔ３間だけ印加する。2. Description of the Related Art Conventionally, as a method for driving a ferroelectric liquid crystal device having a memory property, Japanese Patent Application No.
No. 9-85481 , “Driving Method of Liquid Crystal Element” is proposed. 1 (a) and 1 (b) show Japanese Patent Application No. 59-85481 .
The drive waveform of is shown. The scanning electrodes Vt, the first t 1 within the selected time t 0 for each predetermined period, and applying the erase pulse of the pulse width t 1 'peak value -V 0, Between remaining t 2, the period 2t A selection pulse train having the opposite sign to that of the erase pulse is applied with a 4 ′ pulse width t 4 ′ crest value +2 V 1 . On the other hand, the signal electrode V
In d, a display pulse train having a period 2t 4 ′ pulse width t 4 ′ crest value ± V 1 is applied only for the last t 3 of the selection time.
【手続補正２】[Procedure Amendment 2]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】０００３[Name of item to be corrected] 0003
【補正方法】変更[Correction method] Change
【補正内容】[Correction content]
【０００３】また、特許出願済みの駆動波形及び液晶に
印加される波形を図２に示す。走査電極Ｘ１には、選択
期間ｔ０内に液晶の飽和値を越えるＶ１及びＶ２の波高
値及び、極性の異なる電圧パルスをパルス幅ｔ ３，ｔ４
でそれぞれ印加し、非選択期間ｔ１内は零Ｖが印加され
る。一方信号電極Ｙ１には、選択期間ｔ０内の電圧パル
スＶ１，Ｖ２とそれぞれ同一極性で波高値がＶ３でパル
ス幅がｔ３以下の正負電圧パルスを、又光透過状態を別
の状態にする時は、選択期間ｔ０の時間零Ｖにされる。FIG. 2 shows the driving waveforms for which a patent has been applied and the waveforms applied to the liquid crystal. The pulse widths t 3 and t 4 are applied to the scan electrodes X 1 by the pulse widths of V 1 and V 2 that exceed the saturation value of the liquid crystal and voltage pulses having different polarities within the selection period t 0 .
, And 0 V is applied during the non-selection period t 1 . On the other hand, to the signal electrode Y 1 , positive and negative voltage pulses having the same polarity as the voltage pulses V 1 and V 2 in the selection period t 0 , the peak value V 3 and the pulse width t 3 or less, and the light transmission state are different. When the state is set to 0 , the time is set to 0V during the selection period t 0 .
【手続補正３】[Procedure 3]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】０００５[Name of item to be corrected] 0005
【補正方法】変更[Correction method] Change
【補正内容】[Correction content]
【０００５】[0005]
【発明が解決しようとする課題】上記従来の駆動方法に
おいてはいずれの場合も選択期間内に消去パルスを印加
している。しかし、最近の我々の数々の実験によれば、
図３（ａ）に示すような波形を液晶電気光学素子に印加
した場合その光透過特性は、図３（ｂ）に示すように、
メモリー性の低下現象が認められることが判明した。と
ころが、図４（ａ）に示すような波形を液晶電気光学素
子に印加した場合の図に示した光透過特性は、メモリー
性の低下現像が認められない。この現象の原因について
は現在検討中であるが、実際のマルチプレックス駆動に
おいては、メモリー性の低下が起こり好ましくない。こ
れは、図３（ａ）では、消去パルス印加直後に逆極性の
選択信号電圧を印加しているため、消去パルスにより走
査電極と信号電極間に印加された大電圧の電荷が、逆極
性の選択信号電圧により充分に解消しきれずに電極間に
残り、液晶のメモリー性を低下させているものと推測さ
れる。 In any of the above-mentioned conventional driving methods, the erase pulse is applied within the selection period. However, according to our recent experiments,
When a waveform as shown in FIG. 3A is applied to the liquid crystal electro-optical element, its light transmission characteristics are as shown in FIG.
It was revealed that a phenomenon of deterioration of memory property was observed. However, the light transmission characteristics shown a waveform as shown in the figure when applied to the liquid crystal electro-optical element FIG. 4 (a), reduced development of memory capability is not observed. The cause of this phenomenon is currently under study, but in actual multiplex driving, the memory property deteriorates, which is not preferable. This
This is because, in FIG.
Since the selection signal voltage is applied, it is driven by the erase pulse.
The large voltage charge applied between the test electrode and the signal electrode
Selection signal voltage of the sex
It is speculated that the rest is deteriorating the memory property of the liquid crystal.
Be done.
【手続補正４】[Procedure amendment 4]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】０００６[Correction target item name] 0006
【補正方法】変更[Correction method] Change
【補正内容】[Correction content]
【０００６】本発明は、消去パルスを選択期間外に印加
し、その後所定期間経過後に選択期間とすることで上記
問題点を解決し、良好なコントラストを長時間にわたっ
て維持できるメモリー性液晶電気光学素子を提供するこ
とを目的とする。The present invention applies the erase pulse outside the selection period.
It is an object of the present invention to provide a memory type liquid crystal electro-optical element which can solve the above-mentioned problems by setting a selection period after a lapse of a predetermined period and maintain good contrast for a long time.
【手続補正５】[Procedure Amendment 5]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】０００９[Correction target item name] 0009
【補正方法】変更[Correction method] Change
【補正内容】[Correction content]
【０００９】本発明の実施例としての強誘電性スメクチ
ック液晶のマルチプレッシング駆動波形を図５に示す。
液晶素子は一対の基板に形成された走査電極群Ｘと信号
電極群Ｙからなる対向透明電極間に、メモリー性を有す
る液晶を封入して構成される。周知のように、一対の対
向電極の交差部に画素が形成される。 FIG. 5 shows a multiplexing driving waveform of the ferroelectric smectic liquid crystal as an embodiment of the present invention.
The liquid crystal element is configured by enclosing a liquid crystal having a memory property between opposing transparent electrodes formed of a scanning electrode group X and a signal electrode group Y formed on a pair of substrates. As is well known, pixels are formed at the intersections of a pair of counter electrodes.
【手続補正６】[Procedure correction 6]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】００１１[Correction target item name] 0011
【補正方法】変更[Correction method] Change
【補正内容】[Correction content]
【００１１】波高値の設定は次のように行った。合成波
形のＶ１−Ｖ３，Ｖ１＋Ｖ３の値は液晶の飽和電圧以
上、−Ｖ２＋Ｖ３は液晶の飽和電圧未満、−Ｖ２−Ｖ３
は液晶の飽和値以上となるように設定した。本合成波形
を液晶電気光学素子に印加したときの光応答特性にはメ
モリーの低下も認められず、波高値Ｖ１±Ｖ３の消去パ
ルスの位置を移動させる事で階調表示も可能となった。
同時に本発明は、選択期間内に液晶を一方向に揃えるた
めの消去パルスを印加するマルチプレッシング駆動方法
すべてに応用できる。図５においては、すでに出願済の
駆動波形の消去パルスを選択期間内から非選択期間内へ
移動させるという非常に簡便な方法であるが、メモリー
性の維持、及び階調表示が容易である。すなわち、消去
パルス印加後に時間を置いてから選択期間を設けたの
で、消去パルスにより走査電極と信号電極間の液晶に印
加された電圧の電荷が、印加後の所定期間である程度解
消され、その上で選択期間によりメモリー性を与えてい
るので、非選択期間に電極間に残った電荷が少なくな
り、メモリー性が低下現象を引き起こすことはない。 （実施例１）本実施例では、液晶材料にＤＯＢＡＭＢＣ
（Ｐ−ｄｅｃｙｌｏｘｙｂｅｎｚｙｌｉｄｅｎ Ｐ’−
ａｍｉｎｏ−２−ｍｅｔｈｙｌｂｕｔｙｌ ｃｉｎｎａ
ｍａｔａ）を使用し、液晶層厚１．０μｍ，ｔ０＝２０
０μｓ，ｔ１＝３ｍｓ，ｔ３＝ｔ４＝ｔ６＝１００μ
ｓ，ｔ５＝２．４ｍｓ，ｔ７＝５００μｓ，Ｖ１＝２０
Ｖ，Ｖ２＝−２３Ｖ，Ｖ３＝４Ｖとしたところ１：２１
のコントラストが得られた。The crest value was set as follows. The values of V 1 -V 3 and V 1 + V 3 of the composite waveform are equal to or higher than the saturation voltage of the liquid crystal, -V 2 + V 3 is lower than the saturation voltage of the liquid crystal, -V 2 -V 3
Was set to be equal to or higher than the saturation value of the liquid crystal. No deterioration in memory was observed in the optical response characteristics when this composite waveform was applied to the liquid crystal electro-optical element, and gradation display was also possible by moving the position of the erasing pulse with the peak value V 1 ± V 3. It was
At the same time, the present invention can be applied to all the multiplex driving methods in which the erase pulse for aligning the liquid crystal in one direction is applied within the selection period. In FIG. 5 , it is a very simple method of moving the erase pulse of the drive waveform already applied for from the selection period to the non-selection period, but it is easy to maintain the memory property and display the gradation. That is, erase
After the pulse was applied, there was a time interval before the selection period
To mark the liquid crystal between the scan electrode and the signal electrode with an erase pulse.
The applied voltage charge has some degree of solution within a predetermined period after application.
It is erased, and then memory is given for a selected period.
Therefore, the charge remaining between the electrodes during the non-selection period is reduced.
Therefore, the memory property does not deteriorate. (Example 1) In this example, the liquid crystal material is DOBAMBC.
(P-decyloxybenzyliden P'-
amino-2-methylbutyl cinna
liquid crystal layer thickness 1.0 μm, t 0 = 20
0 μs, t 1 = 3 ms, t 3 = t 4 = t 6 = 100 μ
s, t 5 = 2.4 ms, t 7 = 500 μs, V 1 = 20
When V, V 2 = -23V and V 3 = 4V are set, 1:21
The contrast was obtained.
【手続補正７】[Procedure Amendment 7]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】００１３[Correction target item name] 0013
【補正方法】変更[Correction method] Change
【補正内容】[Correction content]
【００１３】[0013]
【発明の効果】本発明は、メモリー性を有する液晶の画
素に有する液晶表示素子を線順次走査方式で駆動する方
法において、画素の液晶分子を一方向に揃えて前の表示
を消去するための電圧パルスを非選択期間に印加するこ
とにより、選択期間に選択した走査電極に対応する画素
の液晶のメモリー状態を、他の走査電極の選択期間中に
消去できるので、フレーム周期を長くすることもなく、
各画素の液晶のコントラスト比をほぼ均一にして、かつ
向上させ、表示画面のちらつきも低減される。また、液
晶分子を一方向に揃える電圧パルスを印加した後、所定
期間経過後に選択期間を設けたので、非選択期間にメモ
リー性の低下現象を引き起こすこともない。この駆動方
法は、メモリー性，コントラストの良好な液晶表示素子
を提供するものである。同時に消去パルスの位置を、フ
レーム周期内で自由に選択できるので、高速応答プリン
ターヘッドの階調表示も容易である。 INDUSTRIAL APPLICABILITY The present invention is a liquid crystal display having a memory property.
A method of driving a liquid crystal display element included in a pixel by a line-sequential scanning method
Method, the liquid crystal molecules of the pixels are aligned in one direction
Application of a voltage pulse to erase the
The pixel corresponding to the scan electrode selected during the selection period
The liquid crystal memory state of the
Since it can be erased, without increasing the frame period,
Make the liquid crystal contrast ratio of each pixel almost uniform, and
It also improves and reduces flickering on the display screen. Also, the liquid
After applying a voltage pulse that aligns the crystal molecules in one direction,
Since the selection period was set after the lapse of the period, make a note during the non-selection period.
It does not cause the phenomenon of deterioration of the leak property. This driving method
Method is a liquid crystal display device with good memory and contrast
Is provided. At the same time, change the position of the erase pulse to
Since it is possible to select freely within the frame period, a fast response print
It is easy to display the gradation of the target head.
【手続補正８】[Procedure Amendment 8]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】図面の簡単な説明[Name of item to be corrected] Brief description of the drawing
【補正方法】変更[Correction method] Change
【補正内容】[Correction content]
【図面の簡単な説明】[Brief description of drawings]
【図１】（ａ）、（ｂ）出願済みの液晶表示素子の駆動
波形図。FIG. 1A and FIG. 1B are drive waveform diagrams of a liquid crystal display element for which an application has been filed.
【図２】出願済みの液晶表示素子の駆動波形系図。FIG. 2 is a drive waveform system diagram of an applied liquid crystal display element.
【図３】液晶表示素子の印加波形図、及び液晶表示素子
の光応答特性図。 FIG. 3 is an applied waveform diagram of a liquid crystal display element and a liquid crystal display element
The optical response characteristic diagram of
【図４】液晶表示素子の印加波形図、及び液晶表示素子
の光応答特性図。 FIG. 4 is an applied waveform diagram of a liquid crystal display element and a liquid crystal display element.
The optical response characteristic diagram of
【図５】本発明の駆動波形図。 FIG. 5 is a drive waveform diagram of the present invention.
【手続補正９】[Procedure Amendment 9]
【補正対象書類名】図面[Document name to be corrected] Drawing
【補正対象項目名】図３[Name of item to be corrected] Figure 3
【補正方法】変更[Correction method] Change
【補正内容】[Correction content]
【図３】 [Figure 3]
【手続補正１０】[Procedure Amendment 10]
【補正対象書類名】図面[Document name to be corrected] Drawing
【補正対象項目名】図４[Name of item to be corrected] Fig. 4
【補正方法】変更[Correction method] Change
【補正内容】[Correction content]
【図４】 [Figure 4]
【手続補正１１】[Procedure Amendment 11]
【補正対象書類名】図面[Document name to be corrected] Drawing
【補正対象項目名】図５[Name of item to be corrected] Figure 5
【補正方法】変更[Correction method] Change
【補正内容】[Correction content]
【図５】 [Figure 5]
【手続補正１２】[Procedure Amendment 12]
【補正対象書類名】図面[Document name to be corrected] Drawing
【補正対象項目名】図６[Name of item to be corrected] Figure 6
【補正方法】削除[Correction method] Delete
【手続補正１３】[Procedure Amendment 13]
【補正対象書類名】図面[Document name to be corrected] Drawing
【補正対象項目名】図７[Name of item to be corrected] Figure 7
【補正方法】削除[Correction method] Delete
Claims (1)
極群と信号電極群を有し、該走査電極群と信号電極群の
間にメモリー性を有する液晶を配置してなる液晶素子を
線順次走査方式により駆動してなる液晶素子の駆動方法
であって、 前記各走査電極に電圧を印加する周期中に、当該走査電
極を選択して表示信号に応じた電圧を印加する選択期間
と、当該走査電極を選択せずに他の走査電極を選択する
非選択期間とを有し、 前記各走査電極の非選択期間中に、当該走査電極に対応
する画素の液晶分子を一方向に揃えるためのパルスを印
加する期間を設け、この後所定期間後に前記選択期間と
なるようにしたことを特徴とする液晶素子の駆動方法。1. A liquid crystal element comprising a scanning electrode group and a signal electrode group forming a pixel at each intersection, and a liquid crystal having a memory property being arranged between the scanning electrode group and the signal electrode group. A method of driving a liquid crystal element driven by a sequential scanning method, wherein during a period of applying a voltage to each of the scan electrodes, a selection period of selecting the scan electrode and applying a voltage according to a display signal, A non-selection period for selecting another scan electrode without selecting the scan electrode, and aligning liquid crystal molecules of pixels corresponding to the scan electrode in one direction during the non-selection period of each scan electrode. The method for driving a liquid crystal element is characterized in that a period for applying the pulse is provided, and then the selection period comes after a predetermined period.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10869594A JPH07140443A (en) | 1994-05-23 | 1994-05-23 | Method for driving liquid crystal element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10869594A JPH07140443A (en) | 1994-05-23 | 1994-05-23 | Method for driving liquid crystal element |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60149803A Division JPH0750268B2 (en) | 1985-07-08 | 1985-07-08 | Liquid crystal element driving method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH07140443A true JPH07140443A (en) | 1995-06-02 |
Family
ID=14491304
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10869594A Pending JPH07140443A (en) | 1994-05-23 | 1994-05-23 | Method for driving liquid crystal element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH07140443A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2007080655A1 (en) | 2006-01-16 | 2007-07-19 | Fujitsu Limited | Display element drive method, display element, and electronic terminal |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS629324A (en) * | 1985-07-08 | 1987-01-17 | Seiko Epson Corp | Driving method for liquid crystal element |
-
1994
- 1994-05-23 JP JP10869594A patent/JPH07140443A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS629324A (en) * | 1985-07-08 | 1987-01-17 | Seiko Epson Corp | Driving method for liquid crystal element |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2007080655A1 (en) | 2006-01-16 | 2007-07-19 | Fujitsu Limited | Display element drive method, display element, and electronic terminal |
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