JPH07115283A - Multilayer sealed board containing inner layer circuit and inner layer circuit board - Google Patents
Multilayer sealed board containing inner layer circuit and inner layer circuit boardInfo
- Publication number
- JPH07115283A JPH07115283A JP26049793A JP26049793A JPH07115283A JP H07115283 A JPH07115283 A JP H07115283A JP 26049793 A JP26049793 A JP 26049793A JP 26049793 A JP26049793 A JP 26049793A JP H07115283 A JPH07115283 A JP H07115283A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- circuit
- inner layer
- layer circuit
- circuits
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
- Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、製造工程を簡略化する
ことができる内層回路入り多層シールド板およびそのた
めの内層用回路板に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer shield plate containing an inner layer circuit and a circuit board for an inner layer therefor, which can simplify the manufacturing process.
【０００２】[0002]
【従来の技術】従来の内層回路入り多層シールド板は、
内層用回路が使用機種毎に異なるため、特定機種にしか
対応できず、少量多品種生産をしなければならない。ま
た、その製造工程は、内層用回路板を製造するための金
属箔張り積層板の積層プレス成形を行ない、内層用回路
板の回路加工・表面処理を行なった後、二次積層プレス
成形し、後加工を行なうという長い工程であるため、中
間製品、副資材（内層用回路形成用フィルムなど）の管
理、また最終製品の在庫、納期管理が非常に煩雑であ
る。2. Description of the Related Art A conventional multilayer shield plate containing an inner layer circuit is
Since the circuit for the inner layer differs depending on the model used, only the specific model can be supported, and it is necessary to produce a large quantity in small quantities. In addition, in the manufacturing process, the metal foil-clad laminate for manufacturing the circuit board for the inner layer is laminated and press-molded, and after the circuit processing and the surface treatment of the circuit board for the inner layer is performed, the secondary laminated press-molding is performed, Since it is a long process of post-processing, it is very complicated to manage intermediate products and sub-materials (circuit forming film for inner layers, etc.), and final product inventory and delivery.
【０００３】[0003]
【発明が解決しようとする課題】本発明が解決しようと
する課題は、製造工程を簡略化することができる内層回
路入り多層シールド板およびそのための内層用回路板を
提供することである。SUMMARY OF THE INVENTION An object of the present invention is to provide a multilayer shield plate containing an inner layer circuit and a circuit board for an inner layer therefor, which can simplify the manufacturing process.
【０００４】[0004]
【課題を解決するための手段】上記課題を解決するため
に、本発明に係る内層回路入り多層シールド板は、内層
用回路（第２層回路１，第３層回路２）が格子状で、透
視して平面的に見たとき、第２層回路１と第３層回路２
とが縦方向同士、横方向同士でそれぞれ実質的に重なる
ことがなく、同様に平面的に見たとき、第２層および第
３層に回路を有しない部分と、第２層のみに回路を有す
る部分と、第３層のみに回路を有する部分と、第２層お
よび第３層に回路を有する部分とを備えたことを特徴と
する。第１層と第４層は表面であり、金属箔（銅箔）４
で覆われている。また、本発明に係る内層用回路板は、
絶縁層３の両面に格子状の回路を有し、両面の回路を平
面的に見たとき、絶縁層３を介して存在する回路が縦方
向同士、横方向同士でそれぞれ実質的に重なることがな
く、同様に両面の回路を平面的に見たとき、両面とも回
路を有しない部分と、第１の面のみに回路を有する部分
と、第２の面のみに回路を有する部分と、両面に回路を
有する部分とを備えたことを特徴とする。In order to solve the above-mentioned problems, in the multilayer shield plate with an inner layer circuit according to the present invention, the inner layer circuits (second layer circuit 1, third layer circuit 2) have a grid shape, When seen through in a plan view, the second layer circuit 1 and the third layer circuit 2
Does not substantially overlap each other in the vertical direction and in the horizontal direction, and when viewed in a plan view in the same manner, a portion having no circuit in the second and third layers and a circuit in the second layer only. It is characterized in that it has a portion having, a portion having a circuit only in the third layer, and a portion having a circuit in the second layer and the third layer. The first layer and the fourth layer are the surface, and the metal foil (copper foil) 4
Is covered with. Further, the inner layer circuit board according to the present invention,
The insulating layer 3 has lattice-shaped circuits on both sides, and when the circuits on both sides are viewed in plan, the circuits existing via the insulating layer 3 may substantially overlap each other in the vertical direction and in the horizontal direction. Similarly, when the circuits on both sides are viewed in a plan view, a portion having no circuit on both sides, a portion having a circuit only on the first surface, a portion having a circuit only on the second surface, and And a portion having a circuit.
【０００５】[0005]
【作用】内層回路入り多層シールド板は、一般に、 ａ）第１層と第４層 ｂ）第１層または第４層と第２層 ｃ）第１層または第４層と第３層 が、それぞれスルーホールにより接続される。そこで、
上記のような構成としたことにより、 ａ）第１層と第４層とを接続する場合は第２，第３層に
回路を有しない部分を、 ｂ）第１層または第４層と第２層とを接続する場合は第
２層のみに回路を有する部分を、 ｃ）第１層または第４層と第３層とを接続する場合は第
３層のみに回路を有する部分を、 それぞれ使用できるように、第１層と第４層の回路設計
を行なうことにより、内層用回路板を共通化することが
できる。上記のように内層用回路板を共通化することに
より、中間製品、副資材（内層回路形成用のフィルムな
ど）の管理、また最終製品の在庫、納期管理を簡略化す
ることができる。格子状回路の形状、幅、間隔は特に限
定するものではない。In general, a multilayer shield plate with an inner layer circuit comprises: a) a first layer and a fourth layer b) a first layer or a fourth layer and a second layer c) a first layer or a fourth layer and a third layer, Each is connected by a through hole. Therefore,
With the above-described structure, a) when connecting the first layer and the fourth layer, a portion having no circuit in the second and third layers, b) the first layer or the fourth layer When connecting two layers, a portion having a circuit only on the second layer, c) When connecting the first layer or the fourth layer and the third layer, a portion having a circuit only on the third layer, respectively. By designing the circuits of the first layer and the fourth layer so that they can be used, the inner-layer circuit board can be made common. By sharing the inner layer circuit board as described above, it is possible to simplify management of intermediate products and auxiliary materials (films for forming inner layer circuits), and inventory and delivery date management of final products. The shape, width, and spacing of the grid-shaped circuit are not particularly limited.
【０００６】[0006]
実施例１ ＦＲ−４両面銅張り積層板（板厚：０．４mm，銅箔厚
み：３５μｍ）を使用し、両面の銅箔をエッチング加工
して平面的に透視した状態が図１に示すような内層用回
路板を用意した。これは、４層の回路板において、第２
層回路１と第３層回路２を構成するものであり、回路が
それぞれ格子状で、透視して平面的に見たとき、第２層
回路１と第３層回路２とが縦方向同士、横方向同士でそ
れぞれ実質的に重なることがなく、同様に平面的に見た
とき、第２層および第３層に回路を有しない部分と、第
２層のみに回路を有する部分と、第３層のみに回路を有
する部分と、第２層および第３層に回路を有する部分と
を備えている。上記内層用回路板の両表面に接着プリプ
レグ５（ＦＲ−４材，厚み：０．１mm）を各２枚重ね、
最表面には銅箔４（厚み：１８μｍ）を配置した後、圧
力２０kgｆ/cm2、温度１７０℃で９０分間加熱加圧し、
厚み０．８mmの内層回路入り多層シールド板を得た。Example 1 Using a FR-4 double-sided copper-clad laminate (plate thickness: 0.4 mm, copper foil thickness: 35 μm), the copper foil on both sides was subjected to an etching process and seen in a plan view as shown in FIG. 1. An inner layer circuit board was prepared. This is the second in a four-layer circuit board.
The layer circuit 1 and the third layer circuit 2 are formed, and when the circuits are respectively in a grid shape and are seen through in a plan view, the second layer circuit 1 and the third layer circuit 2 are arranged in the vertical direction, Similarly, when viewed two-dimensionally, they do not substantially overlap each other in the lateral direction, a portion having no circuit in the second layer and the third layer, a portion having a circuit only in the second layer, and a third portion. A portion having a circuit only in the layer and a portion having a circuit in the second layer and the third layer are provided. Two adhesive prepregs 5 (FR-4 material, thickness: 0.1 mm) are laminated on each of both surfaces of the inner layer circuit board,
After arranging the copper foil 4 (thickness: 18 μm) on the outermost surface, heat and pressure for 90 minutes at a pressure of 20 kgf / cm 2 and a temperature of 170 ° C.,
A multilayer shield plate with an inner layer circuit having a thickness of 0.8 mm was obtained.
【０００７】実施例２ 絶縁層３となるプリプレグ（ＦＲ−４材，厚み：０．２
mm）を４枚を重ね、その両表面に打ち抜き加工により格
子状回路とした両面粗化銅箔（厚み：３５μｍ）からな
る第２層回路１および第３層回路２を図２に示すように
配置した後、さらにその両側に接着プリプレグ５（ＦＲ
−４材，厚み：０．１mm）を各２枚、最表面には銅箔４
（厚み：１８μｍ）を各１枚を配置した後、圧力２０kg
ｆ/cm2、温度１７０℃で９０分間加熱加圧し、厚み０．
８mmの内層回路入り多層シールド板を得た。Example 2 Prepreg (FR-4 material, thickness: 0.2) to be the insulating layer 3
mm) four layers, and the second layer circuit 1 and the third layer circuit 2 made of double-sided roughened copper foil (thickness: 35 μm) are formed into a lattice-shaped circuit on both surfaces by punching as shown in FIG. After arranging, the adhesive prepreg 5 (FR
-4 materials, thickness: 0.1 mm) 2 each, copper foil 4 on the outermost surface
After arranging 1 each (thickness: 18μm), pressure 20kg
f / cm 2 at 170 ° C. for 90 minutes under heat and pressure to a thickness of 0.
A multilayer shield plate with an inner layer circuit of 8 mm was obtained.
【０００８】従来例 ＦＲ−４両面銅張り積層板（板厚：０．４mm，銅箔厚
み：３５μｍ）を使用し、両面の銅箔を目的とする所定
の回路模様にエッチング加工して、専用の内層用回路板
とした。以下、実施例１と同様にして、厚み０．８mmの
内層回路入り多層シールド板を得た。Conventional example FR-4 Double-sided copper-clad laminate (board thickness: 0.4 mm, copper foil thickness: 35 μm) is used, and the copper foil on both sides is etched into a desired circuit pattern for exclusive use. It was used as the inner layer circuit board. Thereafter, in the same manner as in Example 1, a multilayer shield plate having an inner layer circuit and having a thickness of 0.8 mm was obtained.
【０００９】これら内層回路入り多層シールド板製造時
の主な工程毎の工数比較を行なった結果を表１に示す。Table 1 shows the results of comparison of man-hours for each main step in manufacturing these multilayer shield plates with inner layer circuits.
【００１０】[0010]
【表１】 [Table 1]
【００１１】[0011]
【発明の効果】上述のように、本発明によれば、内層用
回路を共通化することができるので、内層回路入り多層
シールド板の製造工程を簡略化することができる。As described above, according to the present invention, since the circuit for the inner layer can be made common, the manufacturing process of the multilayer shield plate containing the inner layer circuit can be simplified.
【図１】本発明に係る内層回路入り多層シールド板の実
施例において内層回路を透視した平面図である。FIG. 1 is a plan view in which an inner layer circuit is seen through in an embodiment of a multilayer shield plate containing an inner layer circuit according to the present invention.
【図２】本発明に係る内層回路入り多層シールド板の実
施例において層構成を示す説明図である。FIG. 2 is an explanatory diagram showing a layer structure in an example of a multilayer shield plate with an inner layer circuit according to the present invention.
１は第２層回路 ２は第３層回路 ３は絶縁層 ４は金属箔（銅箔） ５は接着プリプレグ 1 is a second layer circuit 2 is a third layer circuit 3 is an insulating layer 4 is a metal foil (copper foil) 5 is an adhesive prepreg
Claims (2)
方向同士、横方向同士でそれぞれ実質的に重なることが
なく、 同様に平面的に見たとき、第２層および第３層に回路を
有しない部分と、第２層のみに回路を有する部分と、第
３層のみに回路を有する部分と、第２層および第３層に
回路を有する部分とを備えたことを特徴とする内層回路
入り多層シールド板。1. The inner layer circuits (second layer, third layer) are in a lattice shape, and when viewed in a plan view, the circuits of the second layer and the third layer are arranged in the vertical direction and in the horizontal direction, respectively. Similarly, when viewed two-dimensionally, they do not substantially overlap with each other, and when viewed in a plane, a portion having no circuit on the second and third layers, a portion having a circuit only on the second layer, and a circuit only on the third layer. An inner layer circuit-containing multi-layer shield plate, comprising: a portion having and a portion having a circuit in the second and third layers.
方向同士でそれぞれ実質的に重なることがなく、 両面の回路を平面的に見たとき、両面とも回路を有しな
い部分と、第１の面のみに回路を有する部分と、第２の
面のみに回路を有する部分と、両面に回路を有する部分
とを備えたことを特徴とする内層用回路板。2. A grid-shaped circuit is provided on both sides of an insulating layer, and when the circuits on both sides are viewed in plan, the circuits do not substantially overlap each other in the vertical direction and in the horizontal direction. When the circuit is viewed two-dimensionally, a portion having no circuit on both sides, a portion having a circuit only on the first surface, a portion having a circuit only on the second surface, and a portion having a circuit on both sides are provided. An inner layer circuit board characterized by being provided.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26049793A JPH07115283A (en) | 1993-10-19 | 1993-10-19 | Multilayer sealed board containing inner layer circuit and inner layer circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26049793A JPH07115283A (en) | 1993-10-19 | 1993-10-19 | Multilayer sealed board containing inner layer circuit and inner layer circuit board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH07115283A true JPH07115283A (en) | 1995-05-02 |
Family
ID=17348794
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP26049793A Pending JPH07115283A (en) | 1993-10-19 | 1993-10-19 | Multilayer sealed board containing inner layer circuit and inner layer circuit board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH07115283A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7514779B2 (en) | 1998-09-17 | 2009-04-07 | Ibiden Co., Ltd. | Multilayer build-up wiring board |
-
1993
- 1993-10-19 JP JP26049793A patent/JPH07115283A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7514779B2 (en) | 1998-09-17 | 2009-04-07 | Ibiden Co., Ltd. | Multilayer build-up wiring board |
| US7847318B2 (en) | 1998-09-17 | 2010-12-07 | Ibiden Co., Ltd. | Multilayer build-up wiring board including a chip mount region |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPH07115283A (en) | Multilayer sealed board containing inner layer circuit and inner layer circuit board | |
| WO2019026835A1 (en) | Method for manufacturing multilayer printed wiring board and multilayer printed wiring board | |
| JP7124128B2 (en) | Printed circuit board manufacturing method and printed circuit board | |
| CN110650597B (en) | Circuit board, manufacturing method thereof and electronic equipment | |
| JP3882739B2 (en) | Manufacturing method of metal foil clad laminate with inner layer circuit | |
| JP6361906B2 (en) | Wiring substrate manufacturing method and laminate with support material | |
| JP2001036237A (en) | Manufacture of multilayered printed board | |
| JP2000216543A (en) | Manufacture of multilayered printed wiring board | |
| JP2858978B2 (en) | Method for manufacturing multilayer wiring board | |
| JPH05121876A (en) | Manufacture of multilayer printed wiring board | |
| JPH10313152A (en) | Circuit board | |
| JPH07117174A (en) | Metal-foiled laminated plate and manufacture thereof | |
| JP2903893B2 (en) | Method for producing copper-clad laminate for multilayer printed wiring board | |
| JPH11186722A (en) | Manufacture of metal-core multilayer shield board | |
| JPH0417385A (en) | Manufacture of compound circuit board | |
| JP3610591B2 (en) | Manufacturing method of multilayer printed wiring board | |
| JPS62252189A (en) | Copper clad laminated board | |
| JPH0564098B2 (en) | ||
| JP3922148B2 (en) | Manufacturing method of multilayer printed wiring board | |
| JPH01248685A (en) | Manufacture of single-sided metallic-foil-clad laminated board and manufacture of single-sided printed circuit board | |
| JPH04268797A (en) | Manufacture of laminated board | |
| JPH04268798A (en) | Manufacture of multilayer copper plated laminated board | |
| JP2000196238A (en) | Manufacture of multilayer metal foil laminate board with inner circuit | |
| JPH01264813A (en) | Manufacture of laminate | |
| JPH04278599A (en) | Manufacture of multilayer printed circuit board |