JP2903893B2 - Method for producing copper-clad laminate for multilayer printed wiring board - Google Patents
Method for producing copper-clad laminate for multilayer printed wiring boardInfo
- Publication number
- JP2903893B2 JP2903893B2 JP4246940A JP24694092A JP2903893B2 JP 2903893 B2 JP2903893 B2 JP 2903893B2 JP 4246940 A JP4246940 A JP 4246940A JP 24694092 A JP24694092 A JP 24694092A JP 2903893 B2 JP2903893 B2 JP 2903893B2
- Authority
- JP
- Japan
- Prior art keywords
- printed wiring
- clad laminate
- multilayer printed
- wiring board
- copper
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Landscapes
- Laminated Bodies (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Description
【０００１】[0001]
【産業上の利用分野】本発明は、寸法精度に優れた多層
印刷配線板用銅張積層板の製造方法に関するものであ
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for producing a copper-clad laminate for a multilayer printed wiring board having excellent dimensional accuracy.
【０００２】[0002]
【従来の技術】多層印刷配線板用銅張積層板は、内層回
路板にガラス基材プリプレグを介して銅はくを重ねるか
又は内層回路板にガラス布基材片面銅張積層板を銅はく
が外側となるよう重ね、加熱加圧して製造される。内層
回路板の回路パターンには、多層化接着後の寸法精度を
向上させるため、縦方向及び横方向の寸法補正を加えて
いる。2. Description of the Related Art A copper-clad laminate for a multilayer printed wiring board is formed by laminating a copper foil on an inner circuit board via a glass base material prepreg or a copper-clad laminate of a glass cloth base on the inner circuit board. It is manufactured by stacking the spiders on the outside and heating and pressing. In order to improve the dimensional accuracy after the multi-layer bonding, the dimensional correction in the vertical and horizontal directions is added to the circuit pattern of the inner circuit board.
【０００３】[0003]
【発明が解決しようとする課題】しかしながら、このよ
うな補正を加えてもなお寸法精度は満足できるものでは
なかった。本発明は、寸法精度を更に向上させるため、
内層回路の寸法補正方法を提供することを目的とするも
のである。However, even with such correction, the dimensional accuracy has not been satisfactory. The present invention, in order to further improve the dimensional accuracy,
It is an object of the present invention to provide a method for correcting a size of an inner layer circuit.
【０００４】[0004]
【課題を解決するための手段】本発明者らは、多層化接
着工程での内層回路板の挙動について種々検討した結
果、加熱加圧による多層化接着するときに、内層回路板
が、図１に示すＡ及びＢ方向（縦及び横方向）だけでな
く、Ｃ方向（斜め方向）にも収縮することを見出し、本
発明を完成した。The present inventors have conducted various studies on the behavior of the inner layer circuit board in the multi-layer bonding step. The present invention was found to shrink not only in the A and B directions (vertical and horizontal directions), but also in the C direction (oblique direction).
【０００５】本発明は、多層化接着工程における寸法変
化を加味して、縦、横及び斜め方向に寸法を補正した回
路パターンを有する内層回路板の所定枚数及び外層材を
接着用プリプレグを介して加熱加圧して一体にすること
を特徴とする多層印刷配線板用銅張積層板の製造方法で
ある。寸法の補正値は、基準値を１とすると、縦方向
（図１のＡ方向）を１．０００００〜１．０００５０、
横方向（図１のＢ方向）を０．９９９８０〜１．０００
３０、斜め方向（図１のＣ方向）を１．０００１０〜
１．０００５０とするのが適当である。According to the present invention, a predetermined number of inner-layer circuit boards having a circuit pattern whose dimensions are corrected in the vertical, horizontal and oblique directions and an outer layer material are bonded via a bonding prepreg in consideration of a dimensional change in a multilayer bonding step. A method for producing a copper-clad laminate for a multilayer printed wiring board, wherein the copper-clad laminate is integrated by heating and pressing. Assuming that the reference value is 1, the dimension correction value is 1.00000 to 1.00050 in the vertical direction (A direction in FIG. 1),
The horizontal direction (B direction in FIG. 1) is 0.99980 to 1.000.
30, the diagonal direction (direction C in FIG. 1) is 1.00010-
1.00050 is appropriate.
【０００６】[0006]
【作用】回路パターンに縦方向（図１のＡ方向）及び横
方向（図１のＢ方向）の寸法補正に加えて、斜め（図１
のＣ方向）にも補正をしておくことで精度よく多層化接
着時の寸法変化を相殺することができる。In addition to the vertical (A direction in FIG. 1) and lateral (B direction in FIG. 1) dimensional correction, the circuit pattern is oblique (FIG.
(C direction), it is possible to accurately cancel the dimensional change during the multi-layer bonding.
【０００７】[0007]
【実施例】両面にパターン周辺部の導体残存部６及び内
層回路パターン領域２を形成した厚み０．８ｍｍの内層
回路板（銅張積層板）１を用意した。この内層回路板１
の両側に、厚み０．１ｍｍのガラス布基材プリプレグ３
枚をプリプレグの縦方向がＡ方向になるようにして重
ね、その外側に厚み３５μｍの銅はくを重ね、１８０
℃、９０分間、４ＭＰａで加熱加圧して多層印刷配線板
用銅張積層板を得た。内層回路パターン領域２は、パタ
ーン形成の導体残存部４及びパターン形成の導体除去部
３からなっており、パターン形成の導体残存部４の周辺
の導体を除去し、パターン周辺部の導体除去部５とし
た。なお、内層回路パターンのＡ方向に１．０００３０
を乗じた補正、Ｂ方向に１．０００１０を乗じた補正、
Ｃ方向に１．０００３０を乗じた補正をした。EXAMPLE An inner layer circuit board (copper-clad laminate) 1 having a thickness of 0.8 mm and having a conductor remaining portion 6 at the periphery of the pattern and an inner layer circuit pattern region 2 formed on both surfaces was prepared. This inner circuit board 1
On both sides of the glass cloth substrate prepreg 0.1 mm thick 3
The prepregs are stacked such that the longitudinal direction of the prepreg is in the direction A, and a copper foil having a thickness of 35 μm is stacked on the outside of the prepreg.
It heated and pressurized at 4 degreeC and 90 degreeC for 90 minutes, and obtained the copper-clad laminated board for multilayer printed wiring boards. The inner-layer circuit pattern region 2 is composed of a conductor remaining portion 4 for forming a pattern and a conductor removing portion 3 for forming a pattern. And In addition, 1.00030 in the A direction of the inner layer circuit pattern.
Correction, multiplication by 1.00010 in the B direction,
Correction was performed by multiplying 1.00030 in the C direction.
【０００８】比較例１ Ａ方向及びＢ方向に補正し、Ｃ方向に補正しないように
した他は、実施例と同様にして多層印刷配線板用銅張積
層板を得た。Comparative Example 1 A copper-clad laminate for a multilayer printed wiring board was obtained in the same manner as in the example, except that the correction was made in the directions A and B but not in the direction C.
【０００９】比較例２ 寸法補正を全くせず、他は実施例と同様にして多層印刷
配線板用銅張積層板を得た。Comparative Example 2 A copper-clad laminate for a multilayer printed wiring board was obtained in the same manner as in the example except that no dimensional correction was performed.
【００１０】実施例、比較例１及び比較例２で得た多層
印刷配線板用銅張積層板について、パターン内位置精度
（設計値からのずれ量として測定）を調べた。その結果
を表１に示す。With respect to the copper-clad laminates for multilayer printed wiring boards obtained in Examples, Comparative Examples 1 and 2, positional accuracy in a pattern (measured as a deviation from a design value) was examined. Table 1 shows the results.
【００１１】[0011]
【表１】 [Table 1]
【００１２】[0012]
【発明の効果】本発明によれば、加熱加圧による多層化
接着時の縦、横、斜め方向の寸法変化を加味して内層回
路を形成することによって寸法精度のよい多層印刷配線
板用銅張積層板を得ることができる。According to the present invention, a copper for a multilayer printed wiring board having high dimensional accuracy can be obtained by forming an inner layer circuit in consideration of dimensional changes in the vertical, horizontal, and oblique directions at the time of multilayer bonding by heating and pressing. A laminated board can be obtained.
【図１】本発明の実施例に係る内層回路板の平面図であ
る。FIG. 1 is a plan view of an inner circuit board according to an embodiment of the present invention.
１：内層回路板 ２：内層回路パターン領域 ３：パターン形成の導体除去部 ４：パターン形成の導体残存部 ５：パターン周辺部の導体除去部 ６：パターン周辺部の導体残存部 1: Inner layer circuit board 2: Inner layer circuit pattern area 3: Conductor removal portion for pattern formation 4: Conductor removal portion for pattern formation 5: Conductor removal portion for pattern peripheral portion 6: Conductor removal portion for pattern peripheral portion
───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.6，ＤＢ名) H05K 3/46 ──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. 6 , DB name) H05K 3/46
Claims (1)
して、縦、横及び斜め方向に寸法を補正した回路パター
ンを有する内層回路板の所定枚数及び外層材を接着用プ
リプレグを介して加熱加圧して一体にすることを特徴と
する多層印刷配線板用銅張積層板の製造方法。1. A predetermined number of inner layer circuit boards having a circuit pattern whose dimensions have been corrected in the vertical, horizontal and oblique directions and an outer layer material are heated and heated via an adhesive prepreg in consideration of a dimensional change in a multilayer bonding step. A method for producing a copper-clad laminate for a multilayer printed wiring board, which comprises pressing and integrating.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4246940A JP2903893B2 (en) | 1992-09-17 | 1992-09-17 | Method for producing copper-clad laminate for multilayer printed wiring board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4246940A JP2903893B2 (en) | 1992-09-17 | 1992-09-17 | Method for producing copper-clad laminate for multilayer printed wiring board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0697653A JPH0697653A (en) | 1994-04-08 |
| JP2903893B2 true JP2903893B2 (en) | 1999-06-14 |
Family
ID=17156009
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4246940A Expired - Lifetime JP2903893B2 (en) | 1992-09-17 | 1992-09-17 | Method for producing copper-clad laminate for multilayer printed wiring board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2903893B2 (en) |
-
1992
- 1992-09-17 JP JP4246940A patent/JP2903893B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0697653A (en) | 1994-04-08 |
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