JPH0564098B2 - - Google Patents
Info
- Publication number
- JPH0564098B2 JPH0564098B2 JP61015373A JP1537386A JPH0564098B2 JP H0564098 B2 JPH0564098 B2 JP H0564098B2 JP 61015373 A JP61015373 A JP 61015373A JP 1537386 A JP1537386 A JP 1537386A JP H0564098 B2 JPH0564098 B2 JP H0564098B2
- Authority
- JP
- Japan
- Prior art keywords
- inner layer
- board
- circuit pattern
- prepreg
- circuit board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 11
- 239000011889 copper foil Substances 0.000 claims description 11
- 238000000034 method Methods 0.000 claims description 11
- 238000004519 manufacturing process Methods 0.000 claims description 10
- 238000000465 moulding Methods 0.000 claims description 10
- 238000010438 heat treatment Methods 0.000 claims description 4
- 238000010030 laminating Methods 0.000 claims description 3
- 238000003475 lamination Methods 0.000 claims description 2
- 239000011521 glass Substances 0.000 description 4
- 238000007796 conventional method Methods 0.000 description 3
- 239000003822 epoxy resin Substances 0.000 description 3
- 229920000647 polyepoxide Polymers 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000003825 pressing Methods 0.000 description 2
- 230000007261 regionalization Effects 0.000 description 2
- 238000005476 soldering Methods 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 230000000052 comparative effect Effects 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000009719 polyimide resin Substances 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
Landscapes
- Laminated Bodies (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Description
［発明の技術分野］
本発明はボイドがなく、耐熱性にも優れた多層
板を製造することのできる多層板の製造方法に関
する。
［発明の技術的背景とその問題点］
近年の電子機器の少量多品種化に伴い、回路パ
ターン形成面が極端に少ない内層回路を有する特
殊な多層板が使用されるようになつてきている。
従来、このような多層板を製造する場合には、
一般の多層板と同様に次のような方法で製造され
ている。
すなわち、予め回路パターンを形成した所定枚
数の内層回路基板と、外層基板もしくは外層銅箔
とをプリプレグを介挿させつつ積層し、これらを
加熱加圧成形により一体化させている。
しかしながらこのような方法では、内層回路基
板の回路パターン形成面と回路パターン非形成面
に板厚差があり、かつ回路パターン非形成面が広
いために、加熱加圧成形時に内層回路基板の回路
パターン非形成面に充分な圧力がかからず、成形
品にボイドを生じ、特性が低下するという問題が
あつた。またこのボイドは内層回路基板とプリプ
レグ間にの生じたボイドであるため、後の半田工
程時に積層剥離を起すおそれがあつた。
この対策として、成形圧力を高めたり、プリプ
レグの硬化時間を長くする等の方法が行われてい
るが、その効果は充分ではなく、逆に製品に反り
やねじれを生じ、またレジンフローが大きくなつ
て作業性を低下させるという問題があつた。
［発明の目的］
本発明はこのような点に対処してなされたもの
で、回路パターン形成面が極端に少ない内層回路
基板を用いた場合でも、ボイドがなく、耐熱性も
良好な高品質の多層板を製造することができる多
層板の製造方法を提供することを目的とする。
［発明の概要］
すなわち本発明の多層板の製造方法は、予め回
路パターンを形成した内層回路基板と外層基板も
しくは外層銅箔とをプリプレグを介挿させつつ積
層し、これらを一体に加熱加圧成形して多層板を
製造するにあたり、前記内層回路基板の回路パタ
ーン非形成面にプリプレグ切片を配置した後、積
層および加熱加圧成形することにより、ボイドの
ない耐熱性に優れた高品質の多層板を製造可能と
したものである。
本発明においては、まず、たとえばガラスクロ
ス−エポキシ樹脂、ガラスクロス−ポリイミド樹
脂等の銅張積層板の銅箔面に常法により所定の内
層回路パターンを形成した内層回路基板と、この
内層回路基板と同材質の銅張積層板等の外層基板
もしくは外層銅箔とをプリプレグを介挿させつつ
積層する。
このとき、予め内層回路基板の回路パターン非
形成面に回路パターン形成面と板厚がほぼ等しく
なるように、内層回路基板と同材質のプリプレグ
切片を、たとえばそのプリプレグ切片と同系の熱
硬化性樹脂系接着剤により接着固定させておくこ
とが望ましい。なおこのプリプレグ切片は、回路
パターン非形成面のすべてに完全に嵌合配置する
必要はなく、角形状や円形状といつた比較的簡単
な形状でかつ回路パターン非形成面をできるだけ
縮小させ得る大きさのものを配置すれば充分であ
る。プリプレグ切片の厚さは、たとえば銅箔の厚
さが70μｍのものでは50μｍ、銅箔の厚さが35μｍ
のものでは25μｍ程度とすることが好ましい。
しかる後これら積層体を常法により通常の条件
で加熱加圧成形して一体化させる。
この方法においては、内層回路基板の回路パタ
ーン非形成面にプリプレグ切片を配置して、プリ
プレグ積層時に内層回路基板との間に広い面積に
わたつて隙間を生じることのないようにするの
で、成形時の加圧が充分かつほぼ均一に行われる
ことになり、ボイドのない耐熱性も良好な高品質
の多層板を得ることができる。
なお回路パターン非形成面にボイドを生じやす
くなるのは、隣接する回路間が1.6cm以上離れる
場合であり、このような場合に本発明は特に顕著
な効果を示す。
［発明の実施例］
以下、本発明の実施例について説明する。
実施例
銅箔厚70μｍのガラスクロス−エポキシ樹脂両
面銅張積層板の銅箔面に所定の内層回路パターン
を形成して得た、1.8cm×17.5cmの長方形状の回
路パターン非形成面を含む内層回路基板のその回
路パターン非形成面に、幅1.5cm、長さ17cm、厚
さ50μｍのガラスクロス−エポキシ樹脂プリプレ
グ切片を接着した。次いでこのプリプレグ切片が
接着された内層回路基板の両面に同じプリプレグ
を３枚ずつ重ね、さらにその両端にそれぞれ厚さ
18μｍの銅箔を重ね合せた後、40Kg／cm2、175℃
の成形条件で加熱加圧して多層板を得た。
比較例
実施例と同じ内層回路基板、外層銅箔、プリプ
レグを、内層回路基板の回路パターン非形成面に
プリプレグ切片を接着しない点を除いて実施例と
同様に積層した後、実施例と同じ条件で加熱加圧
成形して多層板を得た。
以上のようにして得られた多層板について、ボ
イドの発生の有無、半田処理時の剥れを調べた。
その結果を次表に示す。
[Technical Field of the Invention] The present invention relates to a method for producing a multilayer board that is void-free and has excellent heat resistance. [Technical Background of the Invention and Problems thereof] With the recent trend of small-volume, high-mix electronic devices, special multilayer boards having inner layer circuits with extremely small circuit pattern formation surfaces have come into use. Conventionally, when manufacturing such multilayer boards,
It is manufactured in the same way as general multilayer boards using the following method. That is, a predetermined number of inner layer circuit boards on which circuit patterns have been formed in advance and outer layer substrates or outer layer copper foil are laminated with prepreg interposed therebetween, and these are integrated by heating and pressure molding. However, in this method, there is a difference in thickness between the circuit pattern-formed surface and the non-circuit pattern-formed surface of the inner-layer circuit board, and the circuit pattern-free surface is wide, so the circuit pattern of the inner-layer circuit board is removed during hot-pressure molding. There was a problem in that sufficient pressure was not applied to the non-formed surface, causing voids in the molded product and deteriorating its properties. Furthermore, since these voids were generated between the inner layer circuit board and the prepreg, there was a risk that the lamination would peel off during the subsequent soldering process. As a countermeasure to this problem, methods such as increasing the molding pressure and prolonging the curing time of the prepreg have been used, but these methods are not sufficiently effective, and instead cause warping and twisting of the product, and increase resin flow. There was a problem that the work efficiency was reduced. [Objective of the Invention] The present invention has been made to address the above-mentioned problems, and even when using an inner layer circuit board with an extremely small circuit pattern formation surface, it is possible to create a high-quality, void-free and heat-resistant circuit board. It is an object of the present invention to provide a method for manufacturing a multilayer board that can manufacture a multilayer board. [Summary of the Invention] That is, the method for manufacturing a multilayer board of the present invention involves laminating an inner layer circuit board on which a circuit pattern has been formed in advance and an outer layer substrate or outer layer copper foil while interposing a prepreg, and heating and pressing them together. When manufacturing a multilayer board by molding, prepreg pieces are placed on the non-circuit pattern surface of the inner layer circuit board, and then laminated and heated and pressed to form a high-quality multilayer board with no voids and excellent heat resistance. This makes it possible to manufacture plates. In the present invention, first, an inner layer circuit board is prepared by forming a predetermined inner layer circuit pattern on the copper foil surface of a copper-clad laminate made of glass cloth-epoxy resin, glass cloth-polyimide resin, etc. by a conventional method, and this inner layer circuit board. An outer layer substrate such as a copper-clad laminate or an outer layer copper foil made of the same material is laminated with a prepreg interposed therebetween. At this time, in advance, a prepreg piece made of the same material as the inner layer circuit board is placed on the non-circuit pattern formed side of the inner layer circuit board so that the thickness is almost equal to the circuit pattern formed side. It is preferable to use adhesive to fix it. It should be noted that this prepreg piece does not need to be arranged completely to fit all of the non-circuit pattern-formed surfaces, but should have a relatively simple shape such as a square or circular shape and a size that can reduce the circuit-pattern-free surface as much as possible. It is sufficient to place one of these. The thickness of the prepreg section is, for example, 50 μm if the copper foil is 70 μm thick, and 35 μm if the copper foil is 35 μm thick.
The thickness is preferably about 25 μm. Thereafter, these laminates are integrally formed by heat and pressure molding under normal conditions using a conventional method. In this method, prepreg pieces are placed on the non-circuit-patterned surface of the inner-layer circuit board to prevent gaps from forming over a wide area between the inner-layer circuit board and the inner-layer circuit board when laminating the prepreg. This means that the pressure is applied sufficiently and almost uniformly, making it possible to obtain a high-quality multilayer board with no voids and good heat resistance. Note that voids are likely to occur on the surface on which no circuit pattern is formed when the distance between adjacent circuits is 1.6 cm or more, and the present invention exhibits a particularly remarkable effect in such a case. [Examples of the invention] Examples of the invention will be described below. Example: Obtained by forming a predetermined inner layer circuit pattern on the copper foil surface of a glass cloth-epoxy resin double-sided copper-clad laminate with a copper foil thickness of 70 μm, including a 1.8 cm x 17.5 cm rectangular circuit pattern-free surface. A glass cloth-epoxy resin prepreg section having a width of 1.5 cm, a length of 17 cm, and a thickness of 50 μm was adhered to the surface of the inner layer circuit board on which no circuit pattern was formed. Next, three sheets of the same prepreg are stacked on both sides of the inner layer circuit board to which this prepreg section is glued, and a thickness of
After overlapping 18μm copper foil, 40Kg/cm 2 , 175℃
A multilayer board was obtained by heating and pressing under the following molding conditions. Comparative Example The same inner layer circuit board, outer layer copper foil, and prepreg as in the example were laminated in the same manner as in the example except that the prepreg pieces were not bonded to the non-circuit pattern-formed surface of the inner layer circuit board, and then the same conditions as in the example were applied. A multilayer board was obtained by heat and pressure molding. The multilayer board obtained as described above was examined for the presence or absence of voids and for peeling during soldering.
The results are shown in the table below.
【表】
表からも明らかなように、本発明方形により得
られた多層板は、従来の方法により得られた多層
板と比較して、ボイドがなく、耐熱性にも優れて
いる。
［発明の効果］
以上説明したように本発明方法によれば、回路
パターン形成面が少なく回路パターン非形成面の
広い内層回路基板を用いた場合であつても、成形
時に充分な加圧が得られ、ボイドがなく耐熱性も
良好な品質のよい多層板を製造することができ
る。[Table] As is clear from the table, the multilayer board obtained by the rectangular method of the present invention has no voids and is superior in heat resistance compared to the multilayer board obtained by the conventional method. [Effects of the Invention] As explained above, according to the method of the present invention, sufficient pressure can be applied during molding even when an inner layer circuit board with a small circuit pattern-formed surface and a large non-circuit pattern-formed surface is used. It is possible to produce a high-quality multilayer board with no voids and good heat resistance.
Claims (1)
外層基板もしくは外層銅箔とをプリプレグを介挿
させつつ積層し、これらを一体に加熱加圧成形し
て多層板を製造するにあたり、前記内層回路基板
の回路パターン非形成面にプリプレグ切片を配置
した後、積層および加熱加圧成形を行うことを特
徴とする多層板の製造方法。 ２ プリプレグ切片を予め前記内層回路基板の回
路パターン非形成面に接着させておく特許請求の
範囲第１項記載の多層板の製造方法。[Claims] 1. In manufacturing a multilayer board by laminating an inner layer circuit board on which a circuit pattern has been formed in advance and an outer layer board or an outer layer copper foil with a prepreg interposed therebetween, and molding them together under heat and pressure. . A method for manufacturing a multilayer board, which comprises arranging prepreg pieces on the non-circuit pattern formed surface of the inner layer circuit board, and then performing lamination and heating and pressure molding. 2. The method of manufacturing a multilayer board according to claim 1, wherein prepreg pieces are bonded in advance to the circuit pattern-free surface of the inner layer circuit board.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61015373A JPS62173236A (en) | 1986-01-27 | 1986-01-27 | Manufacture of multi-layer plate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61015373A JPS62173236A (en) | 1986-01-27 | 1986-01-27 | Manufacture of multi-layer plate |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62173236A JPS62173236A (en) | 1987-07-30 |
| JPH0564098B2 true JPH0564098B2 (en) | 1993-09-13 |
Family
ID=11886973
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61015373A Granted JPS62173236A (en) | 1986-01-27 | 1986-01-27 | Manufacture of multi-layer plate |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62173236A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105291549B (en) * | 2015-11-06 | 2018-03-13 | 南京双威生物医学科技有限公司 | A kind of multimembrane heat seal device |
-
1986
- 1986-01-27 JP JP61015373A patent/JPS62173236A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS62173236A (en) | 1987-07-30 |
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