JPH0697444A - Thin film transistor - Google Patents
Thin film transistorInfo
- Publication number
- JPH0697444A JPH0697444A JP4210560A JP21056092A JPH0697444A JP H0697444 A JPH0697444 A JP H0697444A JP 4210560 A JP4210560 A JP 4210560A JP 21056092 A JP21056092 A JP 21056092A JP H0697444 A JPH0697444 A JP H0697444A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor layer
- film
- tft
- layer
- insulating film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- Liquid Crystal (AREA)
- Formation Of Insulating Films (AREA)
- Thin Film Transistor (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は絶縁ゲート形薄膜トラン
ジスタ（以下ＴＦＴと称す）に関するものであり、特に
半導体層にグロー放電法で得られる少なくとも一部が微
結晶化したシリコン（以下単に微結晶シリコンと称す）
を用いた場合に於いて、特性が良好で高い信頼性を得る
ことができるＴＦＴ構造に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an insulated gate thin film transistor (hereinafter referred to as a TFT), and particularly to a semiconductor layer in which at least a portion of silicon obtained by a glow discharge method (hereinafter simply referred to as microcrystalline silicon). Called)
The present invention relates to a TFT structure having good characteristics and high reliability in the case of using.
【０００２】[0002]
【従来の技術】従来の一般的なＴＦＴの構造及びその形
成法について図２とともに説明する。絶縁基板１上にゲ
ート電極２，ゲート絶縁膜３，半導体層４を順次堆積
し、半導体層４にソース電極５及びドレイン電極６を形
成することによりＴＦＴが作成される。絶縁基板１とし
ては、一般的にガラス板，セラミック板，石英板等が用
いられる。また、ゲート電極２はＣｒ，Ａｌ，Ｎｉ，Ａ
ｕ等の金属材料、ゲート絶縁膜３はＳｉＯ，ＳｉＯ2，
Ａｌ2Ｏ3，Ｔａ2Ｏ5，Ｙ2Ｏ3，Ｓｉ3Ｎ4，ＭｇＦ2等の
酸化物，窒化物または弗化物、半導体層４はＣｄＳ，Ｃ
ｄＳｅ，Ｔｅ，ＰｂＳ，アモルファスシリコンまたは微
結晶シリコン等で形成される。ソース電極５及びドレイ
ン電極６としてはＡｌ，Ａｕ，Ｎｉ，Ｃｒ，Ｉｎ等の半
導体層４とオーミックコンタクトが可能な金属が用いら
れる。2. Description of the Related Art The structure of a conventional general TFT and its forming method will be described with reference to FIG. A TFT is formed by sequentially depositing a gate electrode 2, a gate insulating film 3, and a semiconductor layer 4 on an insulating substrate 1 and forming a source electrode 5 and a drain electrode 6 on the semiconductor layer 4. As the insulating substrate 1, a glass plate, a ceramic plate, a quartz plate or the like is generally used. The gate electrode 2 is made of Cr, Al, Ni, A
The gate insulating film 3 is made of SiO, SiO 2 ,
Al 2 O 3, Ta 2 O 5, Y 2 O 3, Si 3 N 4, MgF 2 and the like oxides, nitrides or fluorides semiconductor layer 4 is CdS, C
It is formed of dSe, Te, PbS, amorphous silicon, microcrystalline silicon, or the like. As the source electrode 5 and the drain electrode 6, a metal such as Al, Au, Ni, Cr, In or the like capable of making ohmic contact with the semiconductor layer 4 is used.
【０００３】上記構造を有するＴＦＴを例えば液晶表示
装置のマルチプレックス駆動に使用する場合、ＴＦＴの
オフ抵抗（ＲOFF）が充分に高く遮断性が良好であるこ
と、オン抵抗（ＲON）が充分に低くオン／オフ比（Ｒ
OFF／ＲON）が高いこと及びスイッチング速度が大きい
ことを必要とし、更に長時間の動作に対して安定である
ことが要求される。このような特性を満足するＴＦＴを
実現するためにはＴＦＴのゲート絶縁膜３が、（１）絶
縁性が良好（ピンホールが無い）でかつ信頼性及び耐圧
が高いこと、（２）可動イオン密度が低いこと、（３）
半導体との界面準位密度が小さいこと、（４）半導体に
対する電界効果が大きいこと、等の条件を満たしている
ことが必要であるが、上記（１）と（４）は相反する要
求であり、これを同時に満足させることは困難である。
例えばスパッタリング法、ＣＶＤ法等でＳｉＯ3，Ｓｉ3
Ｎ4 等の薄膜を形成する場合、２０００〜３０００Å以
下の厚さではピンホールの無い薄膜を形成することは極
めて困難となる。しかしながら、陽極酸化法によれば、
数百Åの厚さでピンホールの無い絶縁膜を得ることが出
来、耐圧も高い。半導体表面に対する電界効果はゲート
に印加する電圧を一定とすれば絶縁膜の誘電率に比例し
厚さに反比例するので陽極酸化膜を用いることにより絶
縁性を良好に保持しながら厚さを薄くすることができ、
極めて大きな電界効果が期待される。When the TFT having the above structure is used, for example, for multiplex driving of a liquid crystal display device, the off resistance (R OFF ) of the TFT is sufficiently high and the blocking property is good, and the on resistance (R ON ) is sufficient. Low on / off ratio (R
OFF / R ON ) is required to be high and the switching speed is high, and it is required to be stable for long-term operation. In order to realize a TFT satisfying such characteristics, the gate insulating film 3 of the TFT has (1) good insulation (no pinhole), high reliability and high breakdown voltage, and (2) movable ions. Low density (3)
It is necessary that the interface state density with the semiconductor is small, (4) the electric field effect on the semiconductor is large, and the like, but the above (1) and (4) are contradictory requirements. , It is difficult to satisfy this at the same time.
For example, a sputtering method, SiO 3, Si 3 by a CVD method or the like
When forming a thin film of N 4 or the like, it becomes extremely difficult to form a thin film without pinholes with a thickness of 2000 to 3000 Å or less. However, according to the anodizing method,
With a thickness of several hundred Å, an insulating film without pinholes can be obtained, and the breakdown voltage is high. The electric field effect on the semiconductor surface is proportional to the dielectric constant of the insulating film and inversely proportional to the thickness when the voltage applied to the gate is constant, so using an anodized film reduces the thickness while maintaining good insulation. It is possible,
An extremely large electric field effect is expected.
【０００４】一方、半導体層４としては、アモルファス
シリコンを使用すると、従来用いられてきたＣｄＳｅ等
の化合物半導体に於いて問題となる化学両論的組成から
のずれに起因する特性のばらつきが少なく、またエネル
ギーギヤップも大きく真性キャリァの数が少ないこと等
のＴＦＴ用半導体層として優れた利点が得られる。しか
しながらアモルファスシリコンに於いては、そのキャリ
ァ移動度が極めて小さく応答速度の点で問題があった。
一方、グロー放電により、多量の水素で希釈したＳｉＨ
4 ガスを分解して形成した水素含有シリコン膜は微結晶
を含み、移動度が大であり、上記アモルファスシリコン
のＴＦＴとしての利点を損なうことなく応答速度が改善
される。従って、陽極酸化膜をゲート絶縁膜３として組
み合わせることにより、極めて特性の良いＴＦＴが作製
されると考えられる。On the other hand, when amorphous silicon is used as the semiconductor layer 4, there is little variation in the characteristics due to the deviation from the stoichiometric composition, which is a problem in the conventionally used compound semiconductors such as CdSe. Excellent advantages as a semiconductor layer for TFT, such as large energy gap and a small number of intrinsic carriers, can be obtained. However, in amorphous silicon, its carrier mobility is extremely small and there is a problem in response speed.
On the other hand, SiH diluted with a large amount of hydrogen by glow discharge
The hydrogen-containing silicon film formed by decomposing 4 gas contains microcrystals and has a high mobility, and the response speed is improved without impairing the advantages of the amorphous silicon as a TFT. Therefore, by combining an anodized film as the gate insulating film 3, it is considered that a TFT having excellent characteristics can be manufactured.
【０００５】[0005]
【発明が解決しようとする課題】しかしながら、標準酸
化還元電位の小さい（即ち酸素との結合力が弱い）Ｔａ
2Ｏ5からなる陽極酸化膜にグロー放電による微結晶シリ
コン層を堆積すると還元性雰囲気のために陽極酸化膜が
損傷を受けて劣化し、絶縁性が著しく低下するためＴＦ
Ｔのゲート絶縁膜３としての機能を果すことが出来なく
なる。陽極酸化膜をゲート絶縁膜３として用いる場合に
は必然的に半導体層４の形成工程はゲート絶縁膜３の形
成工程の後でなければならず、このため上記絶縁性の低
下を回避することが、良好なＴＦＴを作製する上で非常
に重要な要件となる。However, Ta having a small standard redox potential (that is, a weak binding force with oxygen) is Ta.
When a microcrystalline silicon layer formed by glow discharge is deposited on the anodic oxide film made of 2 O 5 , the anodic oxide film is damaged and deteriorated due to the reducing atmosphere, and the insulating property is significantly deteriorated.
It becomes impossible for T to function as the gate insulating film 3. When the anodic oxide film is used as the gate insulating film 3, the step of forming the semiconductor layer 4 must necessarily be after the step of forming the gate insulating film 3, so that the above-mentioned decrease in insulating property can be avoided. That is a very important requirement for producing a good TFT.
【０００６】[0006]
【課題を解決するための手段】本発明は上記問題点に鑑
み、技術的手段を駆使することにより、陽極酸化膜の絶
縁低下を招くことなく、微結晶シリコン層を半導体層と
して形成した新規有用なＴＦＴを提供することを目的と
する。SUMMARY OF THE INVENTION In view of the above problems, the present invention makes full use of technical means to provide a novel and useful method in which a microcrystalline silicon layer is formed as a semiconductor layer without lowering the insulation of an anodized film. The purpose is to provide a thin TFT.
【０００７】本発明の薄膜トランジスタは、基板上に形
成されたＴａ膜からなるゲート電極の表面が陽極酸化さ
れたＴａ2Ｏ5 からなる第１のゲート絶縁膜となり、該
第１のゲート絶縁膜上に窒化膜からなる第２のゲート絶
縁膜を介して水素の含有された微結晶シリコンからなる
半導体層が堆積され、該半導体層にはソース電極及びド
レイン電極が電気的接続されかつ露呈部分が絶縁保護膜
で被覆されていることを特徴とする。In the thin film transistor of the present invention, the surface of the gate electrode made of the Ta film formed on the substrate becomes the first gate insulating film made of Ta 2 O 5 anodized, and the first gate insulating film is formed on the first gate insulating film. A semiconductor layer made of hydrogen-containing microcrystalline silicon is deposited on the semiconductor layer through a second gate insulating film made of a nitride film, the source electrode and the drain electrode are electrically connected to the semiconductor layer, and the exposed portion is insulated. It is characterized by being covered with a protective film.
【０００８】[0008]
【作用】Ｔａ2Ｏ5 膜は標準酸化還元電位が−０．８１
Ｅ°（Ｖ）（電気化学通論 Ｐ４４５田島 栄著 共立
出版発行参照）と比較的小さく、還元性雰囲気下で容易
に酸素が脱離し易いという性質を有するが、本発明の構
造によれば、Ｔａ2Ｏ5からなる陽極酸化膜（第１のゲー
ト絶縁膜）上を窒化膜からなる第２のゲート絶縁膜が覆
っているので、半導体層を積層形成する際に用いられる
水素で希釈された反応ガスを利用するグロー放電法に対
してＴａ2Ｏ5膜中の酸素が水素と化合して脱離するとい
うことがなく、還元性雰囲気下での陽極酸化膜の損傷が
防止される。The Ta 2 O 5 film has a standard redox potential of −0.81.
It has a relatively small value of E ° (V) (see Electrochemical Theory, P445, Sakae Tajima, published by Kyoritsu Shuppan), and easily releases oxygen in a reducing atmosphere. However, according to the structure of the present invention, Ta is used. Since the second gate insulating film made of a nitride film covers the anodic oxide film made of 2 O 5 (first gate insulating film), the reaction diluted with hydrogen used when forming the semiconductor layers is formed. Oxygen in the Ta 2 O 5 film does not combine with hydrogen to be released from the glow discharge method using gas, and damage to the anodic oxide film in a reducing atmosphere is prevented.
【０００９】[0009]
【実施例】図１は本発明の一実施例を示すＴＦＴの構成
断面図である。DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a sectional view of the structure of a TFT showing an embodiment of the present invention.
【００１０】ガラス基板１０上にＴａ膜を堆積した後、
これを酒石酸アンモニウム水溶液に浸漬し、化成処理す
る。６５Ｖの定電圧化成で１０００ÅのＴａ2Ｏ5膜が作
製され、この結果Ｔａからなるゲート電極２０とＴａ表
面の薄い陽極酸化膜からなる第１の絶縁膜３０が形成さ
れる。第１の絶縁膜３０上にはＣＶＤ法またはスパッタ
リング法等で厚さ１０００ÅのＳｉ3Ｎ4からなる窒化膜
が第２の絶縁膜３１として積層される。第２の絶縁膜３
１は陽極酸化されたＴａ2Ｏ5膜即ち第１の絶縁膜を保護
する機能を有する。この第１の絶縁膜３０と第２の絶縁
膜３１で２重ゲート絶縁層が構成される。After depositing a Ta film on the glass substrate 10,
This is immersed in an ammonium tartrate aqueous solution and subjected to chemical conversion treatment. A 1000 Å Ta 2 O 5 film is formed by constant voltage formation of 65 V, and as a result, a gate electrode 20 made of Ta and a first insulating film 30 made of a thin anodic oxide film on the Ta surface are formed. A nitride film made of Si 3 N 4 having a thickness of 1000 Å is laminated as a second insulating film 31 on the first insulating film 30 by the CVD method or the sputtering method. Second insulating film 3
Reference numeral 1 has a function of protecting the anodized Ta 2 O 5 film, that is, the first insulating film. The first insulating film 30 and the second insulating film 31 form a double gate insulating layer.
【００１１】次に半導体層４０としてグロー放電により
多量の水素で希釈したＳｉＨ4 ガス例えば、ＳｉＨ4／
（ＳｉＨ4＋Ｈ2）＝０．０３を分解し、水素がドープさ
れた微結晶シリコン層を３０００Å積層し、次にソース
電極５０及びドレイン電極６０として３０００ÅのＴｉ
を蒸着すると本実施例のＴＦＴが作製される。半導体層
４０は微結晶シリコンの集合体あるいは一部が微結晶化
したアモルファス（非晶質）シリコン層で構成される。
また微結晶シリコンの粒径は５０Å程度から数百Å程度
に設定される。多量の水素で希釈したＳｉＨ4 ガスを用
いてグロー放電すると、得られる層はアモルファスシリ
コン層中に微結晶シリコンが島状に点在した状態とな
り、その粒径は一般的に５０〜１００Å程度である。こ
れを必要に応じて成長させると微結晶シリコンが順次増
大し、全体が多結晶体に移行する。このＴＦＴは保護膜
７０としてＣＶＤ法によりＳｉ3Ｎ4が３０００Å積層さ
れ、半導体層４０がコートされる。この保護膜７０は微
結晶シリコン層の保護のみならず半導体層４０の裏の表
面８０を空乏化し、オフ状態のリーク電流を減少させ、
ＴＦＴの特性を大きく向上させる。Next, as the semiconductor layer 40, SiH 4 gas diluted with a large amount of hydrogen by glow discharge, for example, SiH 4 /
(SiH 4 + H 2 ) = 0.03 is decomposed, a hydrogen-doped microcrystalline silicon layer is laminated on 3000 Å, and then 3000 Å Ti is used as the source electrode 50 and the drain electrode 60.
Is vapor-deposited to produce the TFT of this embodiment. The semiconductor layer 40 is composed of an aggregate of microcrystalline silicon or an amorphous silicon layer in which a part is microcrystallized.
The grain size of microcrystalline silicon is set to about 50 Å to several hundred Å. When glow discharge is performed using SiH 4 gas diluted with a large amount of hydrogen, the obtained layer has a state in which microcrystalline silicon is scattered like islands in the amorphous silicon layer, and the particle size is generally about 50 to 100Å. is there. When this is grown as necessary, the amount of microcrystalline silicon increases in sequence, and the whole becomes a polycrystalline body. In this TFT, as the protective film 70, 3000 Å of Si 3 N 4 is laminated by the CVD method, and the semiconductor layer 40 is coated. This protective film 70 not only protects the microcrystalline silicon layer, but also depletes the back surface 80 of the semiconductor layer 40, reducing the leak current in the off state,
The characteristics of the TFT are greatly improved.
【００１２】上記実施例において、Ｓｉ3Ｎ4の比誘電率
を６．４、Ｔａ2Ｏ5の比誘電率を２６．０とすれば、ゲ
ート絶縁膜をＳｉ3Ｎ4のみで形成して本実施例と同等の
電界効果を得るには１２５０Å程度の厚さに層設するこ
とが必要であるが、これではピンホールのために絶縁特
性が劣化する。しかるに上記実施例の如くゲート絶縁膜
をＴａ2Ｏ5膜とＳｉ3Ｎ4膜の複合膜で構成した場合、Ｔ
ａ2Ｏ5膜にはピンホール等の発生がなく高い絶縁特性が
得られる。またＴａ2Ｏ5膜上にＳｉ3Ｎ4膜を堆積するこ
とにより、微結晶シリコン層をグロー放電の還元性雰囲
気下で形成する際にＳｉ3Ｎ4膜がＴａ2Ｏ5膜を保護する
こととなりＴａ2Ｏ5膜を損傷することがなく、従って半
導体層４形成後も絶縁性の良好なＴａ2Ｏ5膜を維持する
ことができる。In the above embodiment, if the relative permittivity of Si 3 N 4 is 6.4 and the relative permittivity of Ta 2 O 5 is 26.0, the gate insulating film is formed of only Si 3 N 4. In order to obtain an electric field effect equivalent to that of this embodiment, it is necessary to form a layer with a thickness of about 1250Å, but this deteriorates the insulation characteristics due to pinholes. However, when the gate insulating film is composed of a composite film of Ta 2 O 5 film and Si 3 N 4 film as in the above embodiment, T
The a 2 O 5 film does not have pinholes, etc., and high insulation characteristics are obtained. By depositing the Si 3 N 4 film on the Ta 2 O 5 film also, the Si 3 N 4 film protects the Ta 2 O 5 film microcrystalline silicon layer when forming a reducing atmosphere of the glow discharge In other words, the Ta 2 O 5 film is not damaged, and therefore, the Ta 2 O 5 film having good insulating properties can be maintained even after the semiconductor layer 4 is formed.
【００１３】ゲート電極２０はＴａで構成されている
が、ｎチャンネル動作のＴＦＴに於いては、Ａｌ等の場
合と比較してＴａの仕事関数が大きいのでピンチオフ電
圧が正となり、ノーマル・オフのＴＦＴが得られ、ゲー
ト電圧が０Ｖでの抵抗（オフ抵抗）が高くなり、液晶マ
トリックス駆動用ＴＦＴとして適する特性が得られる。
また保護膜７０は、ＴＦＴの半導体層が直接大気と接触
することを防止し、微結晶シリコン層のゲートと逆の面
（裏面）８０に於けるバンドの曲がりを少なくし、特性
の安定化を向上せしると同時にオフ抵抗を高く保持する
作用を有する。更に液晶表示素子を駆動するための一方
のセル基板に適用した場合にも液晶層とＴＦＴが直接接
触するのを防止し、ＴＦＴの寿命特性の向上に寄与す
る。その他上記保護膜７０は、光の遮蔽のため金属層を
ＴＦＴの活性領域上に形成する場合にも重要で、保護膜
７０上に金属層を設け、ＴＦＴの活性領域を蔽った場合
にもリークによりオフ抵抗が低下するといった問題がな
い。Although the gate electrode 20 is made of Ta, in a n-channel operation TFT, the work function of Ta is larger than that in the case of Al or the like, so that the pinch-off voltage becomes positive and the normal-off state is obtained. A TFT can be obtained, and the resistance (OFF resistance) at a gate voltage of 0 V becomes high, and a characteristic suitable as a liquid crystal matrix driving TFT can be obtained.
Further, the protective film 70 prevents the semiconductor layer of the TFT from coming into direct contact with the atmosphere, reduces the bending of the band on the surface (rear surface) 80 of the microcrystalline silicon layer opposite to the gate, and stabilizes the characteristics. At the same time, it has the effect of holding off resistance high. Further, when it is applied to one cell substrate for driving a liquid crystal display element, it prevents direct contact between the liquid crystal layer and the TFT and contributes to improvement of life characteristics of the TFT. In addition, the protective film 70 is important when a metal layer is formed on the active region of the TFT to shield light, and also when the metal layer is provided on the protective film 70 to cover the active region of the TFT. There is no problem that the off resistance decreases due to leakage.
【００１４】図３は上述のＴＦＴに於けるドレイン電流
−ゲート電圧特性（ＶDS＝＋１０Ｖ）を示すものであ
る。測定したＴＦＴはソース電極５０とドレイン電極６
０間の間隔に対応するチヤネル長Ｌが４０μｍ，チヤネ
ル幅Ｗが２０００μｍのものである。またソースドレイ
ン間の電圧ＶDSは１０Ｖである。ゲート電圧が０Ｖ〜＋
５Ｖの範囲において３桁以上、０Ｖ〜＋１０Ｖの範囲に
おいて５桁のオン・オフ比（ドレイン電流比）が得られ
ていることがわかる。FIG. 3 shows the drain current-gate voltage characteristic (V DS = + 10 V) in the above-mentioned TFT. The measured TFT has a source electrode 50 and a drain electrode 6
The channel length L corresponding to the interval between 0 is 40 μm, and the channel width W is 2000 μm. The voltage V DS between the source and drain is 10V. Gate voltage is 0V to +
It can be seen that an on / off ratio (drain current ratio) of three digits or more is obtained in the range of 5 V and five digits in the range of 0 V to +10 V.
【００１５】[0015]
【発明の効果】以上詳説した如く、本発明はゲート絶縁
膜を陽極酸化膜とこの陽極酸化膜を微結晶シリコンのグ
ロー放電形成時に保護する保護膜との複合絶縁膜で形成
することにより信頼性の高いかつ特性の良好な微結晶シ
リコン半導体層のＴＦＴを構成したものであり、その技
術的意義は多大である。As described above in detail, according to the present invention, the gate insulating film is formed by the composite insulating film of the anodic oxide film and the protective film which protects the anodic oxide film during the glow discharge formation of microcrystalline silicon. The TFT is composed of a microcrystalline silicon semiconductor layer having high characteristics and good characteristics, and its technical significance is great.
【図１】本発明の一実施例を示す従来のＴＦＴの基本的
構成を示す断面図である。FIG. 1 is a sectional view showing a basic structure of a conventional TFT showing an embodiment of the present invention.
【図２】本従来発明のＴＦＴの基本的構成図である。FIG. 2 is a basic configuration diagram of a TFT of the present invention.
【図３】図１に示すＴＦＴのドレイン電流対ゲート電圧
特性を示す説明図である。FIG. 3 is an explanatory diagram showing drain current-gate voltage characteristics of the TFT shown in FIG.
１０ ガラス基板 ２０ ゲート電極 ３０ 第１の絶縁膜 ３１ 第２の絶縁膜 ４０ 半導体層 ５０ ソース電極 ６０ ドレイン電極 ７０ 保護膜 10 glass substrate 20 gate electrode 30 first insulating film 31 second insulating film 40 semiconductor layer 50 source electrode 60 drain electrode 70 protective film
Claims (1)
ト電極の表面が陽極酸化されたＴａ2Ｏ5からなる第１の
ゲート絶縁膜となり、該第１のゲート絶縁膜上に窒化膜
からなる第２のゲート絶縁膜を介して水素の含有された
微結晶シリコンからなる半導体層が堆積され、該半導体
層にはソース電極及びドレイン電極が電気的接続され、
かつ露呈部分が絶縁保護膜で被覆されていることを特徴
とする薄膜トランジスタ。1. A surface of a gate electrode made of a Ta film formed on a substrate becomes a first gate insulating film made of anodized Ta 2 O 5 , and a nitride film is formed on the first gate insulating film. A semiconductor layer made of hydrogen-containing microcrystalline silicon is deposited through a second gate insulating film made of, and a source electrode and a drain electrode are electrically connected to the semiconductor layer,
A thin film transistor characterized in that the exposed portion is covered with an insulating protective film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21056092A JPH0691256B2 (en) | 1992-08-07 | 1992-08-07 | Thin film transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21056092A JPH0691256B2 (en) | 1992-08-07 | 1992-08-07 | Thin film transistor |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58015748A Division JPS59141271A (en) | 1982-02-25 | 1983-01-31 | Thin-film transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0697444A true JPH0697444A (en) | 1994-04-08 |
| JPH0691256B2 JPH0691256B2 (en) | 1994-11-14 |
Family
ID=16591346
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP21056092A Expired - Lifetime JPH0691256B2 (en) | 1992-08-07 | 1992-08-07 | Thin film transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0691256B2 (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0744776A2 (en) * | 1995-05-25 | 1996-11-27 | Central Glass Company, Limited | Amorphous silicon thin film transistor and method preparing same |
| EP0744775A2 (en) * | 1995-05-25 | 1996-11-27 | Central Glass Company, Limited | Microcrystal silicon thin film transistor |
| KR100283788B1 (en) * | 1995-09-28 | 2001-04-02 | 가네꼬 히사시 | Method of fabricating field effect thin film transistor |
| JP2015043388A (en) * | 2013-08-26 | 2015-03-05 | 国立大学法人 琉球大学 | Semiconductor device, method of manufacturing semiconductor device, and electronic apparatus |
-
1992
- 1992-08-07 JP JP21056092A patent/JPH0691256B2/en not_active Expired - Lifetime
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0744776A2 (en) * | 1995-05-25 | 1996-11-27 | Central Glass Company, Limited | Amorphous silicon thin film transistor and method preparing same |
| EP0744775A2 (en) * | 1995-05-25 | 1996-11-27 | Central Glass Company, Limited | Microcrystal silicon thin film transistor |
| EP0744775A3 (en) * | 1995-05-25 | 1997-11-26 | Central Glass Company, Limited | Microcrystal silicon thin film transistor |
| EP0744776A3 (en) * | 1995-05-25 | 1997-11-26 | Central Glass Company, Limited | Amorphous silicon thin film transistor and method preparing same |
| US5834796A (en) * | 1995-05-25 | 1998-11-10 | Central Glass Company, Limited | Amorphous silicon thin film transistor and method of preparing same |
| KR100283788B1 (en) * | 1995-09-28 | 2001-04-02 | 가네꼬 히사시 | Method of fabricating field effect thin film transistor |
| JP2015043388A (en) * | 2013-08-26 | 2015-03-05 | 国立大学法人 琉球大学 | Semiconductor device, method of manufacturing semiconductor device, and electronic apparatus |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0691256B2 (en) | 1994-11-14 |
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