JPS59193062A - Polycrystalline silicon thin film transistor - Google Patents
Polycrystalline silicon thin film transistorInfo
- Publication number
- JPS59193062A JPS59193062A JP6547083A JP6547083A JPS59193062A JP S59193062 A JPS59193062 A JP S59193062A JP 6547083 A JP6547083 A JP 6547083A JP 6547083 A JP6547083 A JP 6547083A JP S59193062 A JPS59193062 A JP S59193062A
- Authority
- JP
- Japan
- Prior art keywords
- polycrystalline silicon
- thin film
- film transistor
- electrode
- silicon thin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 229910021420 polycrystalline silicon Inorganic materials 0.000 title claims abstract description 40
- 239000010409 thin film Substances 0.000 title claims abstract description 24
- 239000010408 film Substances 0.000 claims abstract description 31
- 229910045601 alloy Inorganic materials 0.000 claims abstract description 9
- 239000000956 alloy Substances 0.000 claims abstract description 9
- 229910052723 transition metal Inorganic materials 0.000 claims abstract description 9
- 150000003624 transition metals Chemical class 0.000 claims abstract description 9
- 230000007704 transition Effects 0.000 claims description 2
- 229910021419 crystalline silicon Inorganic materials 0.000 claims 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims 1
- 239000010931 gold Substances 0.000 claims 1
- 229910052737 gold Inorganic materials 0.000 claims 1
- 238000000137 annealing Methods 0.000 abstract description 9
- 238000000034 method Methods 0.000 abstract description 6
- 238000009792 diffusion process Methods 0.000 abstract description 5
- 239000013078 crystal Substances 0.000 abstract description 4
- 238000004544 sputter deposition Methods 0.000 abstract description 3
- 239000012212 insulator Substances 0.000 abstract description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 abstract 1
- 229910052593 corundum Inorganic materials 0.000 abstract 1
- 238000009413 insulation Methods 0.000 abstract 1
- 229910001845 yogo sapphire Inorganic materials 0.000 abstract 1
- 239000004065 semiconductor Substances 0.000 description 14
- 239000000758 substrate Substances 0.000 description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 238000001259 photo etching Methods 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 238000007740 vapor deposition Methods 0.000 description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 239000007772 electrode material Substances 0.000 description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- 239000011159 matrix material Substances 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- -1 CdS and Cd8e Chemical class 0.000 description 1
- 229910000990 Ni alloy Inorganic materials 0.000 description 1
- 241000282806 Rhinoceros Species 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000005284 excitation Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 238000009832 plasma treatment Methods 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 229910052702 rhenium Inorganic materials 0.000 description 1
- 230000000087 stabilizing effect Effects 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 238000007738 vacuum evaporation Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/7866—Non-monocrystalline silicon transistors
- H01L29/78672—Polycrystalline or microcrystalline silicon transistor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/45—Ohmic electrodes
- H01L29/456—Ohmic electrodes on silicon
- H01L29/458—Ohmic electrodes on silicon for thin film silicon, e.g. source or drain electrode
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明は多結晶シリコンを用いた薄膜トランジスタに関
するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a thin film transistor using polycrystalline silicon.
；ｉ才膜トジンジスタは、絶縁体基板上に蒸着等により
、半導体薄膜を被着形成して能動素子を作ったもので、
通常は１８、界効果形であり、才１に造および動作とも
にＭ（Ｊ８− ）’Ｅ’ｉ’ Ｋ 類似している。しか
しながらＭＯＳ −ＦＥ’ｌ’が通常犀、Ｒ７晶基板を
用いて形成されるのに対してこの薄膜トランジスタは絶
縁体基板上に形成した半導体薄膜によって４１・（成さ
れるために大面状トランジスタプレイを製作できるとい
う利点を有している。このだめ、例えは、液晶マトリッ
クスディスプレイのクロストーク防止用スイッチング素
子として極めて好適である。すなわち液晶マトリックス
ディスプレイは近年ポケットテレビやコンピュータ端用
川扱儲として一発が進められ、画像の一層の精細化が求
められているが、画素子数の増加に伴なうクロストーク
を防止するためには、各画素にスイッチング素子を付設
する手段が有効である。この場合、薄膜トランジスタを
用いればディスプレイパネルの一方の基板上に形成でき
るので有利である。またこの場合、薄膜を構成する半導
体としては、ＣｄＳ 、 Ｃｄ８ｅ等の化合物やアモル
ファスシリコン等も用いられるが、特性の安定性や無公
害の観点から多結晶シリコンが最もすぐれている。An active element is an active element made by depositing a semiconductor thin film on an insulating substrate by vapor deposition or the like.
Normally, it is a field effect type, and is similar in structure and operation to M(J8-)'E'i'K. However, while MOS-FE'l' is usually formed using a rhinoceros or R7 crystal substrate, this thin film transistor is formed using a semiconductor thin film formed on an insulating substrate. It has the advantage that it can be manufactured as a switching element for preventing crosstalk in liquid crystal matrix displays.In other words, liquid crystal matrix displays have recently become popular as devices for pocket TVs and computer terminals. As the number of pixels continues to increase, there is a demand for further definition of images, and in order to prevent crosstalk caused by an increase in the number of pixels, it is effective to attach a switching element to each pixel. In this case, it is advantageous to use a thin film transistor because it can be formed on one substrate of the display panel.Also, in this case, compounds such as CdS and Cd8e, amorphous silicon, etc. can be used as the semiconductor constituting the thin film, but the characteristics Polycrystalline silicon is the best in terms of stability and non-polluting properties.
第１図および＃２図は、通常用いられでいるこの稀の薄
膜トランジスタの一例を示すや細断面図である。同図に
おいて、Ｉけガラス等からなる絶縁体基板、２は半導体
膜、３は絶縁膜、４，５はソース、ドレイン電極、６け
ゲート電極である。FIGS. 1 and 2 are thin cross-sectional views showing an example of this rare thin film transistor that is commonly used. In the figure, an insulating substrate made of glass or the like, 2 a semiconductor film, 3 an insulating film, 4 and 5 a source electrode, a drain electrode, and a 6 gate electrode.
しかしながら、上記構成を有するＭＩＩＮ）ランジスタ
において、半導体膜２が多結晶シリコンの場合、膜厚が
薄いと結晶性が不十分で良好々動作特性が得られず、良
好な動作特性を得るためには膜厚は約２０００λ以上、
望１しく岐約５ｏｏｏＡ以上必要である。ところが、半
導体膜２の膜厚をこのように厚くすると、第１図、第２
図の構造の場合、ゲートに電圧を印加してもソース可、
極４およびドレイン電極５近傍の半導体膜２にキャリア
が十分に励起されず、動作しにくくなるという欠点があ
った。そこで半導体膜２として多結晶シリコンを用いる
場合には、キャリア励起上、有利な第３図、第４図の構
造が望ましいと考えられる。However, in the MIIN) transistor having the above configuration, if the semiconductor film 2 is made of polycrystalline silicon, if the film thickness is thin, the crystallinity will be insufficient and good operating characteristics will not be obtained. The film thickness is approximately 2000λ or more,
Preferably, approximately 500A or more is required. However, if the thickness of the semiconductor film 2 is increased in this way,
In the case of the structure shown in the figure, even if a voltage is applied to the gate, the source can be
There was a drawback that carriers were not sufficiently excited in the semiconductor film 2 near the pole 4 and the drain electrode 5, making it difficult to operate. Therefore, when polycrystalline silicon is used as the semiconductor film 2, the structures shown in FIGS. 3 and 4, which are advantageous in terms of carrier excitation, are considered desirable.
なお、第３図、第４図において、ｌ＠１図、第２図と同
一部分には同一符号を付しである。しかしながら、第３
図の構造ではソース電極４およびドレイン１ｔＬ極５を
形成後、多結晶シリコンの半導体膜２を形成することに
なる妙よ、多結晶シリコン膜を形成するためＫは基板温
度を約５００−Ｃあるいけそれ以上に士げる必要があシ
、シリコン膜を形成する時点で電極材料がシリコン中に
拡散、あるいはシリコンと反応してしまい、笑際上採用
できないという欠点がある。結局半導体ｐＡ２として多
結晶シリコンを用いる場合には第４図の構造をとらざる
を得なぐなる。In FIGS. 3 and 4, the same parts as in FIGS. 1 and 2 are given the same reference numerals. However, the third
In the structure shown in the figure, after forming the source electrode 4 and drain 1tL pole 5, the polycrystalline silicon semiconductor film 2 is formed.In order to form the polycrystalline silicon film, K is the substrate temperature of about 500-C. However, it is necessary to take more precautions than this, and the disadvantage is that the electrode material diffuses into the silicon or reacts with the silicon at the time of forming the silicon film, making it practically unusable. In the end, if polycrystalline silicon is used as the semiconductor pA2, the structure shown in FIG. 4 has to be adopted.
第４図の構造の場合、ソース電極４．ドレインｔ＆５の
形成は、マスク蒸着でも可能であるが、電極パターンの
種度が不十分であシ、ソース電極今とドレイン電極５間
のリークが起りゃすいなどの欠点がある。これに対して
フォトエツチングでは容易に所定の電極パターンを形成
することができて望まし騒結果を得ることができる。ま
た、電極材料としては多結晶シリコンと反応しにくいこ
と、良好な電気的コンクタトがと五ることなどのφ件を
考慮すると、はぼＡｔに限定される。結局多結晶シリコ
ン薄膜トランジスタのソース電極４゜ドレイン電極５と
してはフォトエツチングでＡｔのパターンを形成したも
のが望寸しいことになる。In the case of the structure shown in FIG. 4, the source electrode 4. The drains T&5 can be formed by mask vapor deposition, but there are drawbacks such as the electrode pattern is insufficiently seeded and leakage between the source electrode 5 and the drain electrode 5 is likely to occur. On the other hand, photoetching can easily form a predetermined electrode pattern and produce desired results. Further, the electrode material is limited to At, taking into account the following factors, such as being difficult to react with polycrystalline silicon and having good electrical contact. As a result, it is desirable that the source electrode 4 and the drain electrode 5 of a polycrystalline silicon thin film transistor have an At pattern formed by photoetching.
しかしながら、このような多結晶シリコン薄膜トランジ
スタを製作したところ、以下に記述するような問題があ
った。すなわち、多結晶シリコン薄膜トランジスタは、
完成後にｈｙ囲気中あるいはＨ２を含んだ市雰囲気中で
アニール処理を行なうと動作管性が改善されるが、アニ
ールｌ１ｌｉＨｉ４：が高いとンース屯極４．ドレイン
電極５を形成するＡｔが多結晶シリコンの結晶粒界に拡
散し、オフ抵抗が低下する。However, when such a polycrystalline silicon thin film transistor was manufactured, there were problems as described below. In other words, the polycrystalline silicon thin film transistor is
If annealing is performed after completion in a hy environment or in a city atmosphere containing H2, the operational performance will be improved, but if the annealing level is high, the 4. At which forms the drain electrode 5 diffuses into the grain boundaries of polycrystalline silicon, reducing the off-resistance.
これを抑止するためには、アニール処理をＡｔの多結晶
シリコンの結晶粒界への拡散が顕著とならない範囲の低
い温度で行なえばよいが、このような温度でアニール処
理を行なった場合には動作特性の改善効果が十分に得ら
れず、このため良好７よ動作特性が得にくくなるという
問題があった。In order to prevent this, annealing should be performed at a low temperature that does not cause noticeable diffusion of At into the grain boundaries of polycrystalline silicon, but if annealing is performed at such a temperature, There was a problem in that the effect of improving the operating characteristics was not sufficiently obtained, and as a result, it was difficult to obtain operating characteristics better than Good 7.
したがって本発明は、このような問題に＠今てなされた
ものであり、その目的とするところは、ソース電極、ド
レイン電極を形成するＡｔの多結晶シリコンの結晶粒子
ｆへの拡散全抑制して動作特性が良好でかつ一定の多結
晶シリコン埠膜トランジスタを提供することにある。Therefore, the present invention has been made to solve this problem, and its purpose is to completely suppress the diffusion of At into the crystal grains f of polycrystalline silicon forming the source and drain electrodes. An object of the present invention is to provide a polycrystalline silicon barrier film transistor with good and constant operating characteristics.
このような目的？達成するために本発す」は、ソース電
極、ドレイン電極をＡｔと逓移輩りとの合金で形成した
ものである。A purpose like this? In order to achieve this, the source electrode and the drain electrode are formed of an alloy of At and a transition layer.
〔発明の笑施ｆ！ｉ Ｊ 次に図面を用いて本発明の案施例をＩ？細に説明する。[Invention lol! i J Next, an example of the present invention will be explained using the drawings. Explain in detail.
第５図は本発明による多結晶シリコン薄膜トランジスタ
の一例を示す断面図であ）、前述の図と同一部分忙は同
一符号を付しである。同図において、多Ｍ、１％シリコ
ン薄股トランジスタは、絶縁体基板ｌ上に真空蒸着して
形成した多結晶シリコン半導体膜２を用い、ゲート絶縁
膜３にはスパッタで形成したＡｔｘｃ）ｓを用い、ゲー
ト電極６はＡｔを真空蒸着したＡｔＭをフォトエツチン
グすることＫよシ形成している。そして、ソース電極４
０゜ドレイン電極５０はＡｔＫ遷移金属としてへｉをモ
ル比で２５％含むＡｔ−２５＊Ｎｉ合金を真空蒸着した
Ａｔ Ｎ７合金膜をフォトエツチングすることによシ形
成されている。このとき、ゲート絶縁膜３を形成する前
に多結晶シリコン半導体膜２の表面を酸素プラノ１にさ
らし、酸化処理膜を形成しておくと、多結晶シリコン薄
膜トランジスタのオフ抵抗の経時変化を抑止することが
可能であり、多結晶シリコン半導体膜２０表面の酸素プ
ラズマ処理は特性の安定化に極めて有効である。FIG. 5 is a cross-sectional view showing an example of a polycrystalline silicon thin film transistor according to the present invention), in which the same parts as in the previous figures are given the same reference numerals. In the same figure, the multi-M, 1% silicon thin-stitch transistor uses a polycrystalline silicon semiconductor film 2 formed by vacuum evaporation on an insulating substrate l, and the gate insulating film 3 is made of Atxc)s formed by sputtering. The gate electrode 6 is formed by photo-etching AtM on which At is vacuum-deposited. And source electrode 4
The 0° drain electrode 50 is formed by photo-etching an At-N7 alloy film which is vacuum-deposited with an At-25*Ni alloy containing 25% of heli as an AtK transition metal in molar ratio. At this time, if the surface of the polycrystalline silicon semiconductor film 2 is exposed to oxygen plano 1 and an oxidized film is formed before forming the gate insulating film 3, changes over time in the off-resistance of the polycrystalline silicon thin film transistor can be suppressed. Therefore, oxygen plasma treatment of the surface of the polycrystalline silicon semiconductor film 20 is extremely effective in stabilizing the characteristics.
このような多結晶シリコン薄膜トランジスタを完成した
後にＮ２＋ＩＯ％１（２８囲気中で約４５０″Ｃで約３
０分間アニール処理をした。比較としてソース電極、ド
レイン電極にＡｔ膜を用いた以外は全く同じ方法によっ
た多結晶シリコン′ｆＷ膜トランジスタを製作した。そ
して、両者のオフ抵抗を比較したところ、前者の値は多
結晶シリコン膜の比抵抗と、ソース電極、ドレイン電極
の寸法から期待されるものとはほぼ一致したが、後者の
値はそれよシ約１桁低下していた。また、ソース電極。After completing such a polycrystalline silicon thin film transistor, N2+IO%1 (approximately 3
Annealing was performed for 0 minutes. For comparison, a polycrystalline silicon fW film transistor was fabricated using the same method except that an At film was used for the source and drain electrodes. When we compared the off-resistances of the two, we found that the former value almost matched what was expected from the specific resistance of the polycrystalline silicon film and the dimensions of the source and drain electrodes, but the latter value was more It was down by about one digit. Also the source electrode.
ドレイン電極にＡｔ膜を用い、完成後のアニール温度を
約３５０’Ｃ以外は全く同じ方法によった多結晶シリコ
ン薄膜トランジスタのオフ抵抗は、多結晶シリコン膜の
比抵抗と、ンース電極、ドレイン箪極の寸法から期待さ
れるものとほぼ一致したが、その相互コンダクタンスの
値は本発明による多結晶シリコン薄膜トランジスタの値
の約３０チであった。The off-resistance of a polycrystalline silicon thin film transistor made using the same method except that an At film is used for the drain electrode and the annealing temperature after completion is approximately 350'C is determined by the specific resistance of the polycrystalline silicon film, the source electrode, and the drain electrode. The transconductance value was approximately 30 cm higher than that of the polycrystalline silicon thin film transistor according to the present invention.
々お、前述した実施例では、ソース電極、ドレイン電極
に遷移金属としてＡｔ−２５％Ｎ１合金を用いた場合に
ついて説明したが、本発明はこれに限定されず、Ｎｉの
代りに他の遷移金属として例えばＣｏ、 Ｐｔ、 Ｗ、
Ｍｏ、 Ｐｄ、 Ｒｅ、 Ｔａ、 ’１’、ｉな、ど
を用いても良い。また、その含有量は２５％（モル比）
に限定されず、５〜５０％の範囲であれば良い。この場
合、遷移金属の含有量が５％未満ではＡｔの多結晶シリ
コンの結晶粒界への拡散を抑止する効果が得られず、５
０％をこだると多結晶シリコンとの電気的コンタクトが
得Ｋ＜くなる。In the above-mentioned embodiments, a case was explained in which an At-25%N1 alloy was used as the transition metal for the source electrode and the drain electrode, but the present invention is not limited to this, and other transition metals may be used instead of Ni. For example, Co, Pt, W,
Mo, Pd, Re, Ta, '1', i, etc. may be used. In addition, its content is 25% (molar ratio)
It is not limited to , and may be in the range of 5 to 50%. In this case, if the transition metal content is less than 5%, the effect of suppressing the diffusion of At into the grain boundaries of polycrystalline silicon cannot be obtained;
When the value exceeds 0%, electrical contact with polycrystalline silicon can be obtained.
また、前述した冥施例では、ソース電極、ドレイン電極
のＡ／、合金膜を蒸着法により形成した場合について説
明したが、本発明はこれに限定されず、他の方法、例え
ばスパッタなどによって形成しても良い。Further, in the above-mentioned example, a case was explained in which the source electrode, the drain electrode A/, and the alloy film were formed by the vapor deposition method. However, the present invention is not limited to this, and may be formed by other methods such as sputtering. You may do so.
以上説明したように本発明によれば、ソース電極、ドレ
イン電極材料にＡｔと遷移金属との合金を用いることに
よって、多結晶シリコン薄膜トランジスタ完成後のアニ
ール処理時のＡｔの多結晶シリコンの結晶粒界への拡散
が抑制されるので、アニール処理を高温度で行なうこと
ができるため、薄膜トランジスタの動作特性が大幅に向
上するという極めて優れた効果が得られる。As explained above, according to the present invention, by using an alloy of At and a transition metal as the material for the source and drain electrodes, the At crystal grain boundaries of polycrystalline silicon during annealing treatment after completion of a polycrystalline silicon thin film transistor are Since diffusion into the oxide layer is suppressed, the annealing process can be performed at a high temperature, resulting in an extremely excellent effect of significantly improving the operating characteristics of the thin film transistor.
第１図ないし第４図は従来の多結晶シリコン薄刃４トラ
ンジスタを示す要部断面図、第５図は本発明による゛多
結晶シリコン薄膜トランジスタの一例を示す狭部断面図
である。
！・・・・絶縁体基板、２・・・・半導体膜（多結晶シ
リコン膜）、３・・・・絶縁膜、→・・・・ソース電極
、５・・・・ドレイン電極、６・・・・ゲート電極、４
０・・・・ソース電極、５０・・・・ドレイン電極。1 to 4 are sectional views of essential parts of a conventional polycrystalline silicon thin-film transistor, and FIG. 5 is a narrow sectional view of an example of a polycrystalline silicon thin film transistor according to the present invention. ! ... Insulator substrate, 2 ... Semiconductor film (polycrystalline silicon film), 3 ... Insulating film, → ... Source electrode, 5 ... Drain electrode, 6 ...・Gate electrode, 4
0...source electrode, 50...drain electrode.
Claims (1)
リコン膜上にンース′＆ｃ極、ドレイン′に極が形成さ
れた多結晶シリコン薄膜トランジスタにおいて、前記ン
ース電極、ドレイン篭極をＡｔと遷移金酋との合金で形
成することを特徴とした多結晶シリコン薄膜トランジス
タ。 ２、前記Ａｔと遷移金属との合金が遷移金属をモル比で
５〜５０％含んだことを特徴とする特許請求の範囲第１
項記載の多結晶シリコン薄膜トランジスタ。[Scope of Claims] 1. A polycrystalline silicon thin film transistor in which a polycrystalline silicon film is used as a semi-integrated layer, and a second electrode and a drain electrode are formed on the grown crystalline silicon film. A polycrystalline silicon thin film transistor characterized in that its poles are formed of an alloy of At and transition gold. 2. Claim 1, characterized in that the alloy of At and transition metal contains a transition metal in a molar ratio of 5 to 50%.
The polycrystalline silicon thin film transistor described in 2.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6547083A JPS59193062A (en) | 1983-04-15 | 1983-04-15 | Polycrystalline silicon thin film transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6547083A JPS59193062A (en) | 1983-04-15 | 1983-04-15 | Polycrystalline silicon thin film transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59193062A true JPS59193062A (en) | 1984-11-01 |
| JPH0554271B2 JPH0554271B2 (en) | 1993-08-12 |
Family
ID=13288029
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6547083A Granted JPS59193062A (en) | 1983-04-15 | 1983-04-15 | Polycrystalline silicon thin film transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59193062A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04130776A (en) * | 1990-09-21 | 1992-05-01 | Casio Comput Co Ltd | Thin film transistor |
| JPH04130777A (en) * | 1990-09-21 | 1992-05-01 | Casio Comput Co Ltd | Manufacture of thin film transistor |
| KR100799824B1 (en) | 2005-08-17 | 2008-01-31 | 가부시키가이샤 고베 세이코쇼 | Source/drain electrodes, transistor substrates and manufacture methods thereof, and display devices |
| US7683370B2 (en) | 2005-08-17 | 2010-03-23 | Kobe Steel, Ltd. | Source/drain electrodes, transistor substrates and manufacture methods, thereof, and display devices |
| US7915062B2 (en) | 2006-06-22 | 2011-03-29 | Mitsubishi Electric Corporation | Method of manufacturing a TFT array substrate |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS50140269A (en) * | 1974-04-27 | 1975-11-10 | ||
| JPS5821868A (en) * | 1981-08-03 | 1983-02-08 | Hitachi Ltd | Manufacture of thin polycrystalline silicon film transistor |
-
1983
- 1983-04-15 JP JP6547083A patent/JPS59193062A/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS50140269A (en) * | 1974-04-27 | 1975-11-10 | ||
| JPS5821868A (en) * | 1981-08-03 | 1983-02-08 | Hitachi Ltd | Manufacture of thin polycrystalline silicon film transistor |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04130776A (en) * | 1990-09-21 | 1992-05-01 | Casio Comput Co Ltd | Thin film transistor |
| JPH04130777A (en) * | 1990-09-21 | 1992-05-01 | Casio Comput Co Ltd | Manufacture of thin film transistor |
| KR100799824B1 (en) | 2005-08-17 | 2008-01-31 | 가부시키가이샤 고베 세이코쇼 | Source/drain electrodes, transistor substrates and manufacture methods thereof, and display devices |
| US7683370B2 (en) | 2005-08-17 | 2010-03-23 | Kobe Steel, Ltd. | Source/drain electrodes, transistor substrates and manufacture methods, thereof, and display devices |
| US7915062B2 (en) | 2006-06-22 | 2011-03-29 | Mitsubishi Electric Corporation | Method of manufacturing a TFT array substrate |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0554271B2 (en) | 1993-08-12 |
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