JPH0464190B2 - - Google Patents
Info
- Publication number
- JPH0464190B2 JPH0464190B2 JP59194308A JP19430884A JPH0464190B2 JP H0464190 B2 JPH0464190 B2 JP H0464190B2 JP 59194308 A JP59194308 A JP 59194308A JP 19430884 A JP19430884 A JP 19430884A JP H0464190 B2 JPH0464190 B2 JP H0464190B2
- Authority
- JP
- Japan
- Prior art keywords
- oxide film
- manufacturing
- film
- tft
- present
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000010408 film Substances 0.000 claims description 34
- MWUXSHHQAYIFBG-UHFFFAOYSA-N Nitric oxide Chemical compound O=[N] MWUXSHHQAYIFBG-UHFFFAOYSA-N 0.000 claims description 12
- 239000007789 gas Substances 0.000 claims description 12
- 238000004519 manufacturing process Methods 0.000 claims description 11
- 239000004065 semiconductor Substances 0.000 claims description 9
- 239000000758 substrate Substances 0.000 claims description 9
- 238000000034 method Methods 0.000 claims description 8
- 239000010409 thin film Substances 0.000 claims description 8
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 claims description 7
- 229910000077 silane Inorganic materials 0.000 claims description 7
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 229910021417 amorphous silicon Inorganic materials 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 239000012528 membrane Substances 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 230000036962 time dependent Effects 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Liquid Crystal (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Formation Of Insulating Films (AREA)
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、透明基板上に薄膜トランジスター
（以後TFTと記す）を形成し、液晶を基板間に狭
んだ表示装置や、TFTを用いたイメージセンサ
ーにおける、酸化膜の製造方法に関する。[Detailed Description of the Invention] [Industrial Application Field] This invention relates to a display device in which a thin film transistor (hereinafter referred to as TFT) is formed on a transparent substrate and a liquid crystal is sandwiched between the substrates, and a display device using TFT. The present invention relates to a method for manufacturing an oxide film in an image sensor.
従来、通常のガラスが使用できる低温でゲート
酸化膜作成方法として、SiH4ガスとN2Oガスを
使用した低圧および常圧CVD，SiH4とN2Oガス
を使用したプラズマCVDによる酸化膜が知られ
ている。
Conventionally, gate oxide films have been formed using low-pressure and normal-pressure CVD using SiH 4 gas and N 2 O gas, and plasma CVD using SiH 4 and N 2 O gas, as methods for forming gate oxide films at low temperatures where ordinary glass can be used. Are known.
ゲート酸化膜として必要な特性は、リーク電流
が少なく膜の比抵抗が1014Ωcm以上、トランジス
タのスレツシヨルド電圧が低いこと、すなわち絶
縁膜内に電荷が残らないこと。また電気特性にお
いて、ヒステリシス巾が少ないこと。段差比膜性
が良く、膜のブレークダウン電圧が高いこと、な
どである。しかしながら従来の方法による酸化膜
は、Ｎ型基板を用いたＣ−Ｖ特性で、−20ボルト
以上と高く、膜の比抵抗が1013Ωcmのオーダであ
り、さらにスレツシヨルド電圧のヒステリシス巾
が10ボルト以上であつた。
The characteristics required for a gate oxide film are low leakage current, film specific resistance of 10 14 Ωcm or more, and low transistor threshold voltage, that is, no charge remains in the insulating film. Also, in terms of electrical characteristics, hysteresis width should be small. It has good step specific membrane properties and high membrane breakdown voltage. However, the oxide film produced by the conventional method has a high C-V characteristic of -20 volts or more using an N-type substrate, the specific resistance of the film is on the order of 10 13 Ωcm, and the hysteresis width of the threshold voltage is 10 volts. That's all.
そこで本発明は、上記欠点を改善し、高い膜比
抵抗、スレツシヨルド電圧が低く、ヒステリシス
電圧巾の少ない酸化膜を得ることを目的とする。 SUMMARY OF THE INVENTION An object of the present invention is to improve the above-mentioned drawbacks and obtain an oxide film with high film specific resistance, low threshold voltage, and small hysteresis voltage width.
本発明は、上記欠点を解決し、TFT用酸化膜
として必要な特性を得るために、一酸化窒素ガス
とシランガスを混合してグロー放電することによ
つて、酸化膜を作成した。
In the present invention, in order to solve the above-mentioned drawbacks and obtain the characteristics necessary for an oxide film for TFT, an oxide film was created by mixing nitrogen monoxide gas and silane gas and subjecting the mixture to glow discharge.
上記のように、一酸化窒素とシランガスを混合
してグロー放電法によつて作成した酸化膜は、膜
比抵抗1014Ωcm以上、スレツシヨルド電圧が膜厚
0.1ミクロンで−10ボルト以下、ヒステリシス電
圧巾が５ボルト以下、またブレークダウン電圧を
改善することができる。
As mentioned above, the oxide film created by the glow discharge method by mixing nitrogen monoxide and silane gas has a specific resistance of 10 14 Ωcm or more and a threshold voltage of
At 0.1 micron, the voltage is -10 volts or less, the hysteresis voltage width is 5 volts or less, and the breakdown voltage can be improved.
以下本発明によるTFTの製造方法を実施例に
したがつて詳細に説明する。
The method for manufacturing a TFT according to the present invention will be described in detail below using examples.
第１図ａ〜ｄは本発明によるTFTの製造方法
を各工程順に示す。第１図ａは、表面が平坦な基
板１上にゲート電極２を形成したTFTの縦断面
図である。基板はガラス、セラミツクス、プラス
チツク等を使用することができる。ゲート電極
は、導電性メタルから成り、Cr／Auを約1000Å
スパツターにより形成し、次にパターニングを行
つてゲート電極とした。第１図ｂは、ゲート酸化
膜３と半導体膜をプラズマCVDによつて連続的
に形成し、次にパターニングを行つて半導体層４
とした。ゲート酸化膜はプラズマCVD装置によ
つて、一酸化窒素とシランの混合ガスを圧力
0.5torr Power 30watt、周波数13.5MHZの条件
で10分間グロー放電デポジツシヨンを行い、膜厚
2000Åを得た。次に真空を破らずにシランガスの
グロー放電によつて膜厚3000Åの水素化アモルフ
アスシリコン半導体層を形成した。なお本発明に
よるTFT製造方法は、半導体層４として、水素
化アモルフアスシリコン半導体層を用いたが、こ
れをCVD法、蒸着法、あるいは、アニールによ
つて作成したポリシリコン半導体層を形成しても
よいことはもちろんである。第１図ｃはソース電
極５とドレーン電極６を形成した、TFTの縦断
面図を示す。電極は、Alをスパツターによつて
8000Å堆積し、次にパターニングを行つた。第１
図ｄは、TFTの保護膜として酸化膜７を形成し
たTFTの縦断面図である。酸化膜は本実施例で
は、プラズマCVD、グロー放電によつて8000Å
堆積した。 FIGS. 1a to 1d show the method for manufacturing a TFT according to the present invention in order of each step. FIG. 1a is a longitudinal sectional view of a TFT in which a gate electrode 2 is formed on a substrate 1 having a flat surface. The substrate can be made of glass, ceramics, plastic, etc. The gate electrode is made of conductive metal, with Cr/Au approximately 1000Å thick.
It was formed by sputtering and then patterned to form a gate electrode. In FIG. 1b, a gate oxide film 3 and a semiconductor film are successively formed by plasma CVD, and then patterning is performed to form a semiconductor layer 4.
And so. The gate oxide film is made using a plasma CVD device using a mixed gas of nitrogen monoxide and silane under pressure.
Glow discharge deposition was performed for 10 minutes under the conditions of 0.5torr power 30watt and frequency 13.5MHZ, and the film thickness was
Obtained 2000Å. Next, a hydrogenated amorphous silicon semiconductor layer with a thickness of 3000 Å was formed by glow discharge of silane gas without breaking the vacuum. Note that in the TFT manufacturing method according to the present invention, a hydrogenated amorphous silicon semiconductor layer is used as the semiconductor layer 4, but a polysilicon semiconductor layer formed by CVD, vapor deposition, or annealing may be formed on this. Of course it's a good thing. FIG. 1c shows a longitudinal cross-sectional view of a TFT in which a source electrode 5 and a drain electrode 6 are formed. The electrode is made by sputtering Al.
8000 Å was deposited and then patterned. 1st
FIG. d is a longitudinal cross-sectional view of a TFT in which an oxide film 7 is formed as a protective film of the TFT. In this example, the oxide film was formed to a thickness of 8000 Å by plasma CVD and glow discharge.
Deposited.
本発明による製造方法によつて作成したTFT
の特性は、スレツシヨルド電圧が５ボルト以下、
電気特性のヒステリシス、経時変化はまつたくみ
られなかつた。第２図は本発明による薄膜トラン
ジスタの製造方法にしたがつて作成したゲート絶
縁膜のＣ−Ｖ特性を示す。一酸化窒素とシランガ
スのグロー放電によつて、膜厚2000ÅＮ型シリコ
ン基板上にゲート酸化膜を堆積したときのスレツ
シヨルド電圧は、−８ボルト以下となつた。また、
酸化膜の比抵抗は1014Ωcm以上、耐圧は5MV／
cm以上であつた。 TFT manufactured by the manufacturing method according to the present invention
The characteristics are that the threshold voltage is 5 volts or less,
No hysteresis or time-dependent changes in electrical properties were observed. FIG. 2 shows the CV characteristics of a gate insulating film produced according to the method of manufacturing a thin film transistor according to the present invention. When a gate oxide film was deposited on an N-type silicon substrate with a film thickness of 2000 Å by glow discharge of nitrogen monoxide and silane gas, the threshold voltage was less than -8 volts. Also,
The specific resistance of the oxide film is 10 14 Ωcm or more, and the withstand voltage is 5MV/cm.
It was over cm.
以上述べてきたように、本発明による薄膜トラ
ンジスタの製造方法によれば、ゲート絶縁膜を一
酸化窒素とシランガスの混合ガスのグロー放電に
よつて作成することにより、トランジスタのスレ
ツシヨルド電圧が低下し、ヒステリシス、経時変
化がまつたくなく、酸化膜の比抵抗が高いため、
トランジスタのリーク電流を低レベルにおさえる
ことができるというすぐれた効果がある。
As described above, according to the method for manufacturing a thin film transistor according to the present invention, by forming the gate insulating film by glow discharge of a mixed gas of nitrogen monoxide and silane gas, the threshold voltage of the transistor is lowered and hysteresis is reduced. , because it does not change easily over time and the specific resistance of the oxide film is high,
This has the excellent effect of suppressing transistor leakage current to a low level.
第１図ａ〜ｄは、本発明による薄膜トランジス
タの製造方法を工程順に示した薄膜トランジスタ
の縦断面図であり、第１図ａは基板にゲート電極
を形成した縦断面図、第１図ｂはゲート酸化膜と
半導体層を形成した縦断面図、第１図ｃはソース
電極とドレーン電極を形成した縦断面図、第１図
ｄは保護膜を形成した縦断面図である。第２図
は、本発明の製造方法に従つて作成したゲート酸
化膜のＣ−Ｖ特性グラフである。
１……基板、２……ゲート電極、３……酸化
膜、４……半導体膜、５……ソース電極。
1A to 1D are vertical cross-sectional views of a thin film transistor showing the manufacturing method of a thin film transistor according to the present invention in the order of steps, FIG. 1A is a vertical cross-section of a gate electrode formed on a substrate, and FIG. FIG. 1c is a vertical cross-sectional view showing an oxide film and a semiconductor layer formed, FIG. 1c is a vertical cross-sectional view showing a source electrode and drain electrode formed, and FIG. 1d is a vertical cross-sectional view showing a protective film formed. FIG. 2 is a CV characteristic graph of a gate oxide film produced according to the manufacturing method of the present invention. DESCRIPTION OF SYMBOLS 1...Substrate, 2...Gate electrode, 3...Oxide film, 4...Semiconductor film, 5...Source electrode.
Claims (1)
体膜、ソース電極、ドレーン電極からなる薄膜ト
ランジスタの製造方法において、前記酸化膜は、
一酸化窒素とシランとを含有する混合ガスのグロ
ー放電によつて形成したことを特徴とする薄膜ト
ランジスタの製造方法。1. In a method for manufacturing a thin film transistor comprising a gate electrode, an oxide film, a semiconductor film, a source electrode, and a drain electrode formed on a substrate, the oxide film comprises:
A method for manufacturing a thin film transistor, characterized in that the thin film transistor is formed by glow discharge of a mixed gas containing nitrogen monoxide and silane.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59194308A JPS6171674A (en) | 1984-09-17 | 1984-09-17 | Manufacture of thin film transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59194308A JPS6171674A (en) | 1984-09-17 | 1984-09-17 | Manufacture of thin film transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6171674A JPS6171674A (en) | 1986-04-12 |
| JPH0464190B2 true JPH0464190B2 (en) | 1992-10-14 |
Family
ID=16322441
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59194308A Granted JPS6171674A (en) | 1984-09-17 | 1984-09-17 | Manufacture of thin film transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6171674A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2589327B2 (en) * | 1987-11-14 | 1997-03-12 | 株式会社リコー | Method for manufacturing thin film transistor |
-
1984
- 1984-09-17 JP JP59194308A patent/JPS6171674A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6171674A (en) | 1986-04-12 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term | ||
| S533 | Written request for registration of change of name |
Free format text: JAPANESE INTERMEDIATE CODE: R313533 |
|
| R370 | Written measure of declining of transfer procedure |
Free format text: JAPANESE INTERMEDIATE CODE: R370 |