JPH0659017B2 - Logarithmic IF amplifier circuit - Google Patents
Logarithmic IF amplifier circuitInfo
- Publication number
- JPH0659017B2 JPH0659017B2 JP61140511A JP14051186A JPH0659017B2 JP H0659017 B2 JPH0659017 B2 JP H0659017B2 JP 61140511 A JP61140511 A JP 61140511A JP 14051186 A JP14051186 A JP 14051186A JP H0659017 B2 JPH0659017 B2 JP H0659017B2
- Authority
- JP
- Japan
- Prior art keywords
- output
- differential
- transistors
- circuit
- differential amplifier
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Landscapes
- Superheterodyne Receivers (AREA)
- Monitoring And Testing Of Transmission In General (AREA)
- Tone Control, Compression And Expansion, Limiting Amplitude (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は受信機のＩＦ増幅器に関し、特に受信電界検出
の方法に関する。The present invention relates to an IF amplifier of a receiver, and more particularly to a method for detecting a received electric field.
従来電界検出機能を有するＩＦ増幅機の構成は第５図に
示すように多段の増幅器（トランジスタＱ１〜Ｑ１０か
ら成る第１段；Ｑ１１〜Ｑ１９から成る第２段；Ｑ２０
〜Ｑ２７から成る第３段）の各段の出力をコンデンサ
（Ｃ８，Ｃ９，Ｃ１０）を介して整流し、夫々の段の整
流電流波形を加算して電界レベル情報を出していた。As shown in FIG. 5, a conventional IF amplifier having an electric field detecting function has a multistage amplifier (first stage including transistors Q1 to Q10; second stage including Q11 to Q19; Q20).
The output of each stage (third stage consisting of Q27) is rectified through capacitors (C8, C9, C10), and the rectified current waveforms of the respective stages are added to output electric field level information.
上述した従来の電界検出機能を有するＩＦ増幅器では交
流信号の整流はダイオード（Ｑ28，Ｑ29，Ｑ30；Ｑ32，
Ｑ33，Ｑ34；Ｑ35，Ｑ36，Ｑ37）を使って行っているの
で特に温度特性が悪くなり、温度特性を補償するために
は、回路が複雑になるという欠点がある。また整流器は
上述のようにダイオードを用いる半波整流方式であるこ
とより、各々のコンデンサ（Ｃ８，Ｃ９，Ｃ１０）が必
要であり、ＩＦの周波数を下げると大きなコンデンサが
必要となる。In the conventional IF amplifier having the electric field detection function described above, the rectification of the AC signal is performed by the diode (Q28, Q29, Q30; Q32,
Since Q33, Q34; Q35, Q36, Q37) are used, the temperature characteristic becomes particularly bad, and there is a drawback that the circuit becomes complicated to compensate the temperature characteristic. Further, since the rectifier is a half-wave rectification method using diodes as described above, each capacitor (C8, C9, C10) is required, and a large capacitor is required when the IF frequency is lowered.
従って上述のコンデンサをＩＣ内に形成する場合にはチ
ップサイズが大きくなる。またコンデンサを外付けにし
てチップサイズを小さくするためには各段毎に外付けコ
ンデンサが必要となるため外付けコンデンサ用の端子が
増えてＩＣ化には不利であった。Therefore, when the above-mentioned capacitor is formed in the IC, the chip size becomes large. Further, in order to reduce the chip size by externally mounting a capacitor, an external capacitor is required for each stage, and the number of terminals for the external capacitor is increased, which is a disadvantage for IC implementation.
一方入力信号検出電圧の対数特性に対する偏差を小さく
するためには一般的に上述した差動増幅器１段当りの利
得を下げてかつ多段化する必要があり、コンデンサも整
流器の段数だけ必要となる欠点があった。On the other hand, in order to reduce the deviation of the input signal detection voltage with respect to the logarithmic characteristic, it is generally necessary to reduce the gain per one stage of the differential amplifier and increase the number of stages. was there.
本発明の対数ＩＦ増幅回路は差動増幅器の出力が順次次
段の入力となる様に接続されるｎ段の差動増幅器とそれ
ぞれの差動増幅器の入出力に接続されるエミッタサイズ
の比がｌ：１（ｌ＞１）の差動対がｎ＋１個とそれぞれ
の差動対のエミッタの面積係数が１のトランジスタのコ
レクタ電流を加算する加算回路を有している。In the logarithmic IF amplifier circuit of the present invention, the ratio of the n-stage differential amplifier connected so that the output of the differential amplifier becomes the input of the next stage in sequence and the emitter size connected to the input / output of each differential amplifier is It has an adder circuit for adding the collector currents of the transistors in which the area coefficient of the emitter of each differential pair is 1 and the number of differential pairs of 1: 1 (l> 1) is 1.
次に本発明について図面を参照して説明する。 Next, the present invention will be described with reference to the drawings.
第１図は本発明の一実施例を示す回路図である。FIG. 1 is a circuit diagram showing an embodiment of the present invention.
第１段から第ｎ段の差動増幅器は入力信号ＶINを順次増
幅してＶOUTとして出力する。The first to nth differential amplifiers sequentially amplify the input signal V IN and output it as V OUT .
一方エミッタサイズｌ：１（ｌ＞１）のトランジスタ対
で構成される第１から第（ｎ＋１）の差動対は各段の差
動増幅器の入力信号又は出力信号を入力としている。こ
こでトランジスタＱ14，Ｑ24，…，Ｑn4，Ｑ(n+1)4はエ
ミッタサイズがls0でありトランジスタＱ13,Ｑ23,…，
Ｑn3，Ｑ(n+1)3はエミッタサイズＳ０である。On the other hand, the first to (n + 1) th differential pairs formed by transistor pairs having an emitter size of 1: 1 (l> 1) receive the input signal or output signal of the differential amplifier of each stage. Here, the transistors Q 14 , Q 24 , ..., Q n4 , Q (n + 1) 4 have an emitter size of ls 0 , and the transistors Q 13 , Q 23 ,.
Q n3 and Q (n + 1) 3 are the emitter size S 0 .
トランジスタＱ13,Ｑ23,…，Ｑn3，Ｑ(n+1)3のおのおの
のコレクタ電流はトランジスタＱ01，Ｑ02から成る加算
回路で加算され抵抗Ｒ01で電圧ＶLOGに変換され出力さ
れる。The collector current of each of the transistors Q 13 , Q 23 , ..., Q n3 , Q (n + 1) 3 is added by the adder circuit including the transistors Q 01 and Q 02 , converted into the voltage V LOG by the resistor R 01 , and output. It
ここでエミッタサイズがｌ：１（ｌ＞１）の差動対の動
作は例えば第ｎの差動対について考えてみると、第（ｎ
−１）段の差動増幅器の出力をＶn-1とすると次のよう
になる。Here, regarding the operation of the differential pair having an emitter size of 1: 1 (l> 1), for example, when considering the nth differential pair,
Assuming that the output of the -1) th stage differential amplifier is Vn -1 , the following is obtained.
ここでＶBEn3，ＶBEn4はそれぞれトランジスタＱn3，Ｑ
n4のベースエミッタ間電圧であり、ＩCn3，ＩCn4はそれ
ぞれトランジスタＱn3，Ｑn4のコレクタ電流であり、Ｉ
Sn3，ＩSn4はそれぞれトランジスタＱn3，Ｑn4の飽和電
流である。またＶTは次式で示される。 Here, V BEn3 and V BEn4 are transistors Q n3 and Q, respectively.
n4 is a base-emitter voltage, and I Cn3 and I Cn4 are collector currents of the transistors Q n3 and Q n4 , respectively.
Sn3 and I Sn4 are the saturation currents of the transistors Q n3 and Q n4 , respectively. V T is expressed by the following equation.
ＶT＝KT／ｑ ここで 一方トランジスタの増幅率をαとすると またトランジスタＱn3とＱn4のエミッタサイズが１：ｌ
であることより ＩSn3／ＩSn4＝1/l 上式により次式が求まる。V T = KT / q where On the other hand, if the amplification factor of the transistor is α The emitter size of the transistors Q n3 and Q n4 is 1: l.
Therefore, I Sn3 / I Sn4 = 1 / l The following equation is obtained from the above equation.
式でα＝１，ｌ＝exp２＝７．３８９としてICn3の入
力信号レベルＶn-1に対する特性を第２図に示す。 FIG. 2 shows the characteristic of I Cn3 with respect to the input signal level V n-1 when α = 1, l = exp2 = 7.389 in the equation.
第２図からわかるようにＩCn3は入力信号に対して半波
整流特性と飽和特性を持っている。As can be seen from FIG. 2, I Cn3 has a half-wave rectification characteristic and a saturation characteristic with respect to the input signal.
従って第１図においては各段の差動増幅器は利得を持つ
から各差動対への入力レベルは第(n＋1)から順次小さく
なっている。すなわち入力信号ＶINの増加に従って（ｎ
＋１）の差動対を構成するトランジスタＱ(n+1)3のコレ
クタ電流ＩCn+1から順次飽和して行き、最後に第１の差
動対を構成するトランジスタＱ13のコレクタ電流ＩC13
が飽和する。従ってトランジスタＱ13，Ｑ23，…，
Ｑn3，Ｑ(n+1)3のそれぞれのコレクタ電流を加算し、平
滑化すれば入力信号レベルＶINに対して折れ線近似され
た対数特性が得られる。Therefore, in FIG. 1, since the differential amplifier of each stage has a gain, the input level to each differential pair is gradually decreased from the (n + 1) th. That is, as the input signal V IN increases (n
+1) The collector current I Cn + 1 of the transistor Q (n + 1) 3 forming the differential pair is sequentially saturated, and finally the collector current I C13 of the transistor Q 13 forming the first differential pair.
Is saturated. Therefore, the transistors Q 13 , Q 23 , ...,
If the respective collector currents of Q n3 and Q (n + 1) 3 are added and smoothed, a logarithmic characteristic approximated to a polygonal line with respect to the input signal level V IN can be obtained.
ここでトランジスタＱi3のコレクタ電流をＩCi3とする
と加算回路出力電流ＩＯはエミッタの面積係数１のトラ
ンジスタのコレクタ電流の総和と等しくなり で示される。ここでＩＯの直流成分を とすると と示される。今、ｌ＝７．３８９として各段の差動増幅
器の利得をＧｏdBとすると の特性は第３図に示される。このときに で示され、出力電圧ＶLOGは入力信号レベルＶINに対し
て対数特性を持つことがわかる。Here, if the collector current of the transistor Q i3 is I Ci3 , the adder circuit output current I O becomes equal to the sum of the collector currents of the transistors having an emitter area coefficient of 1. Indicated by. Here, the DC component of I O And Is shown. Now, when the gain of the differential amplifier of each stage as l = 7.389 and G o dB The characteristics of are shown in FIG. At this time It can be seen that the output voltage V LOG has a logarithmic characteristic with respect to the input signal level V IN .
また第１図に示す回路では電流電圧を低く出来電源電圧
が１．５Ｖ程度で回路を実現できる。一方第４図に示す
ように加算回路を変更すれば電源電圧は一層低く出来電
源電圧１．０Ｖでも第４図の回路を実現出来る。このと
きに電源電圧をＶCCとすると となる。Further, in the circuit shown in FIG. 1, the current voltage can be lowered and the circuit can be realized with a power supply voltage of about 1.5V. On the other hand, if the adder circuit is changed as shown in FIG. 4, the power supply voltage can be further reduced and the circuit of FIG. 4 can be realized with a power supply voltage of 1.0V. At this time, if the power supply voltage is V CC Becomes
また第３図からわかるように対数特性のダイナミックレ
ンジも差動増幅器の段数を上げることで大きく出来、対
数特性の直線性も差動増幅器の利得を設定することで改
善できる。第１図および第３図に示す回路からわかるよ
うに回路を差動構成としていることにより従来より良く
知られた簡単な温度補償を各定電流源に施すことにより
良好な温度安定度を持つ回路が得られる。Further, as can be seen from FIG. 3, the dynamic range of the logarithmic characteristic can be increased by increasing the number of stages of the differential amplifier, and the linearity of the logarithmic characteristic can be improved by setting the gain of the differential amplifier. As can be seen from the circuits shown in FIGS. 1 and 3, a circuit having a good temperature stability by performing a simple temperature compensation, which is well known in the art, on each constant current source by making the circuit a differential configuration. Is obtained.
また整流器は出力で１個のコンデンサＣ01を必要とする
のみでありＶLOGの出力端子を介してＩＣ外部に外付け
できるのでＩＦ周波数を下げられる。Further, the rectifier only needs one capacitor C 01 at the output and can be externally attached to the outside of the IC through the output terminal of V LOG , so that the IF frequency can be lowered.
以上説明したように本発明によれば低いＩＦ周波数から
動作し、電界検出電圧の温度特性に優れ、かつ低い電源
電圧で実現でき、しかも小さな回路規模で実現出来、ま
たコンデンサを省略出来て、ＩＣ化のメリットが大き
い。As described above, according to the present invention, it operates from a low IF frequency, has excellent temperature characteristics of the electric field detection voltage, can be realized with a low power supply voltage, can be realized with a small circuit scale, and a capacitor can be omitted. There is a large merit of conversion.
第１図は本発明の一実施例を示す回路図である。第２図
は第１図における第ｎの差動対の動作を示す図である。
第３図は第１図に示す回路の特性を示す図である。第４
図は本発明の他の実施例を示す回路図である。第５図は
従来回路を示す。FIG. 1 is a circuit diagram showing an embodiment of the present invention. FIG. 2 is a diagram showing the operation of the n-th differential pair in FIG.
FIG. 3 is a diagram showing characteristics of the circuit shown in FIG. Fourth
The drawing is a circuit diagram showing another embodiment of the present invention. FIG. 5 shows a conventional circuit.
Claims (1)
幅器の出力が順次次段の入力となる様に接続されたＩＦ
増幅器を構成し、ｎ段の前記差動増幅器のそれぞれの入
力と第ｎ段目の前記差動増幅器の出力とに、エミッタサ
イズが所定の比をなす第１及び第２のトランジスタを有
する差動対が（ｎ＋１）個接続され、前記差動対の前記
第１のトランジスタの出力電流を加算することを特徴と
する対数ＩＦ増幅回路。1. An IF connected in such a manner that there are n stages of differential amplifiers, and the output of each differential amplifier is sequentially input to the next stage.
A differential amplifier having a first transistor and a second transistor having an emitter size of a predetermined ratio for each input of the differential amplifier of the nth stage and the output of the differential amplifier of the nth stage. A logarithmic IF amplifier circuit, wherein (n + 1) pairs are connected and the output currents of the first transistors of the differential pair are added.
Priority Applications (8)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61140511A JPH0659017B2 (en) | 1986-06-16 | 1986-06-16 | Logarithmic IF amplifier circuit |
| US07/057,145 US4794342A (en) | 1986-06-04 | 1987-06-03 | Intermediate frequency amplification circuit capable of detecting a field strength with low electric power |
| CA000538715A CA1258499A (en) | 1986-06-04 | 1987-06-03 | Intermediate frequency amplification circuit capable of detecting a field strength with low electric power |
| AU73814/87A AU589094B2 (en) | 1986-06-04 | 1987-06-04 | Intermediate frequency amplification circuit capable of detecting a field strength with low elecric power |
| EP87108099A EP0248428B1 (en) | 1986-06-04 | 1987-06-04 | Intermediate frequency amplification circuit capable of detecting a field strength with low electric power |
| KR1019870005649A KR910001372B1 (en) | 1986-06-04 | 1987-06-04 | Inter-frequency amplifier |
| DE8787108099T DE3783655T2 (en) | 1986-06-04 | 1987-06-04 | INTERMEDIATE FREQUENCY AMPLIFIER CIRCUIT OF SMALL ELECTRICAL POWER FOR DETERMINING A FIELD STRENGTH. |
| HK1031/93A HK103193A (en) | 1986-06-04 | 1993-09-30 | Intermediate frequency amplification circuit capable of detecting a field strength with low electric power |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61140511A JPH0659017B2 (en) | 1986-06-16 | 1986-06-16 | Logarithmic IF amplifier circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62296610A JPS62296610A (en) | 1987-12-23 |
| JPH0659017B2 true JPH0659017B2 (en) | 1994-08-03 |
Family
ID=15270348
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61140511A Expired - Fee Related JPH0659017B2 (en) | 1986-06-04 | 1986-06-16 | Logarithmic IF amplifier circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0659017B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3036121B2 (en) * | 1991-05-30 | 2000-04-24 | 日本電気株式会社 | Pseudo-log IF amplifier |
| US5345185A (en) * | 1992-04-14 | 1994-09-06 | Analog Devices, Inc. | Logarithmic amplifier gain stage |
-
1986
- 1986-06-16 JP JP61140511A patent/JPH0659017B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPS62296610A (en) | 1987-12-23 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |