JPH0650779B2 - Thin film transistor device and manufacturing method thereof - Google Patents
Thin film transistor device and manufacturing method thereofInfo
- Publication number
- JPH0650779B2 JPH0650779B2 JP60212965A JP21296585A JPH0650779B2 JP H0650779 B2 JPH0650779 B2 JP H0650779B2 JP 60212965 A JP60212965 A JP 60212965A JP 21296585 A JP21296585 A JP 21296585A JP H0650779 B2 JPH0650779 B2 JP H0650779B2
- Authority
- JP
- Japan
- Prior art keywords
- thin film
- resistance semiconductor
- semiconductor thin
- region
- electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1251—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs comprising TFTs having a different architecture, e.g. top- and bottom gate TFTs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、非晶質，多結晶または単結晶といった材質の
異なる半導体薄膜をチャンネル領域にもつ２種の薄膜ト
ランジスタ（ＴＦＴ）を搭載したＴＦＴ装置の構造とそ
の製造方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Industrial field of application] The present invention relates to a TFT device equipped with two types of thin film transistors (TFTs) having semiconductor thin films of different materials such as amorphous, polycrystalline or single crystal in a channel region. And the manufacturing method thereof.
絶縁基板上のＴＦＴ装置で、粒径の大きい多結晶または
単結晶の第１高抵抗半導体薄膜を第１チャンネル領域に
もつ第１ＴＦＴと、非晶質または多結晶の第２高抵抗半
導体薄膜を第２チャンネル領域にもつ逆スタガー型の第
２ＴＦＴとを搭載している。第１ＴＦＴは、基板側から
ビームアニールで形成された第１チャンネル領域、第２
ゲート絶縁膜と同じ第１ゲート絶縁膜、第１ゲート電極
から成る。第１ゲート電極は、金属膜の下に第２低抵抗
薄膜、第２高抵抗薄膜をもつ構造となっている。第２Ｔ
ＦＴは、基板側から第１導電膜による第２ゲート電極、
第２ゲート絶縁膜、第２チャンネル領域、第２低抵抗半
導体薄膜による第２ソース及びドレイン領域、金属膜に
よる第２ソース及びドレイン電極を有している。In a TFT device on an insulating substrate, a first TFT having a polycrystalline or single crystal first high-resistance semiconductor thin film with a large grain size in a first channel region and an amorphous or polycrystalline second high-resistance semiconductor thin film are provided. It is equipped with an inverted stagger type second TFT having two channel regions. The first TFT has a first channel region formed by beam annealing from the substrate side, a second channel
The first gate insulating film and the first gate electrode are the same as the gate insulating film. The first gate electrode has a structure having a second low resistance thin film and a second high resistance thin film under the metal film. Second T
FT is a second gate electrode formed of the first conductive film from the substrate side,
It has a second gate insulating film, a second channel region, a second source and drain region made of a second low resistance semiconductor thin film, and a second source and drain electrode made of a metal film.
非晶質シリコン（ａ−Ｓｉ）を用いたＴＦＴは液晶表示
装置等に応用されつつあるが、キャリア移動度が低いた
めに高速動作に限界があり、応用が限られていた。その
ため、高速動作部分にはモノリシックＩＣを用い、ａ−
ＳｉＴＦＴ装置に接続していた。しかし、相互接続の信
頼性やコストに問題がある。それを解決するためにａ−
ＳｉＴＦＴと同一基板上に、レーザ光や電子線等のエネ
ルギービームによるアニールでａ−Ｓｉを結晶化したＴ
ＦＴを混載させる方法がある。A TFT using amorphous silicon (a-Si) is being applied to a liquid crystal display device or the like, but its high speed operation is limited due to its low carrier mobility, and its application is limited. Therefore, a monolithic IC is used for the high-speed operation part, and a-
It was connected to the SiTFT device. However, there are problems with interconnect reliability and cost. A-
On the same substrate as the SiTFT, a-Si was crystallized by annealing with an energy beam such as a laser beam or an electron beam.
There is a method to mix FT.
第２図に、その一構造例を示す。ＴＦＴ２はａ−Ｓｉ膜
を用い、ＴＦＴ１はビームアニールされたＳｉ膜を用い
たＴＦＴである。FIG. 2 shows an example of the structure. The TFT 2 is a TFT using an a-Si film, and the TFT 1 is a TFT using a beam annealed Si film.
ＴＦＴ１はａ−Ｓｉ ＴＦＴで最も実績のある逆スタガ
ー構造をもち、第１ゲート電極１１１、第１ゲート絶縁
膜１１２、第１高抵抗半導体薄膜による第１チャンネル
領域１１３、第１低抵抗半導体薄膜による第１ソース及
びドレイン領域１１４，１１５、金属膜による第１ソー
ス及びドレイン電極１２４，１２５から成る。第１高抵
抗半導体薄膜は第２高抵抗薄膜をビームアニールしたも
のである。一方、ＴＦＴ２も同様に、絶縁基板１上に第
２ゲート電極１１、第２ゲート絶縁膜１２、第２高抵抗
半導体薄膜（a-Si膜）から成る第２チャンネル領域１
３、第２低抵抗半導体薄膜（例えばn+a-Si膜）による第
２ソース及びドレイン領域１４，１５、金属膜による第
２ソース及びドレイン電極２４，２５から成り、必要に
応じ絶縁膜９で被われている。この例の構造は各膜をＴ
ＦＴ１及び２で共通に使える利点があるが、次の問題点
がある。(1)ビームアニールの際、第１高抵抗薄膜の下
に第１ゲート電極１１１があるので、ビームの反射，熱
放散の不均一によってアニールが均一にできない。(2)
第１ソース及びドレイン領域１１４，１１５に第２低抵
抗薄膜と同じ例えばn+a-Siを使うことになり、抵抗率が
大きくＴＦＴ１のオン電流がとれない。(3)これを避け
るため、第１低抵抗薄膜をビームアニールで結晶化でき
るが、やはりアニールの不均一性が問題である。(4)第
１及び第２高抵抗薄膜の厚みは同じであるため、ＴＦＴ
１及び２で最適の厚みを選べない。The TFT 1 has an inverted staggered structure, which is the most proven a-Si TFT, and includes a first gate electrode 111, a first gate insulating film 112, a first channel region 113 made of a first high resistance semiconductor thin film, and a first low resistance semiconductor thin film. The first source / drain regions 114 and 115 and the first source / drain electrodes 124 and 125 made of a metal film. The first high resistance semiconductor thin film is obtained by beam annealing the second high resistance thin film. On the other hand, the TFT 2 similarly includes the second channel region 1 including the second gate electrode 11, the second gate insulating film 12, and the second high resistance semiconductor thin film (a-Si film) on the insulating substrate 1.
3, second source and drain regions 14 and 15 made of a second low resistance semiconductor thin film (for example, n + a-Si film), second source and drain electrodes 24 and 25 made of a metal film, and an insulating film 9 if necessary. Covered. In the structure of this example, each film is
Although it has an advantage that it can be commonly used in FT1 and FT2, it has the following problems. (1) During the beam annealing, the first gate electrode 111 is located under the first high-resistance thin film, so that the annealing cannot be made uniform due to nonuniform beam reflection and heat dissipation. (2)
For example, n + a-Si, which is the same as the second low resistance thin film, is used for the first source and drain regions 114 and 115, and thus the resistivity is large and the ON current of the TFT 1 cannot be obtained. (3) In order to avoid this, the first low resistance thin film can be crystallized by beam annealing, but the nonuniformity of annealing is still a problem. (4) Since the first and second high resistance thin films have the same thickness, the TFT
The optimum thickness cannot be selected for 1 and 2.
本発明は如上の問題に鑑みなされ、逆スタガー型ＴＦＴ
と混在しやすいビームアニールＴＦＴをもつＴＦＴ装置
の構造と製造方法を提供するものである。また、それぞ
れのＴＦＴのチャンネル領域の厚みを自由に選択できる
構造を提供し、それぞれが充分な特性を持つ様にするも
のである。The present invention has been made in view of the above problems, and is an inverted stagger type TFT.
The present invention provides a structure and a manufacturing method of a TFT device having a beam annealed TFT that easily mixes with. In addition, a structure in which the thickness of the channel region of each TFT can be freely selected is provided so that each has sufficient characteristics.
第１ＴＦＴはビームアニールされた第１チャンネル領域
をもち、第２ＴＦＴは逆スタガー型ＴＦＴとする。The first TFT has a beam-annealed first channel region, and the second TFT is an inverted stagger type TFT.
第１ＴＦＴは、基板側から第１高抵抗半導体薄膜による
第１チャンネル領域とその両端に接する第１ソース及び
ドレイン領域と、両領域に接する第１導電膜による第１
ソース及びドレイン電極と、第１ゲート絶縁膜と、第１
ゲート電極を有する。第１ゲート電極は、第２高抵抗及
び低抵抗半導体薄膜と金属膜の多層膜から成っている。The first TFT includes a first channel region formed of the first high-resistance semiconductor thin film, first source and drain regions in contact with both ends thereof, and a first conductive film in contact with both regions from the substrate side.
Source and drain electrodes, a first gate insulating film, a first
It has a gate electrode. The first gate electrode is composed of a multilayer film including a second high resistance and low resistance semiconductor thin film and a metal film.
第２ＴＦＴは第２ゲート電極が第１導電膜で形成され、
第２ゲート絶縁膜は第１ゲート絶縁膜と同一で、その上
に第２高抵抗半導体薄膜による第２チャンネル領域、第
２低抵抗半導体薄膜による第２ソース及びドレイン領
域、金属膜による第２ソース及びドレイン電極をもって
いる。In the second TFT, the second gate electrode is formed of the first conductive film,
The second gate insulating film is the same as the first gate insulating film, and has a second channel region formed of a second high resistance semiconductor thin film, a second source and drain region formed of a second low resistance semiconductor thin film, and a second source formed of a metal film. And has a drain electrode.
上記の構造は、第１及び第２高抵抗薄膜はそれぞれ独立
に堆積できるので、膜厚は自由に選択できる。また、第
２ＴＦＴでは第２ゲート絶縁膜、第２高抵抗薄膜、第２
低抵抗薄膜は連続して大気に触れず堆積できるので、界
面の汚染や損傷による特性の劣化やコンタクト不良がな
く、逆スタガー型の長所をそのままもっている。第１Ｔ
ＦＴでは、第１チャンネル領域が基板直上にあるので、
ビームアニールしやすく均一性もよい。さらに、第１ゲ
ート絶縁膜と第１ゲート電極の一部である第２高抵抗薄
膜は連続堆積でき、界面の不安定性が少ない。第２高抵
抗薄膜は抵抗率が充分高いので、むしろゲート絶縁膜の
一部としても働くが、厚みを充分薄くでき誘電率も高い
ため第１ＴＦＴの特性上問題は少ない。In the above structure, the first and second high resistance thin films can be independently deposited, so that the film thickness can be freely selected. In the second TFT, the second gate insulating film, the second high resistance thin film, the second
Since the low resistance thin film can be continuously deposited without exposure to the atmosphere, there is no deterioration of the characteristics due to interface contamination or damage and contact failure, and the advantages of the inverted stagger type are retained. 1st T
In FT, since the first channel region is directly above the substrate,
Beam annealing is easy and the uniformity is good. Further, the first gate insulating film and the second high resistance thin film which is a part of the first gate electrode can be continuously deposited, and the instability of the interface is small. Since the second high resistance thin film has a sufficiently high resistivity, it rather acts as a part of the gate insulating film, but since the thickness is sufficiently thin and the dielectric constant is high, there is little problem in the characteristics of the first TFT.
以下に図面を用いて本発明を詳述する。 The present invention will be described in detail below with reference to the drawings.
(a)実施例１ＴＦＴ装置断面図（第１図） 第１図は本発明によるＴＦＴ装置の断面構造例である。
ガラス，石英，絶縁膜コートされたＳｉ等の絶縁基板１
上に第１ＴＦＴ（ＴＦＴ１）と第２ＴＦＴ（ＴＦＴ２）
が形成されている。(a) Example 1 Cross-sectional view of TFT device (FIG. 1) FIG. 1 is an example of a cross-sectional structure of a TFT device according to the present invention.
Insulating substrate 1 made of glass, quartz, Si coated with insulating film, etc.
First TFT (TFT1) and second TFT (TFT2) on top
Are formed.
ＴＦＴ１は、基板１上の第１高抵抗半導体薄膜による第
１チャンネル領域１１３、この両側に互いに離間して接
する第１低抵抗半導体薄膜による第１ソース及びドレイ
ン領域１１４，１１５、両領域１１４，１１５に接する
第１導電膜による第１ソース及びドレイン電極１２４，
１２５、第１チャンネル領域１１３上の第１ゲート絶縁
膜１１２、その上の第１ゲート電極１１１から成る。第
１ゲート電極１１１は、下から第２高抵抗半導体薄膜
６、第２低抵抗半導体薄膜７、金属膜８より成る多層膜
である。第１ソース及びドレイン電極１２４，１２５に
は必要に応じ、金属膜による第１ソース及びドレイン配
線１３４，１３５が設けられている。The TFT 1 includes a first channel region 113 formed of a first high resistance semiconductor thin film on the substrate 1, first source and drain regions 114 and 115 formed of first low resistance semiconductor thin films which are spaced apart and in contact with both sides of the first channel region 113, and both regions 114 and 115. The first source and drain electrodes 124, which are in contact with the first conductive film,
125, the first gate insulating film 112 on the first channel region 113, and the first gate electrode 111 thereon. The first gate electrode 111 is a multilayer film including a second high resistance semiconductor thin film 6, a second low resistance semiconductor thin film 7 and a metal film 8 from the bottom. First source and drain electrodes 124 and 125 are provided with first source and drain wirings 134 and 135 made of a metal film, if necessary.
一方、ＴＦＴ２は基板１上に第１導電膜による第２ゲー
ト電極１１、その上に第２ゲート絶縁膜１２、第２高抵
抗半導体薄膜による第２チャンネル領域１３、その両端
に互いに離間した第２低抵抗半導体薄膜による第２ソー
ス及びドレイン領域１４，１５、さらに金属膜による第
２ソース及びドレイン電極２４，２５から成る逆スタガ
ー構造を有している。On the other hand, the TFT 2 includes a second gate electrode 11 formed of a first conductive film on a substrate 1, a second gate insulating film 12 formed thereon, a second channel region 13 formed of a second high-resistance semiconductor thin film, and a second gate electrode 13 separated from each other at both ends. It has an inverted stagger structure including second source and drain regions 14 and 15 made of a low resistance semiconductor thin film and second source and drain electrodes 24 and 25 made of a metal film.
第２高抵抗薄膜は、例えば非晶質シリコン（a-Si：Ｈや
a-Si：Ｆなど）または多結晶Ｓｉから成り、第２低抵抗
薄膜はやはりＰやＢを添加されたa-Si：Ｈやa-Si：Ｆま
たは多結晶Ｓｉであり、典型的な厚みはそれぞれ１００
〜５００Å，５０〜５００Åである。一方、第１高抵抗
薄膜はa-Siや多結晶Ｓｉをレーザ光、電子線等のエネル
ギービームでアニールしたもので、粒径の大きい多結晶
Ｓｉまたは単結晶Ｓｉであり、ＴＦＴ１として必要とさ
れる特性に応じ不純物は添加されていないかもしくは微
量添加されている。第１低抵抗薄膜は第１高抵抗薄膜と
同様ビームアニールで形成された多結晶または単結晶Ｓ
ｉであり、ＰまたはＢ等の不純物が添加されている。第
１高抵抗薄膜はビームアニールされるのに最適は厚み１
０００Å〜１μｍをもち、第２高抵抗薄膜より厚い。The second high resistance thin film is, for example, amorphous silicon (a-Si: H or
a-Si: F, etc.) or polycrystalline Si, and the second low resistance thin film is also a-Si: H or a-Si: F or polycrystalline Si with P or B added, and has a typical thickness. Each is 100
˜500Å, 50-500Å. On the other hand, the first high resistance thin film is a-Si or polycrystalline Si annealed with an energy beam such as a laser beam or an electron beam, and is polycrystalline Si or single crystal Si having a large grain size, which is required for the TFT 1. Depending on the characteristics, impurities are not added or a trace amount is added. The first low-resistance thin film is a polycrystalline or single-crystal S formed by beam annealing like the first high-resistance thin film.
i, and impurities such as P or B are added. The optimum thickness of the first high resistance thin film is 1 for beam annealing.
It has a thickness of 000Å to 1 μm and is thicker than the second high resistance thin film.
第１導電膜には、Ｃｒ，Ｍｏ，Ｗ，Ｎｉ等の金属やその
シクサイド、またはＩＴＯ等の透明導電膜が使われる。
第１及び第２ゲート絶縁膜１１２，１２は同じ絶縁膜が
使われ、例えばプラズマＣＶＤ、光ＣＶＤ等によるＳｉ
Ｏｘ，ＳｉＮｘ等である。金属膜は、第１ソース及びド
レイン配線１３４，１３５、第１ゲート電極１１１の一
部、第２ソース及びドレイン電極２４，２５、さらに必
要に応じ第１ゲート電極１１１の配線や第２ゲート電極
１１の配線として用いられている。For the first conductive film, a metal such as Cr, Mo, W, or Ni, its side, or a transparent conductive film such as ITO is used.
The same insulating film is used for the first and second gate insulating films 112 and 12, and for example, Si formed by plasma CVD, photo CVD or the like is used.
Ox, SiNx, etc. The metal film includes the first source / drain wirings 134 and 135, a part of the first gate electrode 111, the second source / drain electrodes 24 and 25, and if necessary, the wiring of the first gate electrode 111 and the second gate electrode 11. Is used as the wiring.
(b)実施例２製造工程（第３図） 第３図には本発明によるＴＦＴ装置の製造工程例を示
す。(b) Example 2 Manufacturing Process (FIG. 3) FIG. 3 shows an example of manufacturing process of the TFT device according to the present invention.
第３図(a)は、絶縁基板１上に第１高抵抗半導体薄膜２
による第１チャンネル領域１１３と第１低抵抗半導体薄
膜３による第１ソース及びドレイン領域１１４，１１５
を形成し、島状領域として残した状態を示す。第１高抵
抗薄膜２は、a-Siや多結晶Ｓｉをレーザ光、電子線、ラ
ンプ光、ヒーター等のエネルギービームを照射アニール
して得られた粒径の大きい多結晶Ｓｉまたは多結晶Ｓｉ
である。第１高抵抗薄膜２を形成した後、イオン注入や
不純物含有半導体薄膜の堆積−選択エッチ−アニールな
どにより第１高抵抗薄膜２内に第１低抵抗薄膜３を設
け、第１ソース及びドレイン領域１１４，１１５とす
る。第１高抵抗薄膜２には、必要に応じビームアニール
前または後にイオン注入等で不純物が微量添加される。
第３図(b)は、第１導電膜４を堆積し、ＴＦＴ２のゲー
ト電極１１、ＴＦＴ１の第１ソース及びドレイン電極１
２４，１２５を選択エッチで形成した状態である。第１
ソース及びドレイン電極１２４，１２５は第１ソース及
びドレイン領域１１４，１１５の一部に接し、必要によ
り配線の一部もかねられる。第３図(c)は、ゲート絶縁
膜５、第２高抵抗半導体薄膜６、第２低抵抗半導体薄膜
７を連続堆積した状態である。これらの膜は、プラズマ
ＣＶＤ、光ＣＶＤ、減圧ＣＶＤ等で、望ましくは大気に
触れずに連続的に堆積される。第３図(d)は、ＴＦＴ２
の部分、またＴＦＴ１の第１ゲート電極となるべき部分
の第２高抵抗及び低抵抗薄膜６，７を残して他を除去
し、その後必要な部分にゲート絶縁膜５に対しコンタク
ト開孔を設けたものである。第３図(e)は、金属膜８を
堆積し、ＴＦＴ２の第２ソース及びドレイン領域２４，
２５、ＴＦＴ１の第１ゲート電極１１１の形状に選択エ
ッチ後、露光した第２低抵抗薄膜７を除去して完成した
状態を示す。金属膜８は、Ａｌ，Ａｕ等が用いられ、必
要により下地にＭｏ，Ｃｒ，Ｗ等の薄膜が挿入される。
第２低抵抗薄膜７の選択エッチは、第２高抵抗薄膜６に
対し選択性のあることが望ましく、Ｃｌを含むプラズマ
エッチ、反応性イオンエッチ、光励起エッチ等が用いら
れる。FIG. 3 (a) shows the first high-resistance semiconductor thin film 2 on the insulating substrate 1.
Of the first channel region 113 and the first source and drain regions 114 and 115 of the first low resistance semiconductor thin film 3.
Is formed and is left as an island region. The first high-resistance thin film 2 is made of polycrystalline Si or polycrystalline Si having a large grain size obtained by annealing a-Si or polycrystalline Si by irradiation with an energy beam such as a laser beam, an electron beam, a lamp beam, or a heater.
Is. After forming the first high resistance thin film 2, the first low resistance thin film 3 is provided in the first high resistance thin film 2 by ion implantation, deposition-selective etch-annealing of a semiconductor thin film containing impurities, and the first source and drain regions. 114 and 115. If necessary, a small amount of impurities are added to the first high-resistance thin film 2 by ion implantation or the like before or after the beam annealing.
FIG. 3 (b) shows the gate electrode 11 of the TFT 2 and the first source and drain electrodes 1 of the TFT 1 deposited with the first conductive film 4.
24 and 125 are formed by selective etching. First
The source and drain electrodes 124 and 125 are in contact with a part of the first source and drain regions 114 and 115, and can also serve as a part of wiring if necessary. FIG. 3C shows a state in which the gate insulating film 5, the second high resistance semiconductor thin film 6 and the second low resistance semiconductor thin film 7 are continuously deposited. These films are preferably deposited continuously without exposure to the atmosphere by plasma CVD, photo CVD, low pressure CVD, or the like. FIG. 3 (d) shows the TFT2.
And the second high resistance and low resistance thin films 6 and 7 of the portion to be the first gate electrode of the TFT 1 are removed, and the other portions are removed, and then a contact opening is provided to the gate insulating film 5 in a necessary portion. It is a thing. In FIG. 3 (e), the metal film 8 is deposited and the second source and drain regions 24 of the TFT 2 are formed.
25, a state in which the exposed second low resistance thin film 7 is removed after selective etching is performed on the shape of the first gate electrode 111 of the TFT 1 is shown. The metal film 8 is made of Al, Au, or the like, and if necessary, a thin film of Mo, Cr, W, or the like is inserted in the base.
The selective etching of the second low resistance thin film 7 is preferably selective with respect to the second high resistance thin film 6, and plasma etching including Cl, reactive ion etching, photoexcitation etching or the like is used.
(c)実施例３製造工程（第４図） 第４図には、本発明を液晶表示用ＴＦＴ基板に適用した
製造工程例を示す。この場合、ＴＦＴ２は各画素のスイ
ッチとして、ＴＦＴ１は周辺回路用高速ＴＦＴとして使
用される。(c) Example 3 Manufacturing Process (FIG. 4) FIG. 4 shows an example of a manufacturing process in which the present invention is applied to a liquid crystal display TFT substrate. In this case, the TFT 2 is used as a switch for each pixel, and the TFT 1 is used as a high speed TFT for peripheral circuits.
第４図(a)は、第３図(b)と同様、ＴＦＴ１の第１チャン
ネル領域１１３、第１ソース及びドレイン領域１１４，
１１５を形成した後、第１導電膜４で第１ソース及びド
レイン領域１２４，１２５及びＴＦＴ２の第２ゲート電
極１１と画素電極１６を形成したものである。この例で
は、第１導電膜４にＩＴＯ等の透明導電膜４１とＭｏ，
Ｃｒ，Ｗ，Ｎｉ等の金属層４２の多層膜を用いている
が、透明導電膜４１のみでもよい。第４図(b)は、ゲー
ト絶縁膜５、第２高抵抗薄膜６、第２低抵抗薄膜７を連
続堆積した状態を示す。第４図(c)は、第４図(b)で堆積
した３層膜の第１ゲート電極部分及び第２チャンネル領
域１３部分を少なく共残して、他を除去した状態を示
す。この例では、第１ソース及びドレイン電極１２４，
１２５上及び画素電極１６上を少なく共開孔している。
ゲート絶縁膜５も、その上の第２高抵抗及び低抵抗薄膜
６，７の同一形状にエッチするのでマスク枚数が減少で
きる。第４図(d)は、金属膜８を堆積・選択エッチして
第２ソース及びドレイン電極２４，２５、第１ゲート電
極１１１の部分、第１ソース及びドレイン配線１３４，
１３５を形成し、さらに露出した第２低抵抗薄膜７、第
１導電膜４のうちの金属層４２を除去して完成したもの
である。この構造例では、ＴＦＴ２の第２ドレイン電極
（データライン）２５とＴＦＴ１の第１ドレイン配線１
３５を、ＴＦＴ２の第２ソース電極２４と画素電極１６
を接続している。Similar to FIG. 3 (b), FIG. 4 (a) shows the first channel region 113, the first source / drain region 114,
After forming 115, the first source / drain regions 124 and 125, the second gate electrode 11 of the TFT 2 and the pixel electrode 16 are formed by the first conductive film 4. In this example, the first conductive film 4 has a transparent conductive film 41 such as ITO and Mo,
Although the multilayer film of the metal layer 42 of Cr, W, Ni or the like is used, only the transparent conductive film 41 may be used. FIG. 4B shows a state in which the gate insulating film 5, the second high resistance thin film 6 and the second low resistance thin film 7 are continuously deposited. FIG. 4C shows a state in which the first gate electrode part and the second channel region 13 part of the three-layer film deposited in FIG. In this example, the first source and drain electrodes 124,
A small number of co-opening holes are formed on 125 and the pixel electrode 16.
Since the gate insulating film 5 is also etched in the same shape as the second high resistance and low resistance thin films 6 and 7 formed thereon, the number of masks can be reduced. FIG. 4 (d) shows that the metal film 8 is deposited and selectively etched to form second source and drain electrodes 24 and 25, a portion of the first gate electrode 111, a first source and drain wiring 134,
This is completed by forming 135 and further removing the exposed second low resistance thin film 7 and the metal layer 42 of the first conductive film 4. In this structural example, the second drain electrode (data line) 25 of the TFT 2 and the first drain wiring 1 of the TFT 1
35 is the second source electrode 24 of the TFT 2 and the pixel electrode 16
Are connected.
(d)実施例４液晶表示装置用ＴＦＴ基板（第５図） 第５図には、本発明を第４図と同様に液晶表示装置に応
用した場合の構造例を示した。この例では、ＴＦＴ２の
第２ゲート電極１１と、ＴＦＴ１の第１ドレイン電極１
２５を接続した構造を示す。ＴＦＴ１の第１ドレイン領
域１１５はＴＦＴ２の第２ゲート電極１１の下部まで付
加ゲート電極２１として延在している。この付加ゲート
電極２１及び画素補助電極２６は第１低抵抗薄膜３で特
に工程を増さずに形成でき、配線などの冗長度を増加さ
せて欠陥の発生を抑えられる。(d) Example 4 TFT substrate for liquid crystal display device (Fig. 5) Fig. 5 shows a structural example in which the present invention is applied to a liquid crystal display device as in Fig. 4. In this example, the second gate electrode 11 of the TFT 2 and the first drain electrode 1 of the TFT 1
The structure which connected 25 is shown. The first drain region 115 of the TFT1 extends as an additional gate electrode 21 up to the bottom of the second gate electrode 11 of the TFT2. The additional gate electrode 21 and the pixel auxiliary electrode 26 can be formed by the first low-resistance thin film 3 without increasing the number of steps, and the redundancy of wirings can be increased to suppress the occurrence of defects.
以上の様に本発明によれば、a-SiＴＦＴに最適な逆スタ
ガー構造の第２ＴＦＴとビームアニールされた第１ＴＦ
Ｔを容易に混載できる。第１及び第２ＴＦＴのチャンネ
ル領域の厚みは独立に選択できるので、比較的厚く、ビ
ームアニールしやすい、チャンネル領域をもつ第１ＴＦ
Ｔに対し第２ＴＦＴは極めて薄いチャンネル領域で端光
照射性をもたせることができるなど、特性の良好化，多
様化が図れる。この様な利点のため本発明は、周辺駆動
回路を同一基板上に有したＴＦＴ液晶表示装置等a-SiＴ
ＦＴと高速ＴＦＴを混在させた装置に最適であり、それ
ぞれの長所を生かすことができる。As described above, according to the present invention, the second TFT having the inverted stagger structure, which is most suitable for the a-Si TFT, and the first TF beam-annealed.
T can be mixed easily. Since the thicknesses of the channel regions of the first and second TFTs can be independently selected, the first TF having a channel region that is relatively thick and is easy to be beam annealed.
In contrast to T, the second TFT can have edge light irradiation property in an extremely thin channel region, so that the characteristics can be improved and diversified. Due to these advantages, the present invention provides an a-SiT device such as a TFT liquid crystal display device having a peripheral drive circuit on the same substrate.
It is most suitable for the device in which FT and high-speed TFT are mixed, and each advantage can be utilized.
以上主に、a-SiＴＦＴを例に述べたが、多結晶Ｓｉ Ｔ
ＦＴや他の半導体薄膜を用いるＴＦＴにも適用できる。
また、本製造工程は第１及び第２高抵抗薄膜の材料が異
なる場合にも有効である。The description above has mainly dealt with a-Si TFTs as an example.
It can also be applied to TFTs using FT and other semiconductor thin films.
The manufacturing process is also effective when the materials of the first and second high resistance thin films are different.
第１図は本発明によるＴＦＴ装置の断面図、第２図は従
来技術によるＴＦＴの断面図、第３図(a)〜(e)は本発明
によるＴＦＴ装置の製造工程順断面図、第４図(a)〜(d)
は他の実施例によるＴＦＴの製造工程順断面図、第５図
は他のＴＦＴの実施例の断面図である。 １…基板、２…第１高抵抗半導体薄膜、３…第１低抵抗
半導体薄膜、４…第１導電膜、５…ゲート絶縁膜、６…
第２高抵抗半導体薄膜、７…第１低抵抗半導体薄膜、８
…金属膜、１１（１１１）…第２（第１）ゲート電極、
１２（１１２）…第２（第１）ゲート絶縁膜、１３（１
１３）…第２（第１）チャンネル領域、１４（１１４）
…第２（第１）ソース領域、１５（１１５）…第２（第
１）ドレイン領域、１６…画素電極、２４（１２４）…
第２（第１）ソース電極、２５（１２５）…第２（第
１）ドレイン電極1 is a cross-sectional view of a TFT device according to the present invention, FIG. 2 is a cross-sectional view of a conventional TFT, and FIGS. 3A to 3E are cross-sectional views in the order of manufacturing steps of the TFT device according to the present invention. Figures (a)-(d)
Is a sectional view in the order of manufacturing steps of a TFT according to another embodiment, and FIG. 5 is a sectional view of an embodiment of another TFT. DESCRIPTION OF SYMBOLS 1 ... Substrate, 2 ... 1st high resistance semiconductor thin film, 3 ... 1st low resistance semiconductor thin film, 4 ... 1st conductive film, 5 ... Gate insulating film, 6 ...
Second high resistance semiconductor thin film, 7 ... First low resistance semiconductor thin film, 8
... metal film, 11 (111) ... second (first) gate electrode,
12 (112) ... second (first) gate insulating film, 13 (1)
13) ... second (first) channel region, 14 (114)
... second (first) source region, 15 (115) ... second (first) drain region, 16 ... pixel electrode, 24 (124) ...
Second (first) source electrode, 25 (125) ... Second (first) drain electrode
Claims (5)
高抵抗半導体薄膜を第１チャンネル領域として有する第
１の薄膜トランジスタと、前記第１高抵抗半導体薄膜よ
り粒径の小さい非晶質もしくは多結晶の第２高抵抗半導
体薄膜を第２チャンネル領域として有する第２の薄膜ト
ランジスタとを少なく共含む薄膜トランジスタ装置にお
いて、 第１の薄膜トランジスタは、前記絶縁基板上に設けられ
た第１高抵抗半導体薄膜と前記第１高抵抗半導体薄膜に
接し互いに離間した第１低抵抗半導体薄膜から成る第１
ソース領域及び第１ドレイン領域と、前記第１ソース領
域及び第１ドレイン領域にそれぞれ接し第１導電膜より
成る第１ソース電極及び第１ドレイン電極と、前記第１
高抵抗半導体薄膜上に設けられた第１ゲート絶縁膜と、
前記第１ゲート絶縁膜上で第２高抵抗半導体薄膜、第２
低抵抗半導体薄膜、金属膜より成る第１ゲート電極を有
する構造をもち、 第２の薄膜トランジスタは、前記絶縁基板上に設けられ
た第１導電膜から成る第２ゲート電極と、前記第２ゲー
ト電極上に設けられた第２ゲート絶縁膜と、前記第２ゲ
ート絶縁膜上の第２高抵抗半導体薄膜と、前記第２高抵
抗薄膜半導体の表面で互いに離間して設けられた第２低
抵抗半導体薄膜から成る第２ソース領域及び第２ドレイ
ン領域と、前記第２ソース領域及び第２ドレイン領域に
それぞれ接する金属膜から成る第２ソース電極と第２ド
レイン電極とを有する構造をもつことを特徴とする薄膜
トランジスタ装置。1. An insulating substrate and a polycrystalline or single crystal first
A first thin film transistor having a high resistance semiconductor thin film as a first channel region, and a second thin film transistor having an amorphous or polycrystalline second high resistance semiconductor thin film having a grain size smaller than that of the first high resistance semiconductor thin film as a second channel region. In a thin film transistor device including at least two second thin film transistors, the first thin film transistor includes a first high resistance semiconductor thin film provided on the insulating substrate and a first low resistance semiconductor which is in contact with the first high resistance semiconductor thin film and is separated from each other. First made of thin film
A source region and a first drain region, a first source electrode and a first drain electrode which are in contact with the first source region and the first drain region, and which are made of a first conductive film;
A first gate insulating film provided on the high resistance semiconductor thin film;
A second high resistance semiconductor thin film on the first gate insulating film;
The second thin film transistor has a structure having a low resistance semiconductor thin film and a first gate electrode made of a metal film, and a second gate electrode made of a first conductive film provided on the insulating substrate, and the second gate electrode. A second gate insulating film provided above, a second high resistance semiconductor thin film on the second gate insulating film, and a second low resistance semiconductor provided on the surface of the second high resistance thin film semiconductor so as to be separated from each other. It has a structure having a second source region and a second drain region made of a thin film, and a second source electrode and a second drain electrode made of a metal film in contact with the second source region and the second drain region, respectively. Thin film transistor device.
部に含み、第２の薄膜トランジスタの第２ソース電極に
は前記第１導電膜により形成された画素電極が接続され
ていることを特徴とする特許請求の範囲第１項記載の薄
膜トランジスタ装置。2. The first conductive film includes a transparent conductive film in a small amount in a part thereof, and a pixel electrode formed by the first conductive film is connected to a second source electrode of a second thin film transistor. The thin film transistor device according to claim 1, wherein:
２の薄膜トランジスタを少なく共有する薄膜トランジス
タ装置の製造方法において、 (a)前記絶縁基板上に非晶質もしくは多結晶半導体薄膜
を堆積し、エネルギービームを照射して粒径の大きい多
結晶または単結晶の第１高抵抗半導体薄膜を形成する第
１工程と、 (b)前記第１高抵抗半導体薄膜を第１の薄膜トランジス
タの第１チャンネル領域とし、前記第１チャンネル領域
に接し互いに離間する第１低抵抗半導体薄膜より成る第
１ソース領域及び第１ドレイン領域を形成し、前記第１
チャンネル領域、第１ソース領域、第１ドレイン領域を
残して前記絶縁基板を露出する第２工程と、 (c)第１導電膜を堆積し、選択エッチングすることによ
り、第１ソース領域及び第１ドレイン領域にそれぞれ接
する第１ソース電極及び第１ドレイン電極を設けると共
に、露出した前記絶縁基板上に第２の薄膜トランジスタ
の第２ゲート電極を形成する第３工程と、 (d)絶縁膜の堆積に続き、非晶質または多結晶の第２高
抵抗半導体薄膜さらに第２低抵抗半導体薄膜を連続して
堆積する第４工程と、 (e)前記第２低抵抗半導体薄膜及び第２高抵抗半導体薄
膜を選択エッチングすることにより、前記第１チャンネ
ル領域上に第１島状領域を形成するとともに、前記第２
ゲート電極上に第２島状領域を形成する第５工程と、 (f)前記第５工程により露出した絶縁膜を選択エッチン
グすることにより、前記第１ソース電極上及び第１ドレ
イン電極上にコンタクト開孔を設ける第６工程と、 (g)金属膜を堆積し、選択エッチングすることにより、
第１島状領域上に第１ゲート電極と、第２島状領域に接
する第２ソース電極及び第２ドレイン電極を形成する第
７工程と、 (h)前記第７工程により露出した第２低抵抗半導体薄膜
を、前記金属膜をマスクとして選択除去する第８工程と より成る薄膜トランジスタ装置の製造方法。3. A method of manufacturing a thin film transistor device in which a first thin film transistor and a second thin film transistor are shared on an insulating substrate in a small amount, comprising: (a) depositing an amorphous or polycrystalline semiconductor thin film on the insulating substrate, A first step of irradiating a beam to form a polycrystalline or single crystal first high-resistance semiconductor thin film having a large grain size; (b) using the first high-resistance semiconductor thin film as a first channel region of a first thin film transistor Forming a first source region and a first drain region formed of a first low resistance semiconductor thin film in contact with the first channel region and spaced apart from each other;
A second step of exposing the insulating substrate leaving the channel region, the first source region, and the first drain region, and (c) depositing the first conductive film and performing selective etching to remove the first source region and the first source region. A third step of forming a second gate electrode of a second thin film transistor on the exposed insulating substrate while providing a first source electrode and a first drain electrode respectively in contact with the drain region; and (d) depositing an insulating film. A fourth step of continuously depositing an amorphous or polycrystalline second high-resistance semiconductor thin film and a second low-resistance semiconductor thin film, and (e) the second low-resistance semiconductor thin film and the second high-resistance semiconductor thin film Is selectively etched to form a first island-shaped region on the first channel region and the second island region is formed.
A fifth step of forming a second island-shaped region on the gate electrode, and (f) contacting the first source electrode and the first drain electrode by selectively etching the insulating film exposed in the fifth step. By the sixth step of forming an opening and (g) depositing a metal film and performing selective etching,
A seventh step of forming a first gate electrode and a second source electrode and a second drain electrode in contact with the second island area on the first island area; and (h) a second low level exposed by the seventh step. 8. A method of manufacturing a thin film transistor device, comprising the eighth step of selectively removing the resistive semiconductor thin film by using the metal film as a mask.
く共一部を透明導電膜とし、第２ゲート電極に離間した
第１導電膜より成る画素電極を形成し、前記第６工程に
おいて画素電極上にコンタクト開孔を設け、前記第７工
程において画素電極と第２ソース電極間の配線を前記金
属膜で設けることを特徴とする特許請求の範囲第３項記
載の薄膜トランジスタ装置の製造方法。4. In the third step, at least a part of the first conductive film is a transparent conductive film, and a pixel electrode made of a separated first conductive film is formed in the second gate electrode, and in the sixth step. 4. The method of manufacturing a thin film transistor device according to claim 3, wherein a contact opening is provided on the pixel electrode, and the wiring between the pixel electrode and the second source electrode is provided by the metal film in the seventh step. .
２島状領域をマスクとして前記第６工程のコンタクト開
孔を行うことを特徴とする特許請求の範囲第３項または
第４項記載の薄膜トランジスタ装置の製造方法。5. A contact opening according to claim 6, wherein the first and second island-shaped regions formed in the fifth step are used as a mask to carry out the contact opening in the sixth step. Of manufacturing a thin film transistor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60212965A JPH0650779B2 (en) | 1985-09-26 | 1985-09-26 | Thin film transistor device and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60212965A JPH0650779B2 (en) | 1985-09-26 | 1985-09-26 | Thin film transistor device and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6273658A JPS6273658A (en) | 1987-04-04 |
| JPH0650779B2 true JPH0650779B2 (en) | 1994-06-29 |
Family
ID=16631222
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60212965A Expired - Lifetime JPH0650779B2 (en) | 1985-09-26 | 1985-09-26 | Thin film transistor device and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0650779B2 (en) |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2776820B2 (en) * | 1988-01-27 | 1998-07-16 | ソニー株式会社 | Method for manufacturing semiconductor device |
| JP2717234B2 (en) * | 1991-05-11 | 1998-02-18 | 株式会社 半導体エネルギー研究所 | Insulated gate field effect semiconductor device and method of manufacturing the same |
| JP2717237B2 (en) | 1991-05-16 | 1998-02-18 | 株式会社 半導体エネルギー研究所 | Insulated gate semiconductor device and method of manufacturing the same |
| JP2845303B2 (en) * | 1991-08-23 | 1999-01-13 | 株式会社 半導体エネルギー研究所 | Semiconductor device and manufacturing method thereof |
| US5485019A (en) | 1992-02-05 | 1996-01-16 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for forming the same |
| JPH0792500A (en) * | 1993-06-29 | 1995-04-07 | Toshiba Corp | Semiconductor device |
| KR20070081829A (en) | 2006-02-14 | 2007-08-20 | 삼성전자주식회사 | Organic light emitting diode display and method for manufacturing the same |
| WO2011142147A1 (en) * | 2010-05-13 | 2011-11-17 | シャープ株式会社 | Circuit board and display device |
-
1985
- 1985-09-26 JP JP60212965A patent/JPH0650779B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6273658A (en) | 1987-04-04 |
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