JPH0637249A - Mounting structure for capacitor - Google Patents
Mounting structure for capacitorInfo
- Publication number
- JPH0637249A JPH0637249A JP19243092A JP19243092A JPH0637249A JP H0637249 A JPH0637249 A JP H0637249A JP 19243092 A JP19243092 A JP 19243092A JP 19243092 A JP19243092 A JP 19243092A JP H0637249 A JPH0637249 A JP H0637249A
- Authority
- JP
- Japan
- Prior art keywords
- capacitor
- pad
- pin
- land
- power supply
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
Landscapes
- Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体素子が実装され
るプリント基板に於けるキャパシタの取付構造に関す
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a capacitor mounting structure on a printed circuit board on which a semiconductor element is mounted.
【０００２】近年、コンピュータなどの電子装置に於け
る高速化が図られるようになり、ノイズによる障害がク
ローズアップされるようになった。そこで、電子装置を
構成する半導体素子が実装されるプリント基板にはノイ
ズを除去するキャパシタの取付が行われている。In recent years, the speed of electronic devices such as computers has increased, and obstacles due to noise have come to the fore. Therefore, a capacitor for removing noise is attached to a printed circuit board on which a semiconductor element that constitutes an electronic device is mounted.
【０００３】[0003]
【従来の技術】従来は、図３の従来の側面断面図に示す
ように形成されていた。図３に示すように、パッド2 が
配列されたプリント基板1 のパッド2 にはランド4 に固
着されたピン5 を有する半導体パッケージ3 のピン5 を
ボンディングすることで、プリント基板1 に半導体パッ
ケージ3 を実装するように形成されていた。2. Description of the Related Art Conventionally, it is formed as shown in the conventional side sectional view of FIG. As shown in FIG. 3, by bonding the pin 5 of the semiconductor package 3 having the pin 5 fixed to the land 4 to the pad 2 of the printed circuit board 1 on which the pads 2 are arranged, the semiconductor package 3 is mounted on the printed circuit board 1. Was formed to implement.
【０００４】また、このようなパッド2 には信号S の接
続を行う導電パターン10A と、所定の電位の電源V の接
続を行う導電パターン10B と、アース電源G の接続を行
う導電パターン10C とが設けられ、電源供給路に於ける
ノイズを除去するよう導電パターン10B と、10C との間
にキャパシタ6 の挿入が行われていた。Further, a conductive pattern 10A for connecting a signal S, a conductive pattern 10B for connecting a power source V of a predetermined potential, and a conductive pattern 10C for connecting a ground power source G are connected to such a pad 2. The capacitor 6 is provided between the conductive patterns 10B and 10C so as to remove noise in the power supply path.
【０００５】この場合、キャパシタ6 の挿入は、プリン
ト基板1 の所定箇所に導電パターン10B と、10C とのそ
れぞれに接続される中継パッド11を設け、中継パッド11
にキャパシタ6 の電極6Aをボンディングすることで行わ
れていた。In this case, when the capacitor 6 is inserted, the relay pad 11 connected to each of the conductive patterns 10B and 10C is provided at a predetermined position of the printed board 1, and the relay pad 11 is inserted.
It was done by bonding the electrode 6A of the capacitor 6 to.
【０００６】[0006]
【発明が解決しようとする課題】しかし、このような中
継パッド11にキャパシタ6 の電極6Aを固着させることで
は、図３に示すように、中継パッド11と導電パターン10
B とを接続するA 部に示す接続部と、中継パッド11と導
電パターン10C とを接続するB 部に示す接続部とが必要
となる。However, by fixing the electrode 6A of the capacitor 6 to the relay pad 11 as described above, as shown in FIG. 3, the relay pad 11 and the conductive pattern 10 are formed.
A connection part shown in part A for connecting B and a connection part shown in part B for connecting relay pad 11 and conductive pattern 10C are required.
【０００７】したがって、実際には、A,B に示す接続部
の線路長によるL が加わり、特に、多層化されたプリン
ト基板1 では、キャパシタ6 によるノイズを除去する効
率が低下する問題を有していた。Therefore, in practice, L due to the line length of the connecting portion shown by A and B is added, and particularly in the multilayer printed circuit board 1, there is a problem that the efficiency of removing noise by the capacitor 6 is lowered. Was there.
【０００８】そこで、本発明では、ノイズの除去効果の
向上を図ることを目的とする。Therefore, an object of the present invention is to improve the noise removing effect.
【０００９】[0009]
【課題を解決するための手段】図１は本発明の原理説明
図であり、図１に示すように、パッド2 が配設されるプ
リント基板1 と、ピン5 が固着されるランド4 を配列
し、該パッド2 に該ピン5 がボンディングされることで
該プリント基板1 に実装される半導体パッケージ3 とを
備え、前記ピン5 と、前記パッド2 とを介してアース電
源Ｇの接続される前記ランド4 と、該ピン5 と、該パッ
ド2 とを介して所定の電位を有する電源Ｖの接続が行わ
れる該ランド4 との二組の間にノイズを除去するキャパ
シタ6 が固着されるように構成する。FIG. 1 is a diagram for explaining the principle of the present invention. As shown in FIG. 1, a printed board 1 on which a pad 2 is arranged and a land 4 to which a pin 5 is fixed are arranged. And a semiconductor package 3 mounted on the printed circuit board 1 by bonding the pin 5 to the pad 2 and connecting the earth power source G via the pin 5 and the pad 2. A capacitor 6 for removing noise is fixed between two sets of the land 4, the pin 5, and the land 4 to which a power source V having a predetermined potential is connected via the pad 2. Constitute.
【００１０】このように構成することによって前述の課
題は解決される。The above-mentioned problems can be solved by such a configuration.
【００１１】[0011]
【作用】即ち、電源V とアース電源G とが接続される半
導体パッケージ3 のランド4 間にノイズを除去するキャ
パシタ6 の固着を行い、電源V とアース電源G との間に
キャパシタ6 の挿入が行われるようにしたものである。[Function] That is, the capacitor 6 for removing noise is fixed between the land 4 of the semiconductor package 3 to which the power supply V and the ground power supply G are connected, and the capacitor 6 is inserted between the power supply V and the ground power supply G. It was done.
【００１２】したがって、前述のようなキャパシタ6 を
固着するための中継パッド11をプリント基板1 に設ける
よう接続部を形成する必要がなく、接続部の線路長によ
るLの影響がなくなり、キャパシタ6 によるノイズの除
去効果を向上させることができる。Therefore, it is not necessary to form the connecting portion so that the relay pad 11 for fixing the capacitor 6 as described above is provided on the printed circuit board 1, and the influence of L due to the line length of the connecting portion is eliminated. The effect of removing noise can be improved.
【００１３】[0013]
【実施例】以下本発明を図２を参考に詳細に説明する。
図２は本発明による一実施例の説明図で、(a) は側面断
面図,(b)はランドの要部拡大図である。全図を通じて、
同一符号は同一対象物を示す。The present invention will be described in detail below with reference to FIG.
2A and 2B are explanatory views of an embodiment according to the present invention. FIG. 2A is a side sectional view and FIG. 2B is an enlarged view of a main part of a land. Throughout the figure,
The same reference numeral indicates the same object.
【００１４】図２の(a) に示すように、半導体パッケー
ジ3 のピン5 をプリント基板1 のパッド2 にボンディン
グすることで半導体パッケージ3 がプリント基板1 に実
装される時、半導体パッケージ3 の背面3Aに配列され、
ピン5 の固着を行う所定のランド4 間にキャパシタ6 を
固着させるように形成したものである。As shown in FIG. 2A, when the semiconductor package 3 is mounted on the printed circuit board 1 by bonding the pin 5 of the semiconductor package 3 to the pad 2 of the printed circuit board 1, the back surface of the semiconductor package 3 is mounted. Arranged in 3A,
The capacitor 6 is formed so as to be fixed between the predetermined lands 4 for fixing the pin 5.
【００１５】また、この場合、一方のランド4 には電源
V の接続を行う導電パターン10B が接続され、他方のラ
ンド4 にはアース電源G の接続を行う導電パターン10C
が接続されるように形成さている。Further, in this case, one land 4 has a power source.
Conductive pattern 10B for connecting V is connected, and conductive pattern 10C for connecting the ground power supply G is connected to the other land 4
Are formed to be connected.
【００１６】通常、半導体パッケージ3 に信号S,電源V
およびアース電源G の接続を行う場合は、図２の(b) に
示すように、電源V およびアース電源G の接続はピン5
の格子状に配列した対角に行われ、電源V およびアース
電源G の接続が行われた隣接箇所に信号S の接続が行わ
れるように接続され、電源V およびアース電源G の接続
される互いのランド4 間の距離を広くするように配慮さ
れている。Normally, the semiconductor package 3 has a signal S and a power supply V
And the ground power supply G are connected, pin 5 is connected to the power supply V and the ground power supply G as shown in Fig. 2 (b).
Connected diagonally and connected so that signal V is connected to adjacent points where power supply V and ground power supply G are connected, and power supply V and ground power supply G are connected to each other. Consideration has been given to widen the distance between the four lands.
【００１７】そこで、キャパシタ6 の固着は、キャパシ
タ6 を固着すべきランド4 には予め、保持ランド7 を形
成し、保持ランド7 にキャパシタ6 の電極6Aをボンディ
ングすることで行い、確実にキャパシタ6 の固着を行う
ようにする。Therefore, the capacitor 6 is fixed by forming the holding land 7 in advance on the land 4 to which the capacitor 6 should be fixed and bonding the electrode 6A of the capacitor 6 to the holding land 7 to surely fix the capacitor 6 Be sure to fix them.
【００１８】このように構成すると、従来のようなキャ
パシタ6 を固着するよう中継パッド11をプリント基板1
に設ける必要がなく、また、中継パッド11に接続される
接続部による線路長のL の影響を受けることがないの
で、従来の中継パッド11にキャパシタ6 を固着した場合
に比較してL 成分を小さくすることができ、インピーダ
ンスが低くなることでノイズの除去効率が向上されるこ
とが明である。With this configuration, the relay pad 11 is fixed to the printed circuit board 1 so as to fix the conventional capacitor 6.
Since it is not necessary to provide it on the relay pad 11 and it is not affected by the line length L due to the connection part connected to the relay pad 11, the L component is compared to the case where the capacitor 6 is fixed to the conventional relay pad 11. It can be made smaller, and it is apparent that the efficiency of removing noise is improved by lowering the impedance.
【００１９】[0019]
【発明の効果】以上説明したように、本発明によれば、
電源およびアース電源の接続が行われる半導体パッケー
ジのランド間にキャパシタの固着を行うことで、キャパ
シタによるノイズの除去効率の向上が図れる。As described above, according to the present invention,
By fixing the capacitors between the lands of the semiconductor package to which the power source and the ground power source are connected, the efficiency of noise removal by the capacitors can be improved.
【００２０】また、従来のような中継パッドが不要とな
り、特に、多数のキャパシタの固着が必要となる場合
は、容易にキャパシタの固着が行え、しかも、キャパシ
タを固着するための、スペースが不要となり、実装効率
の向上が図れ、実用的効果は大である。Further, the conventional relay pad becomes unnecessary, and particularly when a large number of capacitors need to be fixed, the capacitors can be easily fixed, and the space for fixing the capacitors is not necessary. , The mounting efficiency can be improved, and the practical effect is great.
【図１】 本発明の原理説明図FIG. 1 is an explanatory view of the principle of the present invention.
【図２】 本発明による一実施例の説明図FIG. 2 is an explanatory diagram of an embodiment according to the present invention.
【図３】 従来の説明図FIG. 3 is a conventional explanatory diagram.
１ プリント基板 ２ パッド ３ 半導体パッケージ ４ ランド ５ ピン ６ キャパシタ 1 Printed Circuit Board 2 Pad 3 Semiconductor Package 4 Land 5 Pin 6 Capacitor
Claims (1)
(1) と、ピン(5) が固着されるランド(4) を配列し、該
パッド(2) に該ピン(5) がボンディングされることで該
プリント基板(1) に実装される半導体パッケージ(3) と
を備え、前記ピン(5) と、前記パッド(2) とを介してア
ース電源Ｇの接続される前記ランド(4)と、該ピン(5)
と、該パッド(2) とを介して所定の電位を有する電源Ｖ
の接続が行われる該ランド(4) との二組の間にノイズを
除去するキャパシタ(6) が固着されることを特徴とする
キャパシタの取付構造。1. A printed circuit board on which a pad (2) is arranged.
A semiconductor package mounted on the printed circuit board (1) by arranging (1) and a land (4) to which the pin (5) is fixed, and bonding the pin (5) to the pad (2). (3), the land (4) to which the ground power supply G is connected via the pin (5) and the pad (2), and the pin (5)
And a power source V having a predetermined potential via the pad (2)
A structure for mounting a capacitor, wherein a capacitor (6) for removing noise is fixed between two sets of the land (4) to which is connected.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19243092A JPH0637249A (en) | 1992-07-20 | 1992-07-20 | Mounting structure for capacitor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19243092A JPH0637249A (en) | 1992-07-20 | 1992-07-20 | Mounting structure for capacitor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0637249A true JPH0637249A (en) | 1994-02-10 |
Family
ID=16291184
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19243092A Pending JPH0637249A (en) | 1992-07-20 | 1992-07-20 | Mounting structure for capacitor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0637249A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6369443B1 (en) | 1999-07-21 | 2002-04-09 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device with stacked vias |
| US6873035B2 (en) | 2000-12-15 | 2005-03-29 | Renesas Technology Corp. | Semiconductor device having capacitors for reducing power source noise |
| JP2006173407A (en) * | 2004-12-16 | 2006-06-29 | Fujitsu Ltd | Semiconductor device and its manufacturing method |
-
1992
- 1992-07-20 JP JP19243092A patent/JPH0637249A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6369443B1 (en) | 1999-07-21 | 2002-04-09 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device with stacked vias |
| US6873035B2 (en) | 2000-12-15 | 2005-03-29 | Renesas Technology Corp. | Semiconductor device having capacitors for reducing power source noise |
| US7233065B2 (en) | 2000-12-15 | 2007-06-19 | Renesas Technology Corp. | Semiconductor device having capacitors for reducing power source noise |
| US7319268B2 (en) | 2000-12-15 | 2008-01-15 | Renesas Technology Corp | Semiconductor device having capacitors for reducing power source noise |
| JP2006173407A (en) * | 2004-12-16 | 2006-06-29 | Fujitsu Ltd | Semiconductor device and its manufacturing method |
| JP4571487B2 (en) * | 2004-12-16 | 2010-10-27 | 富士通セミコンダクター株式会社 | Semiconductor device and manufacturing method thereof |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20000307 |